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/freebsd/sys/compat/linuxkpi/common/include/linux/
H A Dbitops.h128 int bit; in find_first_bit() local
143 return (bit); in find_first_bit()
150 int bit; in find_first_zero_bit() local
173 int bit; in find_last_bit() local
199 int bit; in find_next_bit() local
239 int bit; in find_next_zero_bit() local
298 bit = (1UL << bit); in test_and_clear_bit()
313 bit = (1UL << bit); in __test_and_clear_bit()
328 bit = (1UL << bit); in test_and_set_bit()
343 bit = (1UL << bit); in __test_and_set_bit()
[all …]
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DMSP430Target.def179 // With 16-bit hardware multiplier
180 MSP430_MCU_FEAT("msp430f147", "16bit")
181 MSP430_MCU_FEAT("msp430f148", "16bit")
182 MSP430_MCU_FEAT("msp430f149", "16bit")
186 MSP430_MCU_FEAT("msp430f167", "16bit")
187 MSP430_MCU_FEAT("msp430f168", "16bit")
188 MSP430_MCU_FEAT("msp430f169", "16bit")
192 MSP430_MCU_FEAT("msp430c336", "16bit")
193 MSP430_MCU_FEAT("msp430c337", "16bit")
194 MSP430_MCU_FEAT("msp430e337", "16bit")
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H A DBuiltinsRISCV.def20 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "UWiUWi", "nc", "zbb,64bit")
24 TARGET_BUILTIN(__builtin_riscv_ctz_64, "UiUWi", "nc", "zbb,64bit")
31 TARGET_BUILTIN(__builtin_riscv_clmulr_32, "UiUiUi", "nc", "zbc,32bit")
32 TARGET_BUILTIN(__builtin_riscv_clmulr_64, "UWiUWiUWi", "nc", "zbc,64bit")
35 TARGET_BUILTIN(__builtin_riscv_xperm4_32, "UiUiUi", "nc", "zbkx,32bit")
37 TARGET_BUILTIN(__builtin_riscv_xperm8_32, "UiUiUi", "nc", "zbkx,32bit")
42 TARGET_BUILTIN(__builtin_riscv_brev8_64, "UWiUWi", "nc", "zbkb,64bit")
43 TARGET_BUILTIN(__builtin_riscv_zip_32, "UiUi", "nc", "zbkb,32bit")
44 TARGET_BUILTIN(__builtin_riscv_unzip_32, "UiUi", "nc", "zbkb,32bit")
49 TARGET_BUILTIN(__builtin_riscv_aes64ds, "UWiUWiUWi", "nc", "zknd,64bit")
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H A DBuiltinsLoongArchBase.def15 TARGET_BUILTIN(__builtin_loongarch_cacop_d, "vWiUWiWi", "nc", "64bit")
16 TARGET_BUILTIN(__builtin_loongarch_cacop_w, "viUii", "nc", "32bit")
24 TARGET_BUILTIN(__builtin_loongarch_asrtle_d, "vWiWi", "nc", "64bit")
25 TARGET_BUILTIN(__builtin_loongarch_asrtgt_d, "vWiWi", "nc", "64bit")
27 TARGET_BUILTIN(__builtin_loongarch_crc_w_b_w, "iii", "nc", "64bit")
28 TARGET_BUILTIN(__builtin_loongarch_crc_w_h_w, "iii", "nc", "64bit")
29 TARGET_BUILTIN(__builtin_loongarch_crc_w_w_w, "iii", "nc", "64bit")
30 TARGET_BUILTIN(__builtin_loongarch_crc_w_d_w, "iWii", "nc", "64bit")
31 TARGET_BUILTIN(__builtin_loongarch_crcc_w_b_w, "iii", "nc", "64bit")
32 TARGET_BUILTIN(__builtin_loongarch_crcc_w_h_w, "iii", "nc", "64bit")
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmc13xxx.txt55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
86 sw1 : regulator SW1 (register 24, bit 0)
87 sw2 : regulator SW2 (register 25, bit 0)
88 sw3 : regulator SW3 (register 26, bit 0)
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/freebsd/contrib/file/magic/Magdir/
H A Dispell17 >2 leshort 0x00 8-bit, no capitalization, 26 flags
18 >2 leshort 0x01 7-bit, no capitalization, 26 flags
19 >2 leshort 0x02 8-bit, capitalization, 26 flags
20 >2 leshort 0x03 7-bit, capitalization, 26 flags
23 >2 leshort 0x06 8-bit, capitalization, 52 flags
24 >2 leshort 0x07 7-bit, capitalization, 52 flags
27 >2 leshort 0x0A 8-bit, capitalization, 128 flags
28 >2 leshort 0x0B 7-bit, capitalization, 128 flags
31 >2 leshort 0x0E 8-bit, capitalization, 256 flags
41 >2 beshort 0x02 8-bit, capitalization, 26 flags
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H A Dmach11 # it's also separate from the "64-bit libraries" bit in the
20 # 32-bit ABIs.
153 # 64-bit ABIs.
155 >>0 belong&0x00ffffff 0 64-bit architecture=%d
156 >>0 belong&0x00ffffff 1 64-bit architecture=%d
157 >>0 belong&0x00ffffff 2 64-bit architecture=%d
158 >>0 belong&0x00ffffff 3 64-bit architecture=%d
159 >>0 belong&0x00ffffff 4 64-bit architecture=%d
209 # 64_32-bit ABIs.
223 >>0 belong&0x00ffffff 12 64_32-bit arm
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H A Ddyadic21 >>>1 byte 0x01 component file 32-bit non-journaled non-checksummed
27 >>>>7 byte&0x28 0x00 32-bit
28 >>>>7 byte&0x28 0x20 64-bit
36 >>>1 byte 0x08 mapped file 32-bit
37 >>>1 byte 0x09 component file 64-bit non-journaled non-checksummed
38 >>>1 byte 0x0a mapped file 64-bit
41 >>>1 byte 0x0d component file 32-bit level 1 journaled checksummed
42 >>>1 byte 0x0e component file 64-bit level 1 journaled checksummed
43 >>>1 byte 0x0f component file 32-bit level 2 journaled checksummed
47 >>>1 byte 0x13 component file 32-bit non-journaled checksummed
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/freebsd/contrib/jemalloc/include/jemalloc/internal/
H A Dbitmap.h225 bit = goff; in bitmap_set()
246 size_t bit = 0; in bitmap_ffu() local
281 return bit; in bitmap_ffu()
286 size_t bit; in bitmap_ffu() local
288 bit = ffs_lu(g); in bitmap_ffu()
289 if (bit != 0) { in bitmap_ffu()
302 size_t bit; in bitmap_sfu() local
315 bit = (bit << LG_BITMAP_GROUP_NBITS) + (ffs_lu(g) - 1); in bitmap_sfu()
324 bit = (i << LG_BITMAP_GROUP_NBITS) + (bit - 1); in bitmap_sfu()
327 return bit; in bitmap_sfu()
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/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Drenesas,cmt.yaml42 - renesas,r8a7742-cmt0 # 32-bit CMT0 on RZ/G1H
43 - renesas,r8a7743-cmt0 # 32-bit CMT0 on RZ/G1M
44 - renesas,r8a7744-cmt0 # 32-bit CMT0 on RZ/G1N
45 - renesas,r8a7745-cmt0 # 32-bit CMT0 on RZ/G1E
46 - renesas,r8a77470-cmt0 # 32-bit CMT0 on RZ/G1C
57 - renesas,r8a7742-cmt1 # 48-bit CMT1 on RZ/G1H
58 - renesas,r8a7743-cmt1 # 48-bit CMT1 on RZ/G1M
59 - renesas,r8a7744-cmt1 # 48-bit CMT1 on RZ/G1N
60 - renesas,r8a7745-cmt1 # 48-bit CMT1 on RZ/G1E
61 - renesas,r8a77470-cmt1 # 48-bit CMT1 on RZ/G1C
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/freebsd/contrib/sendmail/include/sm/
H A Dbitops.h34 # define _BITWORD(bit) (((unsigned char)(bit) / (BYTEBITS * sizeof (int))) & BITMAPMAX) argument
35 # define _BITBIT(bit) ((unsigned int)1 << ((unsigned char)(bit) % (BYTEBITS * sizeof (int)))) argument
40 # define bitidx(bit) ((unsigned int) (bit) & 0xff) argument
43 # define bitnset(bit, map) ((map)[_BITWORD(bit)] & _BITBIT(bit)) argument
46 # define setbitn(bit, map) (map)[_BITWORD(bit)] |= _BITBIT(bit) argument
49 # define clrbitn(bit, map) (map)[_BITWORD(bit)] &= ~_BITBIT(bit) argument
55 # define bitset(bit, word) (((word) & (bit)) != 0) argument
/freebsd/sys/contrib/device-tree/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
H A Dstm32f7-rcc.h34 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) argument
45 #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) argument
46 #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) argument
52 #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) argument
53 #define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) argument
87 #define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) argument
88 #define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80) argument
112 #define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) argument
113 #define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) argument
H A Dstm32h7-rcc.h17 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) argument
28 #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8)) argument
37 #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8)) argument
56 #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) argument
62 #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8)) argument
90 #define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8)) argument
99 #define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8)) argument
118 #define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8)) argument
134 #define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8)) argument
/freebsd/sys/powerpc/fpu/
H A Dfpu_sqrt.c285 bit = FP_1; in fpu_sqrt()
288 q = bit; in fpu_sqrt()
289 x0 -= bit; in fpu_sqrt()
313 t1 = bit; in fpu_sqrt()
329 q |= bit; in fpu_sqrt()
344 t2 = bit; in fpu_sqrt()
350 q = bit; in fpu_sqrt()
362 q |= bit; in fpu_sqrt()
377 t3 = bit; in fpu_sqrt()
384 q = bit; in fpu_sqrt()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td17 field bit SALU = 0;
18 field bit VALU = 0;
21 field bit SOP1 = 0;
22 field bit SOP2 = 0;
23 field bit SOPC = 0;
35 field bit DPP = 0;
47 field bit DS = 0;
282 bit UseExec = 0, bit DefExec = 0> :
348 bit d16;
415 bit d16;
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/freebsd/crypto/openssl/doc/man3/
H A DOPENSSL_ia32cap.pod24 =item bit #4 denoting presence of Time-Stamp Counter.
30 =item bit #23 denoting MMX support;
32 =item bit #24, FXSR bit, denoting availability of XMM registers;
34 =item bit #25 denoting SSE support;
36 =item bit #26 denoting SSE2 support;
51 =item bit #57 denoting AES-NI instruction set extension;
53 =item bit #58, XSAVE bit, lack of which in combination with MOVBE is used
56 =item bit #59, OSXSAVE bit, denoting availability of YMM registers;
58 =item bit #60 denoting AVX extension;
64 For example, in 32-bit application context clearing bit #26 at run-time
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/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/ELFRelocs/
H A DM68k.def6 ELF_RELOC(R_68K_32, 1) /* Direct 32 bit */
7 ELF_RELOC(R_68K_16, 2) /* Direct 16 bit */
8 ELF_RELOC(R_68K_8, 3) /* Direct 8 bit */
9 ELF_RELOC(R_68K_PC32, 4) /* PC relative 32 bit */
10 ELF_RELOC(R_68K_PC16, 5) /* PC relative 16 bit */
11 ELF_RELOC(R_68K_PC8, 6) /* PC relative 8 bit */
15 ELF_RELOC(R_68K_GOTOFF32, 10) /* 32 bit GOT offset */
16 ELF_RELOC(R_68K_GOTOFF16, 11) /* 16 bit GOT offset */
17 ELF_RELOC(R_68K_GOTOFF8, 12) /* 8 bit GOT offset */
21 ELF_RELOC(R_68K_PLTOFF32, 16) /* 32 bit PLT offset */
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td16 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
18 def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
19 def WriteIMul32 : SchedWrite; // 32-bit multiply on RV64I
48 def WriteFDiv16 : SchedWrite; // 16-bit floating point divide
49 def WriteFDiv32 : SchedWrite; // 32-bit floating point divide
51 def WriteFSqrt16 : SchedWrite; // 16-bit floating point sqrt
52 def WriteFSqrt32 : SchedWrite; // 32-bit floating point sqrt
53 def WriteFSqrt64 : SchedWrite; // 64-bit floating point sqrt
161 def ReadFSqrt16 : SchedRead; // 16-bit floating point sqrt
162 def ReadFSqrt32 : SchedRead; // 32-bit floating point sqrt
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/freebsd/sys/dev/axgbe/
H A Dxgbe_osdep.h61 (bit) < (size); \
62 (bit) = find_next_bit((addr), (size), (bit) + 1))
256 int bit; in find_next_bit() local
263 bit = BITS_PER_LONG * pos; in find_next_bit()
268 return (bit + __ffsl(mask)); in find_next_bit()
271 bit += BITS_PER_LONG; in find_next_bit()
283 bit += __ffsl(mask); in find_next_bit()
285 bit += size; in find_next_bit()
287 return (bit); in find_next_bit()
294 int bit; in find_first_bit() local
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/freebsd/cddl/contrib/opensolaris/cmd/dtrace/test/cmd/baddof/
H A Dbaddof.c58 int bit, i; in corrupt() local
70 for (bit = 0; bit < len * 8; bit++) { in corrupt()
71 saved = buf[bit / 8]; in corrupt()
72 buf[bit / 8] ^= (1 << (bit % 8)); in corrupt()
74 if ((bit % 100) == 0) in corrupt()
75 printf("%d\n", bit); in corrupt()
81 buf[bit / 8] = saved; in corrupt()
94 buf[bit / 8] = saved; in corrupt()
112 buf[bit / 8] = saved; in corrupt()
128 pos[i] = bit / 8; in corrupt()
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap24xx-clocks.dtsi12 ti,bit-shift = <2>;
26 ti,bit-shift = <6>;
78 ti,bit-shift = <23>;
94 ti,bit-shift = <6>;
103 ti,bit-shift = <6>;
132 ti,bit-shift = <2>;
142 ti,bit-shift = <6>;
152 ti,bit-shift = <5>;
180 ti,bit-shift = <3>;
196 ti,bit-shift = <7>;
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/freebsd/sys/contrib/device-tree/Bindings/crypto/
H A Dfsl-sec2.txt20 bit 0 = reserved - should be 0
21 bit 1 = set if SEC has the ARC4 EU (AFEU)
22 bit 2 = set if SEC has the DES/3DES EU (DEU)
23 bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
24 bit 4 = set if SEC has the random number generator EU (RNG)
25 bit 5 = set if SEC has the public key EU (PKEU)
26 bit 6 = set if SEC has the AES EU (AESU)
27 bit 7 = set if SEC has the Kasumi EU (KEU)
28 bit 8 = set if SEC has the CRC EU (CRCU)
39 bit 1 = set if SEC supports the ipsec_esp descriptor type
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/freebsd/contrib/wpa/src/utils/
H A Dbitfield.c40 void bitfield_set(struct bitfield *bf, size_t bit) in bitfield_set() argument
42 if (bit >= bf->max_bits) in bitfield_set()
44 bf->bits[bit / 8] |= BIT(bit % 8); in bitfield_set()
48 void bitfield_clear(struct bitfield *bf, size_t bit) in bitfield_clear() argument
50 if (bit >= bf->max_bits) in bitfield_clear()
52 bf->bits[bit / 8] &= ~BIT(bit % 8); in bitfield_clear()
56 int bitfield_is_set(struct bitfield *bf, size_t bit) in bitfield_is_set() argument
58 if (bit >= bf->max_bits) in bitfield_is_set()
60 return !!(bf->bits[bit / 8] & BIT(bit % 8)); in bitfield_is_set()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCVXsf.td22 // Input: (bit<27-26>, bit<24-20>, scalar_in, vl) or
23 // (bit<27-26>, bit<24-20>, bit<11-7>, scalar_in, vl)
24 class RISCVSFCustomVC_X<bit HasDst, bit HasSE, bit ImmScalar>
29 … !listconcat([IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>], // bit<27-26> and bit<24-20>
41 // Input: (bit<27-26>, vector_in, vector_in/scalar_in, vl) or
42 // (bit<27-26>, bit<11-7>, vector_in, vector_in/scalar_in, vl)
43 class RISCVSFCustomVC_XV<bit HasDst, bit HasSE, bit ImmScalar>
61 // (bit<27-26>, vector_in, vector_in, vector_in/scalar_in, vl)
62 class RISCVSFCustomVC_XVV<bit HasDst, bit HasSE, bit ImmScalar>
76 // (bit<27-26>, wvector_in, vector_in, vector_in/scalar_in, vl)
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