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Searched refs:caches (Results 1 – 25 of 54) sorted by relevance

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/freebsd/sys/x86/x86/
H A Dmp_x86.c215 if (caches[level - 1].present) { in add_deterministic_cache()
221 caches[level - 1].present = 1; in add_deterministic_cache()
328 caches[0].id_shift = 0; in topo_probe_amd()
329 caches[0].present = 1; in topo_probe_amd()
335 caches[1].id_shift = 0; in topo_probe_amd()
336 caches[1].present = 1; in topo_probe_amd()
349 caches[2].id_shift = in topo_probe_amd()
351 caches[2].present = 1; in topo_probe_amd()
474 caches[0].present = 1; in topo_probe_intel_caches()
476 caches[1].present = 1; in topo_probe_intel_caches()
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/freebsd/contrib/llvm-project/compiler-rt/lib/lsan/
H A Dlsan_fuchsia.cpp71 void GetAllThreadAllocatorCachesLocked(InternalMmapVector<uptr> *caches) { in GetAllThreadAllocatorCachesLocked() argument
75 static_cast<decltype(caches)>(arg)->push_back(ctx->cache_begin()); in GetAllThreadAllocatorCachesLocked()
77 caches); in GetAllThreadAllocatorCachesLocked()
H A Dlsan_common.h108 void GetAllThreadAllocatorCachesLocked(InternalMmapVector<uptr> *caches);
/freebsd/crypto/heimdal/kuser/
H A Dkcc-commands.in78 help = "List all caches with their content"
84 help = "List all caches"
230 help = "Copies credential caches"
/freebsd/sys/contrib/device-tree/Bindings/arm/msm/
H A Dqcom,llcc.yaml16 SoC, the idea is to minimize the local caches at the clients and migrate to
H A Dqcom,idle-state.txt49 modes. In a hierarchical power domain SoC, this means L2 and other caches can
/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dpamu.txt61 second is the number of "ways". For direct-mapped caches,
67 second is the number of "ways". For direct-mapped caches,
/freebsd/sys/contrib/openzfs/contrib/pyzfs/
H A DREADME21 synchronously and that, for example, disk caches are flushed.
/freebsd/crypto/openssl/doc/internal/man3/
H A Dx509v3_cache_extensions.pod17 and caches the result of that processing as well as further derived info,
H A Dossl_cmp_ctx_set1_caPubs.pod38 which caches any already validated server cert, or NULL if not available.
H A Dossl_cmp_msg_protect.pod34 tries to build it using ctx->untrusted and caches the result in ctx->chain.
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dti,davinci-rproc.txt12 like L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
H A Dxlnx,zynqmp-r5fss.yaml44 Each processor includes separate L1 instruction and data caches and
H A Dti,k3-dsp-rproc.yaml18 L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
H A Dti,keystone-rproc.txt9 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory controller,
/freebsd/contrib/llvm-project/compiler-rt/lib/hwasan/
H A Dhwasan_thread.cpp211 void GetAllThreadAllocatorCachesLocked(InternalMmapVector<uptr> *caches) {} in GetAllThreadAllocatorCachesLocked() argument
/freebsd/contrib/llvm-project/compiler-rt/lib/tsan/rtl/
H A Dtsan_flags.inc52 TSAN_FLAG(int, flush_symbolizer_ms, 5000, "Flush symbolizer caches every X ms.")
/freebsd/sys/contrib/device-tree/Bindings/cache/
H A Dqcom,llcc.yaml15 SoC, the idea is to minimize the local caches at the clients and migrate to
/freebsd/lib/libomp/
H A Dkmp_i18n_default.inc85 "L1 caches",
87 "L2 caches",
89 "L3 caches",
98 "LL caches",
/freebsd/contrib/file/magic/Magdir/
H A Dgeo114 # MBSystem processing caches the mbinfo output
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcpu-capacity.txt37 max frequency (with caches enabled). The obtained DMIPS score is then divided
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Dcpu-capacity.txt37 max frequency (with caches enabled). The obtained DMIPS score is then divided
/freebsd/crypto/openssl/doc/man3/
H A DOSSL_DECODER_CTX_new_for_pkey.pod84 The internal L<OSSL_PASSPHRASE_CALLBACK(3)> function caches the pass phrase, to
/freebsd/contrib/llvm-project/openmp/runtime/src/i18n/
H A Den_US.txt116 L1Caches "L1 caches"
118 L2Caches "L2 caches"
120 L3Caches "L3 caches"
129 LLCaches "LL caches"
/freebsd/crypto/openssl/
H A DNOTES-UNIX.md71 4. Using system shared object caches and default directories.

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