| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | qcom,spmi-clkdiv.txt | 1 Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv)
3 clkdiv configures the clock frequency of a set of outputs on the PMIC.
14 Definition: must be "qcom,spmi-clkdiv".
46 compatible = "qcom,spmi-clkdiv";
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| H A D | qcom,spmi-clkdiv.yaml | 4 $id: http://devicetree.org/schemas/clock/qcom,spmi-clkdiv.yaml#
20 const: qcom,spmi-clkdiv
57 compatible = "qcom,spmi-clkdiv";
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| H A D | renesas,emev2-smu.txt | 21 - compatible: Should be "renesas,emev2-smu-clkdiv"
40 compatible = "renesas,emev2-smu-clkdiv";
87 compatible = "renesas,emev2-smu-clkdiv";
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| H A D | renesas,emev2-smu.yaml | 49 const: renesas,emev2-smu-clkdiv
129 compatible = "renesas,emev2-smu-clkdiv";
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| /freebsd/sys/arm/ti/ |
| H A D | ti_sdhci.c | 174 uint32_t clkdiv, val32; in ti_sdhci_read_2() local
191 clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) & in ti_sdhci_read_2()
194 val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; in ti_sdhci_read_2()
196 val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) & in ti_sdhci_read_2()
281 uint32_t clkdiv, val32; in ti_sdhci_write_2() local
289 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; in ti_sdhci_write_2()
291 clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) & in ti_sdhci_write_2()
293 clkdiv *= 2; in ti_sdhci_write_2()
294 if (clkdiv > MMCHS_SYSCTL_CLKD_MASK) in ti_sdhci_write_2()
295 clkdiv = MMCHS_SYSCTL_CLKD_MASK; in ti_sdhci_write_2()
[all …]
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| H A D | ti_spi.c | 121 uint32_t clkdiv, conf, div, extclk, reg; in ti_spi_set_clock() local
123 clkdiv = TI_SPI_GCLK / freq; in ti_spi_set_clock()
124 if (clkdiv > MCSPI_EXTCLK_MSK) { in ti_spi_set_clock()
126 clkdiv = 0; in ti_spi_set_clock()
128 while (TI_SPI_GCLK / div > freq && clkdiv <= 0xf) { in ti_spi_set_clock()
129 clkdiv++; in ti_spi_set_clock()
132 conf = clkdiv << MCSPI_CONF_CLK_SHIFT; in ti_spi_set_clock()
134 extclk = clkdiv >> 4; in ti_spi_set_clock()
135 clkdiv &= MCSPI_CONF_CLK_MSK; in ti_spi_set_clock()
136 conf = MCSPI_CONF_CLKG | clkdiv << MCSPI_CONF_CLK_SHIFT; in ti_spi_set_clock()
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| /freebsd/sys/dev/iicbus/controller/rockchip/ |
| H A D | rk_i2c.c | 169 uint32_t clkdiv; in rk_i2c_get_clkdiv() local
176 clkdiv = (sclk_freq / speed / RK_I2C_CLKDIV_MUL / 2) - 1; in rk_i2c_get_clkdiv()
177 clkdiv &= RK_I2C_CLKDIVL_MASK; in rk_i2c_get_clkdiv()
179 clkdiv = clkdiv << RK_I2C_CLKDIVH_SHIFT | clkdiv; in rk_i2c_get_clkdiv()
181 return (clkdiv); in rk_i2c_get_clkdiv()
188 uint32_t clkdiv; in rk_i2c_reset() local
195 clkdiv = rk_i2c_get_clkdiv(sc, busfreq); in rk_i2c_reset()
200 RK_I2C_WRITE(sc, RK_I2C_CLKDIV, clkdiv); in rk_i2c_reset()
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| /freebsd/sys/arm/ti/am335x/ |
| H A D | am335x_ehrpwm.c | 242 u_int clkdiv, hspclkdiv, pwmclk, pwmtick, tbprd; in am335x_ehrpwm_cfg_period() local
257 for (clkdiv = 0; clkdiv < 8; ++clkdiv) { in am335x_ehrpwm_cfg_period()
258 const u_int cd = 1 << clkdiv; in am335x_ehrpwm_cfg_period()
289 regval |= TBCTL_CLKDIV(clkdiv) | TBCTL_HSPCLKDIV(hspclkdiv); in am335x_ehrpwm_cfg_period()
295 clkdiv, hspclkdiv, tbprd - 1, in am335x_ehrpwm_cfg_period()
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| /freebsd/sys/contrib/device-tree/src/arm/renesas/ |
| H A D | emev2.dtsi | 72 compatible = "renesas,emev2-smu-clkdiv";
84 compatible = "renesas,emev2-smu-clkdiv";
103 compatible = "renesas,emev2-smu-clkdiv";
109 compatible = "renesas,emev2-smu-clkdiv";
115 compatible = "renesas,emev2-smu-clkdiv";
121 compatible = "renesas,emev2-smu-clkdiv";
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| /freebsd/sys/contrib/device-tree/Bindings/iio/frequency/ |
| H A D | adf4350.txt | 49 adi,12bit-clkdiv-mode != 0
51 Valid values for the clkdiv mode are:
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| H A D | adi,adf4350.yaml | 116 Clock divider value used when adi,12bit-clkdiv-mode != 0
122 Valid values for the clkdiv mode are:
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| /freebsd/sys/arm/freescale/imx/ |
| H A D | imx_i2c.c | 112 struct clkdiv { struct
116 static struct clkdiv clkdiv_table[] = { argument
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| /freebsd/sys/contrib/device-tree/src/arc/ |
| H A D | abilis_tb10x.dtsi | 197 output-clkdiv = <4>;
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| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | am43xx-clocks.dtsi | 693 cpsw_50m_clkdiv: clock-cpsw-50m-clkdiv {
702 cpsw_5m_clkdiv: clock-cpsw-5m-clkdiv {
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| /freebsd/sys/dev/cxgb/common/ |
| H A D | cxgb_t3_hw.c | 250 u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1; in mi1_init() local
251 u32 val = F_PREEN | V_CLKDIV(clkdiv); in mi1_init()
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