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/freebsd/sys/arm64/arm64/
H A Dmp_machdep.c733 (*cores)++; in cpu_count_acpi_handler()
745 u_int cores; in cpu_count_acpi() local
757 cores = 0; in cpu_count_acpi()
763 return (cores); in cpu_count_acpi()
770 int cores; in cpu_mp_setmaxid() local
779 if (cores > 0) { in cpu_mp_setmaxid()
780 cores = MIN(cores, MAXCPU); in cpu_mp_setmaxid()
783 cores); in cpu_mp_setmaxid()
793 cores = MIN(cores, MAXCPU); in cpu_mp_setmaxid()
796 cores); in cpu_mp_setmaxid()
[all …]
/freebsd/sys/riscv/riscv/
H A Dmp_machdep.c465 int cores; in cpu_mp_setmaxid() local
468 cores = ofw_cpu_early_foreach(cpu_check_mmu, true); in cpu_mp_setmaxid()
469 if (cores > 0) { in cpu_mp_setmaxid()
470 cores = MIN(cores, MAXCPU); in cpu_mp_setmaxid()
472 printf("Found %d CPUs in the device tree\n", cores); in cpu_mp_setmaxid()
473 mp_ncpus = cores; in cpu_mp_setmaxid()
474 mp_maxid = cores - 1; in cpu_mp_setmaxid()
485 if (TUNABLE_INT_FETCH("hw.ncpu", &cores)) { in cpu_mp_setmaxid()
486 if (cores > 0 && cores < mp_ncpus) { in cpu_mp_setmaxid()
487 mp_ncpus = cores; in cpu_mp_setmaxid()
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/freebsd/sys/amd64/vmm/
H A Dx86.c86 uint16_t cores, maxcpus, sockets, threads; in x86_emulate_cpuid() local
141 vm_get_topology(vm, &sockets, &cores, &threads, in x86_emulate_cpuid()
153 width = MIN(0xF, log2(threads * cores)); in x86_emulate_cpuid()
156 logical_cpus = MIN(0xFF, threads * cores - 1); in x86_emulate_cpuid()
241 vm_get_topology(vm, &sockets, &cores, &threads, in x86_emulate_cpuid()
255 logical_cpus = threads * cores; in x86_emulate_cpuid()
282 vm_get_topology(vm, &sockets, &cores, &threads, in x86_emulate_cpuid()
384 logical_cpus = threads * cores; in x86_emulate_cpuid()
397 regs[0] |= (cores - 1) << 26; in x86_emulate_cpuid()
408 logical_cpus *= cores; in x86_emulate_cpuid()
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/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dsnps,arc-timer.txt4 - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically
5 TIMER0 used as clockevent provider (true for all ARC cores)
12 (16 for ARCHS cores, 3 for ARC700 cores)
/freebsd/sys/dev/bhnd/bhndb/
H A Dbhndb_pci.c114 struct bhnd_core_info *cores);
374 cores = NULL; in bhndb_pci_attach()
444 cores = NULL; in bhndb_pci_attach()
464 bhndb_pci_probe_free_core_table(cores); in bhndb_pci_attach()
477 if (cores != NULL) in bhndb_pci_attach()
478 bhndb_pci_probe_free_core_table(cores); in bhndb_pci_attach()
1358 p->cores = NULL; in bhndb_pci_probe_alloc()
1384 if (p->cores != NULL) in bhndb_pci_probe_alloc()
1433 *cores = malloc(len, M_BHND, M_WAITOK); in bhndb_pci_probe_copy_core_table()
1434 memcpy(*cores, probe->cores, len); in bhndb_pci_probe_copy_core_table()
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H A Dbhndbvar.h64 struct bhnd_core_info *cores, u_int ncores,
82 struct bhnd_core_info *cores, u_int ncores,
/freebsd/sys/contrib/device-tree/Bindings/media/xilinx/
H A Dvideo.txt1 DT bindings for Xilinx video IP cores
4 Xilinx video IP cores process video streams by acting as video sinks and/or
10 cores are represented as defined in ../video-interfaces.txt.
18 The following properties are common to all Xilinx video IP cores.
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
H A Dxlnx,video.txt8 video IP cores. Each video IP core is represented as documented in video.txt
11 mappings between DMAs and the video IP cores.
/freebsd/sys/modules/bhnd/
H A DMakefile3 .PATH: ${SRCTOP}/sys/dev/bhnd/cores/chipc
4 .PATH: ${SRCTOP}/sys/dev/bhnd/cores/chipc/pwrctl
5 .PATH: ${SRCTOP}/sys/dev/bhnd/cores/pmu
69 cores \
/freebsd/sys/dev/bhnd/
H A Dbhnd_erom.h166 bhnd_erom_get_core_table(bhnd_erom_t *erom, struct bhnd_core_info **cores, in bhnd_erom_get_core_table() argument
169 return (BHND_EROM_GET_CORE_TABLE(erom, cores, num_cores)); in bhnd_erom_get_core_table()
179 bhnd_erom_free_core_table(bhnd_erom_t *erom, struct bhnd_core_info *cores) in bhnd_erom_free_core_table() argument
181 return (BHND_EROM_FREE_CORE_TABLE(erom, cores)); in bhnd_erom_free_core_table()
H A Dbhnd_erom_if.m114 * Parse all cores descriptors, returning the array in @p cores and the count
121 * @param[out] cores The table of parsed core descriptors.
122 * @param[out] num_cores The number of core records in @p cores.
130 struct bhnd_core_info **cores;
138 * @param cores A core table allocated by @p erom.
142 struct bhnd_core_info *cores;
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dbrcm,bus-axi.txt9 The cores on the AXI bus are automatically detected by bcma with the
12 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
17 The top-level axi bus may contain children representing attached cores
19 detected (e.g. IRQ numbers). Also some of the cores may be responsible
/freebsd/tools/tools/netmap/
H A Dnmreplay.c1157 cores[0] = atoi(av[0]); in main()
1158 cores[1] = cores[0] + 1; in main()
1159 cores[2] = cores[1] + 1; in main()
1160 cores[3] = cores[2] + 1; in main()
1162 cores[0] = atoi(av[0]); in main()
1163 cores[1] = cores[0] + 1; in main()
1164 cores[2] = atoi(av[1]); in main()
1165 cores[3] = cores[2] + 1; in main()
1167 cores[0] = atoi(av[0]); in main()
1168 cores[1] = atoi(av[1]); in main()
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Darm,vexpress-juno.yaml45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
51 - description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores
58 cores in a MPCore configuration in a test chip on the core tile. See
64 A15 CPU cores in a test chip on the core tile. This is the first test
71 CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
77 cores in a test chip on the core tile. See ARM DDI 0498D.
84 AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53
85 cores in a big.LITTLE configuration. It also features the MALI T624
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dti,pru-consumer.yaml37 firmwares for the PRU cores, the default firmware for the core from
39 correspond to the PRU cores listed in the 'ti,prus' property
50 should correspond to the PRU cores listed in the 'ti,prus' property. The
52 and Tx_PRU0 on K3 SoCs). Use the same value for all cores within the
H A Dmtk,scp.yaml87 The other cores are represented as child nodes of the boot core.
93 cores. The power of cache, SRAM and L1TCM power should be enabled
94 before booting SCP cores. The size of cache, SRAM, and L1TCM are varied
97 The SCP cores do not use an MMU, but has a set of registers to
122 initializing sub cores of multi-core SCP.
H A Dti,pru-rproc.yaml7 title: TI Programmable Realtime Unit (PRU) cores
14 (PRU-ICSS or PRUSS) has two 32-bit load/store RISC CPU cores called
20 PRU cores called RTUs with slightly different IP integration. The K3 SoCs
22 auxiliary Transmit PRU cores called Tx_PRUs that augment the PRUs. Each RTU
73 and the PRU/RTU cores. For the values of the interrupt cells please refer
/freebsd/tools/tools/netrate/tcpp/
H A Dparallelism.csh12 set cores=8
19 foreach core (`jot $cores`)
/freebsd/sys/modules/bhnd/cores/bhnd_pci/
H A DMakefile2 .PATH: ${SRCTOP}/sys/dev/bhnd/cores/pci
3 .PATH: ${SRCTOP}/sys/dev/bhnd/cores/pcie2
/freebsd/sys/modules/bhnd/cores/bhnd_pcib/
H A DMakefile2 .PATH: ${SRCTOP}/sys/dev/bhnd/cores/pci
3 .PATH: ${SRCTOP}/sys/dev/bhnd/cores/pcie2
/freebsd/sys/modules/bhnd/cores/bhnd_pci_hostb/
H A DMakefile2 .PATH: ${SRCTOP}/sys/dev/bhnd/cores/pci
3 .PATH: ${SRCTOP}/sys/dev/bhnd/cores/pcie2
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm632.dtsi45 * CPU0-3 are efficiency cores, CPU4-7 are performance cores
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca15-tc1.dts199 volt-cores {
210 amp-cores {
211 /* Total current for the two cores */
224 power-cores {
/freebsd/sys/contrib/device-tree/Bindings/power/
H A Drenesas,apmu.yaml40 Array of phandles pointing to CPU cores, which should match the order of
41 CPU cores used by the WUPCR and PSTR registers in the Advanced Power
/freebsd/sys/contrib/device-tree/Bindings/
H A Dxilinx.txt1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
89 That covers the general approach to binding xilinx IP cores into the

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