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Searched refs:fuse (Results 1 – 25 of 113) sorted by relevance

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/freebsd/sys/contrib/device-tree/Bindings/opp/
H A Dopp-v2-qcom-level.yaml27 qcom,opp-fuse-level:
29 A positive value representing the fuse corner/level associated with
30 this OPP node. Sometimes several corners/levels shares a certain fuse
31 corner/level. A fuse corner/level contains e.g. ref uV, min uV,
39 - qcom,opp-fuse-level
53 qcom,opp-fuse-level = <1>;
57 qcom,opp-fuse-level = <2>;
61 qcom,opp-fuse-level = <3>;
H A Dqcom-opp.txt16 - qcom,opp-fuse-level: A positive value representing the fuse corner/level
18 a certain fuse corner/level. A fuse corner/level contains e.g. ref uV,
/freebsd/sys/contrib/device-tree/Bindings/fuse/
H A Dnvidia,tegra20-fuse.yaml4 $id: http://devicetree.org/schemas/fuse/nvidia,tegra20-fuse.yaml#
38 - const: fuse
45 - const: fuse
81 fuse@7000f800 {
85 clock-names = "fuse";
87 reset-names = "fuse";
H A Dnvidia,tegra20-fuse.txt1 NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
12 nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
20 of the fuse registers.
24 - fuse
28 - fuse
32 fuse@7000f800 {
37 clock-names = "fuse";
39 reset-names = "fuse";
/freebsd/sys/contrib/device-tree/Bindings/power/avs/
H A Dqcom,cpr.txt61 that makes up a fuse corner, for each fuse corner.
62 As well as the CPR fuse revision.
81 qcom,opp-fuse-level = <1>;
85 qcom,opp-fuse-level = <2>;
89 qcom,opp-fuse-level = <3>;
H A Dqcom,cpr.yaml112 qcom,opp-fuse-level = <1>;
116 qcom,opp-fuse-level = <2>;
120 qcom,opp-fuse-level = <3>;
/freebsd/sys/dev/qat/qat_hw/qat_dh895xcc/
H A Dadf_dh895xcc_hw_data.c37 u32 fuse; in get_accel_mask() local
39 fuse = pci_read_config(pdev, ADF_DEVICE_FUSECTL_OFFSET, 4); in get_accel_mask()
41 return (~fuse) >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET & in get_accel_mask()
49 u32 fuse; in get_ae_mask() local
51 fuse = pci_read_config(pdev, ADF_DEVICE_FUSECTL_OFFSET, 4); in get_ae_mask()
53 return (~fuse) & ADF_DH895XCC_ACCELENGINES_MASK; in get_ae_mask()
/freebsd/sys/dev/qat/qat_hw/qat_c62x/
H A Dadf_c62x_hw_data.c33 u32 fuse; in get_accel_mask() local
36 fuse = pci_read_config(pdev, ADF_DEVICE_FUSECTL_OFFSET, 4); in get_accel_mask()
39 return (~(fuse | straps)) >> ADF_C62X_ACCELERATORS_REG_OFFSET & in get_accel_mask()
47 u32 fuse; in get_ae_mask() local
52 fuse = pci_read_config(pdev, ADF_DEVICE_FUSECTL_OFFSET, 4); in get_ae_mask()
66 return (~(fuse | me_straps)) & ADF_C62X_ACCELENGINES_MASK; in get_ae_mask()
/freebsd/sys/dev/qat/qat_hw/qat_c3xxx/
H A Dadf_c3xxx_hw_data.c31 u32 fuse; in get_accel_mask() local
34 fuse = pci_read_config(pdev, ADF_DEVICE_FUSECTL_OFFSET, 4); in get_accel_mask()
37 return (~(fuse | straps)) >> ADF_C3XXX_ACCELERATORS_REG_OFFSET & in get_accel_mask()
45 u32 fuse; in get_ae_mask() local
50 fuse = pci_read_config(pdev, ADF_DEVICE_FUSECTL_OFFSET, 4); in get_ae_mask()
64 return (~(fuse | me_straps)) & ADF_C3XXX_ACCELENGINES_MASK; in get_ae_mask()
/freebsd/sys/dev/qat/qat_hw/qat_200xx/
H A Dadf_200xx_hw_data.c32 u32 fuse; in get_accel_mask() local
35 fuse = pci_read_config(pdev, ADF_DEVICE_FUSECTL_OFFSET, 4); in get_accel_mask()
38 return (~(fuse | straps)) >> ADF_200XX_ACCELERATORS_REG_OFFSET & in get_accel_mask()
46 u32 fuse; in get_ae_mask() local
51 fuse = pci_read_config(pdev, ADF_DEVICE_FUSECTL_OFFSET, 4); in get_ae_mask()
65 return (~(fuse | me_straps)) & ADF_200XX_ACCELENGINES_MASK; in get_ae_mask()
/freebsd/tools/test/stress2/misc/
H A Dfuse2.sh35 [ -c /dev/fuse ] || kldload fusefs.ko
39 [ -c /dev/fuse ] || kldload fusefs.ko
H A Dfuse.sh36 [ -c /dev/fuse ] || kldload fusefs.ko
/freebsd/sys/arm/allwinner/
H A Daw_sid.c364 enum aw_sid_fuse_id fuse = arg2; in aw_sid_sysctl() local
372 aw_sid_get_fuse(fuse, NULL, &size); in aw_sid_sysctl()
374 ret = aw_sid_get_fuse(fuse, data, &size); in aw_sid_sysctl()
376 device_printf(dev, "Cannot get fuse id %d: %d\n", fuse, ret); in aw_sid_sysctl()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPC.td187 def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load",
191 def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load",
199 SubtargetFeature<"fuse-arith-add", "HasArithAddFusion", "true",
203 SubtargetFeature<"fuse-add-logical", "HasAddLogicalFusion", "true",
207 SubtargetFeature<"fuse-logical-add", "HasLogicalAddFusion", "true",
211 SubtargetFeature<"fuse-logical", "HasLogicalFusion", "true",
215 SubtargetFeature<"fuse-sha3", "HasSha3Fusion", "true",
219 SubtargetFeature<"fuse-cmp", "HasCompareFusion", "true",
223 SubtargetFeature<"fuse-wideimm", "HasWideImmFusion", "true",
227 SubtargetFeature<"fuse-zeromove", "HasZeroMoveFusion", "true",
[all …]
/freebsd/lib/libnvmf/
H A Dnvmf_transport.c138 nc->nc_sqe.fuse &= ~NVMEM(NVME_CMD_PSDT); in nvmf_allocate_command()
139 nc->nc_sqe.fuse |= NVMEF(NVME_CMD_PSDT, NVME_PSDT_SGL); in nvmf_allocate_command()
210 if (NVMEV(NVME_CMD_PSDT, nc->nc_sqe.fuse) != NVME_PSDT_SGL) in nvmf_validate_command_capsule()
/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dqcom-cpufreq-nvmem.yaml200 qcom,opp-fuse-level = <1>;
204 qcom,opp-fuse-level = <2>;
208 qcom,opp-fuse-level = <3>;
/freebsd/sys/dev/nvmf/
H A Dnvmf_transport.c110 nc->nc_sqe.fuse &= ~NVMEM(NVME_CMD_PSDT); in nvmf_allocate_command()
111 nc->nc_sqe.fuse |= NVMEF(NVME_CMD_PSDT, NVME_PSDT_SGL); in nvmf_allocate_command()
189 if (NVMEV(NVME_CMD_PSDT, nc->nc_sqe.fuse) != NVME_PSDT_SGL) in nvmf_validate_command_capsule()
/freebsd/sys/kern/
H A DMake.tags.inc25 ${SYS}/fs/fuse/*.[ch] \
74 ${SYS}/fs/fuse \
/freebsd/sys/modules/fusefs/
H A DMakefile2 .PATH: ${SRCTOP}/sys/fs/fuse
/freebsd/sys/contrib/device-tree/Bindings/nvmem/
H A Dvf610-ocotp.txt8 reg : Address and length of OTP controller and fuse map registers
/freebsd/sys/contrib/device-tree/Bindings/rtc/
H A Dstmp3xxx-rtc.txt11 - stmp,crystal-freq: override crystal frequency as determined from fuse bits.
/freebsd/sys/contrib/device-tree/Bindings/gpu/
H A Dnvidia,gk20a.txt31 - fuse
108 clock-names = "gpu", "pwr", "fuse";
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6q-cm-fx6.dts171 * Although the imx6q fuse indicates that 1.2GHz operation is possible,
193 * Although the imx6q fuse indicates that 1.2GHz operation is possible,
215 * Although the imx6q fuse indicates that 1.2GHz operation is possible,
237 * Although the imx6q fuse indicates that 1.2GHz operation is possible,
/freebsd/sys/contrib/zstd/
H A DMakefile315 …LDFLAGS=-fuse-ld=gold MOREFLAGS="-g -fno-sanitize-recover=all -fsanitize=address -Werror" $(MAKE) …
321 …LDFLAGS=-fuse-ld=gold MOREFLAGS="-g -fno-sanitize-recover=all -fsanitize=memory -fno-omit-frame-po…
330 …LDFLAGS=-fuse-ld=gold MOREFLAGS="-g -fno-sanitize-recover=all -fsanitize-recover=pointer-overflow …
333 …LDFLAGS=-fuse-ld=gold MOREFLAGS="-g -fno-sanitize-recover=all -fsanitize=thread -Werror" $(MAKE) -…
/freebsd/sys/contrib/device-tree/Bindings/gpu/host1x/
H A Dnvidia,tegra234-nvdec.yaml35 - const: fuse
137 clock-names = "nvdec", "fuse", "tsec_pka";

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