/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/ |
H A D | MSP430Disassembler.cpp | 324 static MSP430CC::CondCodes getCondCode(unsigned Cond) { in getCondCode() function 353 MI.addOperand(MCOperand::createImm(getCondCode(Cond))); in getInstructionCJ()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 749 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_UINT() 759 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_SINT() 839 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC() 845 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC() 873 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC() 881 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC() 913 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC() 939 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
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H A D | SIISelLowering.cpp | 5807 DAG.getCondCode(CCOpcode)); in lowerICMPIntrinsic() 5836 Src1, DAG.getCondCode(CCOpcode)); in lowerFCMPIntrinsic() 5876 DAG.getConstant(0, SL, MVT::i32), DAG.getCondCode(ISD::SETNE)); in lowerBALLOTIntrinsic()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAG.h | 814 SDValue getCondCode(ISD::CondCode Cond); 1217 {VT, MVT::Other}, {Chain, LHS, RHS, getCondCode(Cond)}); 1218 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond)); 1229 return getNode(ISD::VP_SETCC, DL, VT, LHS, RHS, getCondCode(Cond), Mask, 1248 False, getCondCode(Cond));
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeFloatTypes.cpp | 1023 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC() 1108 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC() 1130 NewRHS, DAG.getCondCode(CCCode)); in SoftenFloatOp_SETCC() 1133 DAG.getCondCode(CCCode)), 0); in SoftenFloatOp_SETCC() 1984 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC() 2069 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
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H A D | LegalizeIntegerTypes.cpp | 5223 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands() 5280 DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands() 5309 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC() 5328 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC() 5345 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
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H A D | LegalizeDAG.cpp | 4009 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode() 4154 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode() 4186 Tmp4 = DAG.getCondCode(NeedInvert ? ISD::SETEQ : ISD::SETNE); in ExpandNode()
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H A D | TargetLowering.cpp | 9963 {Op0, Op1, DAG.getCondCode(CC)})) { in expandIntMINMAX() 9970 {Op0, Op1, DAG.getCondCode(CC)})) { in expandIntMINMAX() 10908 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode() 10921 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
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H A D | SelectionDAGBuilder.cpp | 7819 Opers.push_back(DAG.getCondCode(Condition)); in visitConstrainedFPIntrinsic()
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H A D | SelectionDAG.cpp | 1981 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode() function in SelectionDAG
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 2917 {Abs, MaxValSplat, DAG.getCondCode(ISD::SETOLT), in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() 7272 SDValue SetNE = DAG.getCondCode(ISD::SETNE); in lowerSELECT() 7323 SDValue TargetCC = DAG.getCondCode(CCVal); in lowerSELECT() 7349 SDValue TargetCC = DAG.getCondCode(CCVal); in lowerBRCOND() 10250 SDValue OLECCVal = DAG.getCondCode(ISD::SETOLE); in lowerVectorStrictFSetcc() 10265 SDValue OEQCCVal = DAG.getCondCode(ISD::SETOEQ); in lowerVectorStrictFSetcc() 10922 DAG.getCondCode(ISD::SETNE), in lowerVPReverseExperimental() 14468 CC = DAG.getCondCode(CCVal); in combine_CC() 14489 CC = DAG.getCondCode(CCVal); in combine_CC() 14507 CC = DAG.getCondCode(CCVal); in combine_CC() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 957 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anonbcf2b7680111::ARMOperand 2416 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeNoAL() 2423 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedI() 2430 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedS() 2438 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedU() 2445 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedFP() 2472 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands() 2473 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands() 2525 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands() 3895 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; in print() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 627 AArch64CC::CondCode getCondCode() const { in getCondCode() function in __anon81e25dfa0111::AArch64Operand 1929 Inst.addOperand(MCOperand::createImm(getCondCode())); in addCondCodeOperands() 2533 OS << "<condcode " << getCondCode() << ">"; in print()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 19832 N->getOperand(2), Splat, DAG.getCondCode(CC)); in tryConvertSVEWideCompare() 20208 N->getOperand(3), DAG.getCondCode(ISD::SETUGE)); in performIntrinsicCombine() 20214 N->getOperand(3), DAG.getCondCode(ISD::SETUGT)); in performIntrinsicCombine() 20220 N->getOperand(3), DAG.getCondCode(ISD::SETGE)); in performIntrinsicCombine() 20226 N->getOperand(3), DAG.getCondCode(ISD::SETGT)); in performIntrinsicCombine() 20232 N->getOperand(3), DAG.getCondCode(ISD::SETEQ)); in performIntrinsicCombine() 20238 N->getOperand(3), DAG.getCondCode(ISD::SETNE)); in performIntrinsicCombine() 20243 N->getOperand(3), DAG.getCondCode(ISD::SETUO)); in performIntrinsicCombine() 22786 SetCC.getOperand(2) == DAG.getCondCode(ISD::SETGT)) { in performVSelectCombine() 25820 {Pg, Op1, Op2, DAG.getCondCode(ISD::SETNE)}); in convertFixedMaskToScalableVector()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 6803 DAG.getCondCode(ISD::SETEQ)); in LowerVSETCC() 9300 DAG.getCondCode(ISD::SETNE)); in LowerTruncatei1() 10515 DAG.getCondCode(CC)); in LowerFSETCC()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 3630 DAG.getCondCode(CC)); in LowerSETCC()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 22932 SDValue CC = DAG.getCondCode(Cond); in splitIntVSETCC()
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