Searched refs:isAGPRClass (Results 1 – 10 of 10) sorted by relevance
91 bool IsAGPRDst = TRI->isAGPRClass(MRI->getRegClass(Reg)); in processReg()113 bool IsAGPRSrc = TRI->isAGPRClass(MRI->getRegClass(SrcReg)); in processReg()233 (ST.hasGFX90AInsts() || !TRI->isAGPRClass(RC))) in runOnMachineFunction()
215 static bool isAGPRClass(const TargetRegisterClass *RC) { in isAGPRClass() function
453 if (ST.hasMAIInsts() && (isVGPRClass(RC) || isAGPRClass(RC))) { in getLargestLegalSuperClass()942 if (isAGPRClass(RC) && !ST.hasGFX90AInsts()) in getCrossCopyRegClass()1342 const bool IsAGPR = !ST.hasGFX90AInsts() && isAGPRClass(RC); in buildSpillLoadStore()3015 return RC && isAGPRClass(RC); in isAGPR()3223 if (isAGPRClass(&RC)) in isProperlyAlignedRC()3243 if (isAGPRClass(RC)) in getProperlyAlignedRC()
310 bool IsAGPR = TRI->isAGPRClass(DstRC); in foldVGPRCopyIntoRegSequence()821 if (HasUses && AllAGPRUses && !TRI->isAGPRClass(RC0)) { in processPHINode()
45 : STI->isAGPRClass(RC) in getRegKind()
804 if (RC && SIRegisterInfo::isAGPRClass(RC)) { in usesAGPRs()
1065 if (RI.isAGPRClass(RC)) { in copyPhysReg()1066 if (ST.hasGFX90AInsts() && RI.isAGPRClass(SrcRC)) in copyPhysReg()1073 } else if (RI.hasVGPRs(RC) && RI.isAGPRClass(SrcRC)) { in copyPhysReg()1381 if (RI.isAGPRClass(DstRC)) in getMovOpcode()1714 return TRI.isAGPRClass(RC) ? getAGPRSpillSaveOpcode(Size) in getVectorRegSpillSaveOpcode()1939 return TRI.isAGPRClass(RC) ? getAGPRSpillRestoreOpcode(Size) in getVectorRegSpillRestoreOpcode()6489 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()6493 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()8336 if (RI.isAGPRClass(SrcRC)) { in getDestEquivalentVGPRClass()8337 if (RI.isAGPRClass(NewDstRC)) in getDestEquivalentVGPRClass()
1888 return TRI->isAGPRClass(getDataRegClass(*CI.I)) in getTargetRegisterClass()
304 return TRI->isAGPRClass(&RC) ? AMDGPU::AGPRRegBank : AMDGPU::VGPRRegBank; in getRegBankFromRegClass()
15124 else if (SIRegisterInfo::isAGPRClass(RC)) in getRegForInlineAsmConstraint()