| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 605 return isAdd; in EncodeAddrModeOpValues()
1011 if (isAdd) in getAddrModeImm12OpValue()
1042 if (isAdd) in getT2ScaledImmOpValue()
1090 if (isAdd) in getMveAddrModeQOpValue()
1134 if (isAdd) in getT2AddrModeImm8s4OpValue()
1161 if (isAdd) in getT2AddrModeImm7s4OpValue()
1298 if (isAdd) in getLdStSORegOpValue()
1445 bool isAdd; in getAddrMode5OpValue() local
1470 if (isAdd) in getAddrMode5OpValue()
1485 bool isAdd; in getAddrMode5FP16OpValue() local
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| H A D | ARMAsmBackend.cpp | 528 bool isAdd = true; in adjustFixupValue() local
531 isAdd = false; in adjustFixupValue()
537 Value |= isAdd << 23; in adjustFixupValue()
759 bool isAdd = true; in adjustFixupValue() local
762 isAdd = false; in adjustFixupValue()
779 bool isAdd = true; in adjustFixupValue() local
782 isAdd = false; in adjustFixupValue()
790 Value |= isAdd << 23; in adjustFixupValue()
806 bool isAdd = true; in adjustFixupValue() local
809 isAdd = false; in adjustFixupValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo16Instr.td | 59 let isCommutable = 1, isAdd = 1 in
64 let isCommutable = 1, isAdd = 1 in
69 let isAdd = 1 in
94 let isAdd = 1, Pattern = [(set mGPR:$rz, (add mGPR:$rZ, oimm8:$imm8))] in
103 let isAdd = 1 in
107 let isAdd = 1 in
117 let isAdd = 1 in
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| H A D | CSKYInstrInfo.td | 524 let isAdd = 1 in
548 let isAdd = 1 in
606 let isCommutable = 1, isAdd = 1 in
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | GenericMachineInstrs.h | 389 bool isAdd() const { in isAdd() function
400 bool isSub() const { return !isAdd(); } in isSub()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | InstrDocsEmitter.cpp | 110 FLAG(isAdd) in EmitInstrDocs()
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| H A D | CodeGenInstruction.h | 257 bool isAdd : 1; variable
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| H A D | CodeGenInstruction.cpp | 448 isAdd = R->getValueAsBit("isAdd"); in CodeGenInstruction()
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| H A D | InstrInfoEmitter.cpp | 1216 if (Inst.isAdd) OS << "|(1ULL<<MCID::Add)"; in emitRecord()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 279 bool isAdd() const { return Flags & (1ULL << MCID::Add); } in isAdd() function
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 874 bool isAdd; member
3271 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
3273 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; in addPostIdxImm8Operands()
3282 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
3285 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; in addPostIdxImm8s4Operands()
3292 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
3822 Op->PostIdxReg.isAdd = isAdd; in CreatePostIdxReg()
5495 bool isAdd = true; in parsePostIdxReg() local
5501 isAdd = false; in parsePostIdxReg()
5573 bool isAdd = true; in parseAM3Offset() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 3030 // {12} isAdd
3049 // {12} isAdd
3066 // {12} isAdd
3085 // {12} isAdd
3364 // {12} isAdd
3383 // {12} isAdd
3405 // {12} isAdd
3424 // {12} isAdd
3857 let isAdd = 1 in
3873 let isAdd = 1 in
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| H A D | ARMInstrFormats.td | 802 // {12} isAdd
820 // {12} isAdd
841 // {12} isAdd
894 // {8} isAdd
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| H A D | ARMInstrThumb.td | 966 let isAdd = 1 in {
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| H A D | ARMInstrThumb2.td | 2424 let isAdd = 1 in
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 444 if (DI->getDesc().isAdd()) { in findInductionRegister()
1626 if (DI->getDesc().isAdd()) { in fixupInductionVariable()
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| H A D | HexagonDepInstrInfo.td | 220 let isAdd = 1;
236 let isAdd = 1;
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | Target.td | 622 bit isAdd = false; // Is this instruction an add instruction?
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 46508 auto combineMulShlAddOrSub = [&](int Mult, int Shift, bool isAdd) { in combineMulSpecial() argument
46513 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result, in combineMulSpecial()
46518 auto combineMulMulAddOrSub = [&](int Mul1, int Mul2, bool isAdd) { in combineMulSpecial() argument
46523 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result, in combineMulSpecial()
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