/freebsd/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/ |
H A D | VEInstPrinter.cpp | 56 if (MO.isImm()) { in printOperand() 78 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand() 84 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand() 86 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand() 87 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand() 95 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand() 122 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandASX() 129 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandASX() 153 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandRRM() 160 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandRRM() [all …]
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H A D | VEMCCodeEmitter.cpp | 96 if (MO.isImm()) in getMachineOpValue() 121 if (MO.isReg() || MO.isImm()) in getBranchTargetOpValue() 133 if (MO.isImm()) in getCCOpValue() 143 if (MO.isImm()) in getRDOpValue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/ |
H A D | XtensaInstPrinter.cpp | 62 else if (MC.isImm()) in printOperand() 96 if (MI->getOperand(OpNum).isImm()) { in printBranchTarget() 111 if (MC.isImm()) { in printJumpTarget() 127 if (MC.isImm()) { in printCallOperand() 142 if (MC.isImm()) { in printL32RTarget() 159 if (MI->getOperand(OpNum).isImm()) { in printImm8_AsmOperand() 171 if (MI->getOperand(OpNum).isImm()) { in printImm8_sh8_AsmOperand() 183 if (MI->getOperand(OpNum).isImm()) { in printImm12_AsmOperand() 194 if (MI->getOperand(OpNum).isImm()) { in printImm12m_AsmOperand() 205 if (MI->getOperand(OpNum).isImm()) { in printUimm4_AsmOperand() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCCodeEmitter.cpp | 240 if (MO.isImm()) in getLdStUImm12OpValue() 261 if (MO.isImm()) in getAdrLabelOpValue() 292 if (MO.isImm()) in getAddSubImmOpValue() 323 if (MO.isImm()) in getCondBranchTargetOpValue() 346 if (MO.isImm()) in getPAuthPCRelOpValue() 368 if (MO.isImm()) in getLoadLiteralOpValue() 396 if (MO.isImm()) in getMoveWideImmOpValue() 416 if (MO.isImm()) in getTestBranchTargetOpValue() 438 if (MO.isImm()) in getBranchTargetOpValue() 654 assert(MO.isImm() && in getMoveVecShifterOpValue() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.cpp | 61 assert(Inst.getOperand(2).isImm()); in LowerLargeShift() 275 if (MO.isImm()) in getBranchTargetOpValueMMR6() 298 if (MO.isImm()) in getBranchTargetOpValueLsl2MMR6() 450 if (MO.isImm()) in getBranchTarget26OpValueMM() 526 if (MO.isImm()) { in getUImm5Lsl2Encoding() 544 if (MO.isImm()) { in getSImm3Lsa2Value() 557 if (MO.isImm()) { in getUImm6Lsl2Encoding() 570 if (MO.isImm()) { in getSImm9AddiuspValue() 730 } else if (MO.isImm()) { in getMachineOpValue() 950 if (MO.isImm()) { in getSimm19Lsl2Encoding() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/AsmParser/ |
H A D | XtensaAsmParser.cpp | 142 bool isImm8() const { return isImm(-128, 127); } in isImm8() 145 return isImm(-32768, 32512) && in isImm8_sh8() 154 return isImm(0, 60) && in isOffset4m32() 161 return isImm(0, 510) && in isOffset8m16() 166 return isImm(0, 1020) && in isOffset8m32() 170 bool isUimm4() const { return isImm(0, 15); } in isUimm4() 172 bool isUimm5() const { return isImm(0, 31); } in isUimm5() 174 bool isImm8n_7() const { return isImm(-8, 7); } in isImm8n_7() 176 bool isShimm1_31() const { return isImm(1, 31); } in isShimm1_31() 178 bool isImm16_31() const { return isImm(16, 31); } in isImm16_31() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
H A D | LanaiMCCodeEmitter.cpp | 115 if (MCOp.isImm()) in getMachineOpValue() 146 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits() 154 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits() 194 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue() 200 if (Op2.isImm()) { in getRiMemoryOpValue() 230 assert(AluMCOp.isImm() && "Third operator is not immediate."); in getRrMemoryOpValue() 265 assert((Op2.isImm() || Op2.isExpr()) && in getSplsOpValue() 271 if (Op2.isImm()) { in getSplsOpValue() 292 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
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H A D | LanaiInstPrinter.cpp | 155 else if (Op.isImm()) in printOperand() 166 if (Op.isImm()) { in printMemImmOperand() 180 if (Op.isImm()) { in printHi16ImmOperand() 192 if (Op.isImm()) { in printHi16AndImmOperand() 204 if (Op.isImm()) { in printLo16AndImmOperand() 229 assert((OffsetOp.isImm() || OffsetOp.isExpr()) && "Immediate expected"); in printMemoryImmediateOffset() 230 if (OffsetOp.isImm()) { in printMemoryImmediateOffset()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 49 if (MO.isReg() || MO.isImm()) in getDirectBrEncoding() 158 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding() 220 if (MO.isImm()) in getImm34Encoding() 248 if (MO.isImm()) in getDispRIEncoding() 262 if (MO.isImm()) in getDispRIXEncoding() 276 if (MO.isImm()) { in getDispRIX16Encoding() 296 assert(MO.isImm() && "Expecting an immediate operand."); in getDispRIHashEncoding() 401 assert(MO.isImm()); in getDispSPE8Encoding() 411 assert(MO.isImm()); in getDispSPE4Encoding() 421 assert(MO.isImm()); in getDispSPE2Encoding() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCTargetDesc.cpp | 41 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && in getMCRDeprecationInfo() 42 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && in getMCRDeprecationInfo() 45 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { in getMCRDeprecationInfo() 46 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { in getMCRDeprecationInfo() 61 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && in getMCRDeprecationInfo() 423 if (Inst.getOperand(OpNum).isImm() && in evaluateBranch() 449 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrMode_i12() 487 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrMode5() 506 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrMode5FP16() 526 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) in evaluateMemOpAddrForAddrModeT2_i8s4() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/ |
H A D | BPFInstPrinter.cpp | 62 } else if (Op.isImm()) { in printOperand() 80 if (OffsetOp.isImm()) { in printMemOperand() 94 if (Op.isImm()) in printImm64Operand() 105 if (Op.isImm()) { in printBrTargetOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
H A D | AVRMCCodeEmitter.cpp | 104 assert(MO.isImm()); in encodeRelCondBrTarget() 161 if (OffsetOp.isImm()) { in encodeMemri() 178 assert(MI.getOperand(OpNo).isImm()); in encodeComplement() 206 assert(MO.isImm()); in encodeImm() 221 assert(MO.isImm()); in encodeCallTarget() 261 if (MO.isImm()) in getMachineOpValue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/ |
H A D | M68kInstPrinter.cpp | 65 if (MO.isImm()) { in printOperand() 77 if (MO.isImm()) in printImmediate() 142 if (Op.isImm()) { in printDisp() 160 assert(MO.isImm() && "absolute memory addressing needs an immediate"); in printAbsMem()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/MCTargetDesc/ |
H A D | ARCInstPrinter.cpp | 148 if (Op.isImm()) { in printOperand() 162 assert(offset.isImm() && "Offset should be immediate."); in printMemOperandRI() 171 assert(Op.isImm() && "Predicate operand is immediate."); in printPredicateOperand() 178 assert(Op.isImm() && "Predicate operand is immediate."); in printBRCCPredicateOperand() 190 if (MO.isImm()) { in printU6ShiftedBy()
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/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/ |
H A D | MSP430MCCodeEmitter.cpp | 110 if (MO.isImm()) { in getMachineOpValue() 130 if (MO2.isImm()) { in getMemOpValue() 158 if (MO.isImm()) in getPCRelImmOpValue() 171 assert(MO.isImm() && "Expr operand expected"); in getCGImmOpValue() 190 assert(MO.isImm() && "Immediate operand expected"); in getCCOpValue()
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H A D | MSP430InstPrinter.cpp | 44 if (Op.isImm()) { in printPCRelImmOperand() 62 } else if (Op.isImm()) { in printOperand() 91 assert(Disp.isImm() && "Expected immediate in displacement field"); in printSrcMemOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiMemAluCombiner.cpp | 185 (Op.isImm() && Op.getImm() == 0)); in isZeroOperand() 246 assert((AluOffset.isReg() || AluOffset.isImm()) && in insertMergedInstruction() 251 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction() 265 else if (AluOffset.isImm()) in insertMergedInstruction() 300 if (Op2.isImm()) { in isSuitableAluInstr() 309 if (Offset.isImm() && in isSuitableAluInstr() 374 assert(AluOperand.isImm() && "Unexpected memory operator type"); in combineMemAluInBasicBlock()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
H A D | LanaiAsmParser.cpp | 209 if (!isImm()) in isBrImm() 226 if (!isImm()) in isHiImm16() 249 if (!isImm()) in isHiImm16And() 262 if (!isImm()) in isLoImm16() 286 if (!isImm()) in isLoImm16Signed() 310 if (!isImm()) in isLoImm16And() 323 if (!isImm()) in isImmShift() 334 if (!isImm()) in isLoImm21() 365 if (!isImm()) in isImm10() 376 if (!isImm()) in isCondCode() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCMacroFusion.cpp | 85 if (!Op.isImm()) in matchingImmOps() 128 if (!SI.isImm()) in checkOpConstraints() 138 if (!D.isImm()) in checkOpConstraints() 207 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints() 218 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCCodeEmitter.cpp | 128 if (MO.isImm()) in getMachineOpValue() 153 if (MO.isImm()) in getSImm13OpValue() 210 if (MO.isReg() || MO.isImm()) in getBranchTargetOpValue() 223 if (MO.isReg() || MO.isImm()) in getBranchPredTargetOpValue() 236 if (MO.isReg() || MO.isImm()) in getBranchOnRegTargetOpValue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFoldOperands.cpp | 42 if (FoldOp->isImm()) { in FoldCandidate() 56 bool isImm() const { in isImm() function 418 if (Fold.isImm()) { in updateOperand() 671 if (Op->isImm()) { in getRegSeqInit() 733 if (!Op->isImm()) in tryToFoldACImm() 1181 if (ImmSrc.isImm()) in getImmOrMaterializedImm() 1204 Src0->isImm()) { in tryConstantFoldOp() 1215 if (!Src0->isImm() && !Src1->isImm()) in tryConstantFoldOp() 1221 if (Src0->isImm() && Src1->isImm()) { in tryConstantFoldOp() 1239 if (Src0->isImm() && !Src1->isImm()) { in tryConstantFoldOp() [all …]
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H A D | GCNDPPCombine.cpp | 186 if (Op1.isImm()) in getOldOpndValue() 223 assert(RowMaskOpnd && RowMaskOpnd->isImm()); in createDPPInst() 225 assert(BankMaskOpnd && BankMaskOpnd->isImm()); in createDPPInst() 430 assert(OldOpnd->isImm()); in isIdentityValue() 485 if (!CombBCZ && OldOpndValue && OldOpndValue->isImm()) { in createDPPInst() 514 assert(Imm->isImm()); in hasNoImmOrEqual() 540 assert(DppCtrl && DppCtrl->isImm()); in combineDPPMov() 550 assert(RowMaskOpnd && RowMaskOpnd->isImm()); in combineDPPMov() 552 assert(BankMaskOpnd && BankMaskOpnd->isImm()); in combineDPPMov() 557 assert(BCZOpnd && BCZOpnd->isImm()); in combineDPPMov() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86InstComments.cpp | 662 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments() 678 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments() 694 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments() 708 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments() 726 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments() 820 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments() 838 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments() 1240 if (MI->getOperand(2).isImm() && in EmitAnyX86InstComments() 1241 MI->getOperand(3).isImm()) in EmitAnyX86InstComments() 1250 if (MI->getOperand(3).isImm() && in EmitAnyX86InstComments() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 782 if (Start->isImm() && End->isImm()) { in computeCount() 858 if (Start->isImm()) in computeCount() 860 if (End->isImm()) in computeCount() 874 if (Start->isImm()) in computeCount() 876 else if (End->isImm()) in computeCount() 883 if (Start->isImm()) in computeCount() 885 else if (End->isImm()) in computeCount() 1418 if (!EndVal->isImm()) in loopCountMayWrapOrUnderFlow() 1495 if (MO.isImm()) { in checkForImmediate() 1575 if (MO.isImm()) { in setImmediate() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/ |
H A D | CSKYMCCodeEmitter.cpp | 34 assert(MO.isImm() && "Unexpected MO type."); in getOImmOpValue() 43 assert(MO.isImm() && "Unexpected MO type."); in getImmOpValueIDLY() 55 assert(MSB.isImm() && LSB.isImm() && "Unexpected MO type."); in getImmOpValueMSBSize() 241 if (MO.isImm()) in getMachineOpValue() 253 assert(MI.getOperand(Idx + 1).isImm() && "Unexpected MO type."); in getRegSeqImmOpValue()
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