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Searched refs:isPredicated (Results 1 – 25 of 49) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrInfo.td628 let isPredicated = 1;
644 let isPredicated = 1;
660 let isPredicated = 1;
680 let isPredicated = 1;
701 let isPredicated = 1;
720 let isPredicated = 1;
741 let isPredicated = 1;
756 let isPredicated = 1;
772 let isPredicated = 1;
786 let isPredicated = 1;
[all …]
H A DHexagonVLIWPacketizer.cpp366 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0; in isNewifiable()
568 if (!HII->isPredicated(MI)) in getPredicateSense()
699 if (HII->isPredicated(PacketMI)) { in canPromoteToNewValueStore()
700 if (!HII->isPredicated(MI)) in canPromoteToNewValueStore()
925 if (!HII->isPredicated(*I)) in restrictingDepExistInPacket()
952 assert(QII->isPredicated(MI) && "Must be predicated instruction"); in getPredicatedRegister()
1213 if (HII->isPredicated(I) || HII->isPredicated(J)) in hasDeadDependence()
1253 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI)) in hasControlDependence()
1474 if (HII->isPredicated(I) && HII->isPredicated(J) && in isLegalToPacketizeTogether()
H A DHexagonInstrFormats.td86 bits<1> isPredicated = 0;
87 let TSFlags{10} = isPredicated;
190 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
301 bits<1> isPredicated = 0;
302 let TSFlags{7} = isPredicated;
H A DHexagonExpandCondsets.cpp346 if (HII->isPredicated(*DefI)) in updateKillFlags()
424 if (HII->isPredicated(*DefI)) in updateDeadsInRange()
494 if (!HII->isPredicated(*DefI)) in updateDeadsInRange()
745 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI)) in isPredicable()
781 if (PredValid && HII->isPredicated(*MI)) { in getReachingDefForPred()
938 if (!HII->isPredicated(MI)) in renameInRange()
1010 if (PredValid && HII->isPredicated(MI) && MI.readsRegister(PredR)) in predicate()
H A DHexagonInstrInfo.h224 bool isPredicated(const MachineInstr &MI) const override;
394 bool isPredicated(unsigned Opcode) const;
H A DHexagonPeephole.cpp231 if (QII->isPredicated(MI)) { in runOnMachineFunction()
H A DHexagon.td352 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
360 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
H A DHexagonInstrInfo.cpp655 if (Term != MBB.end() && isPredicated(*Term) && in insertBranch()
1666 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const { in isPredicated() function in HexagonInstrInfo
2252 if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI))) in isDotNewInst()
2490 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode); in isNewValueJump()
2513 assert(isPredicated(MI)); in isPredicatedNew()
2519 assert(isPredicated(Opcode)); in isPredicatedNew()
2537 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const { in isPredicated() function in HexagonInstrInfo
3247 if (Cond.empty() || !isPredicated(Cond[0].getImm())) in predOpcodeHasNot()
3312 if (isPredicated(MI)) { in getBaseAndOffsetPosition()
3845 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form in getDotOldOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp181 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) { in analyzeBranch()
213 CantAnalyze = !isPredicated(*I); in analyzeBranch()
221 if (!isPredicated(*I) && (isUncondBranchOpcode(I->getOpcode()) || in analyzeBranch()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCriticalAntiDepBreaker.cpp177 MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI); in PrescanInstruction()
256 if (!TII->isPredicated(MI)) { in ScanInstruction()
603 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI)) in BreakAntiDependencies()
H A DIfConversion.cpp1104 bool isPredicated = TII->isPredicated(MI); in ScanInstructions() local
1116 if (!isPredicated) { in ScanInstructions()
1131 if (BBI.ClobbersPred && !isPredicated) { in ScanInstructions()
1974 bool BB1Predicated = BBI1T != MBB1.end() && TII->isPredicated(*BBI1T); in IfConvertDiamondCommon()
1975 bool BB2NonPredicated = BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T); in IfConvertDiamondCommon()
2066 if (TI != BBI.BB->end() && TII->isPredicated(*TI)) in IfConvertDiamond()
2124 if (I.isDebugInstr() || TII->isPredicated(I)) in PredicateBlock()
2184 if (!TII->isPredicated(I) && !MI->isDebugInstr()) { in CopyAndPredicateBlock()
2247 if (FromTI != FromMBB.end() && !TII->isPredicated(*FromTI)) in MergeBlocks()
H A DTargetSchedule.cpp290 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI)) in computeOutputLatency()
H A DAggressiveAntiDepBreaker.cpp376 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) || in PrescanInstruction()
453 TII->isPredicated(MI) || MI.isInlineAsm(); in ScanInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.h44 bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLowOverheadLoops.cpp884 bool isPredicated = isVectorPredicated(&MI); in producesFalseLanesZero() local
888 return isPredicated; in producesFalseLanesZero()
918 if (MO.isUse() && isPredicated) in producesFalseLanesZero()
964 bool isPredicated = isVectorPredicated(&MI); in ValidateLiveOuts() local
968 if (isPredicated) in ValidateLiveOuts()
974 else if (!isPredicated && retainsOrReduces) { in ValidateLiveOuts()
977 } else if (!isPredicated && MI.getOpcode() != ARM::MQPRCopy) in ValidateLiveOuts()
H A DARMBlockPlacement.cpp269 if (!TII->isPredicated(Terminator) && in moveBasicBlock()
H A DARMSchedule.td155 "ARM_MC::isPredicated",
156 "isPredicated"
H A DARMBaseInstrInfo.cpp424 if (!isPredicated(*I) && in analyzeBranch()
453 if (AllowModify && !isPredicated(MBB.back()) && in analyzeBranch()
3031 isPredicated(*PotentialAND)) in optimizeCompareInstr()
3150 if (isPredicated(*MI)) in optimizeCompareInstr()
3297 if (isPredicated(MI)) in shouldSink()
5047 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI)) in getExecutionDomain()
5052 if (Subtarget.useNEONForFPMovs() && !isPredicated(MI) && in getExecutionDomain()
5146 assert(!isPredicated(MI) && "Cannot predicate a VORRd"); in setExecutionDomain()
5168 assert(!isPredicated(MI) && "Cannot predicate a VGETLN"); in setExecutionDomain()
5195 assert(!isPredicated(MI) && "Cannot predicate a VSETLN"); in setExecutionDomain()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h284 bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
339 bool isPredicated() const;
H A DHexagonMCChecker.cpp70 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && in initReg()
442 if (ProducerPredInfo.isPredicated() && in checkNewValues()
443 (!ConsumerPredInfo.isPredicated() || in checkNewValues()
H A DHexagonMCInstrInfo.cpp35 bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const { in isPredicated() function in HexagonMCInstrInfo::PredicateInfo
733 bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII, in isPredicated() function in HexagonMCInstrInfo
939 if (!isPredicated(MCII, MCI)) in predicateInfo()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanAnalysis.cpp125 unsigned CallIdx = R->getNumOperands() - (R->isPredicated() ? 2 : 1); in inferScalarTypeForRecipe()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h179 bool isPredicated(const MachineInstr &MI) const override;
H A DR600Packetizer.cpp79 if (TII->isPredicated(*BI)) in getPreviousVector()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DVectorUtils.cpp1187 (!isPredicated(B->getParent()) || EnablePredicatedInterleavedMemAccesses)) { in analyzeInterleaving()
1323 if ((isPredicated(BlockA) || isPredicated(BlockB)) && in analyzeInterleaving()

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