/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsInstPrinter.cpp | 131 if (Op.isReg()) { in printOperand() 277 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && in printAlias() 279 (isReg<Mips::ZERO>(MI, 1) && in printAlias() 288 return isReg<Mips::ZERO>(MI, 1) && in printAlias() 296 return isReg<Mips::ZERO>(MI, 0) && in printAlias() 300 return isReg<Mips::FCC0>(MI, 0) && in printAlias() 304 return isReg<Mips::FCC0>(MI, 0) && in printAlias() 311 (isReg<Mips::RA>(MI, 0) && in printAlias() 324 return isReg<Mips::ZERO>(MI, 2) && in printAlias() 334 return isReg<Mips::ZERO>(MI, 2) && in printAlias() [all …]
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | MachineOperand.h | 227 return isReg() ? 0 : SubReg_TargetFlags; in getTargetFlags() 329 bool isReg() const { return OpKind == MO_Register; } in isReg() function 375 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg() 380 assert(isReg() && "Wrong MachineOperand accessor"); in isUse() 385 assert(isReg() && "Wrong MachineOperand accessor"); in isDef() 390 assert(isReg() && "Wrong MachineOperand accessor"); in isImplicit() 475 if ((isReg() && isImplicit()) || isRegMask()) in isValidExcessOperand() 491 assert(isReg() && "Wrong MachineOperand mutator"); in setSubReg() 515 assert(isReg() && "Wrong MachineOperand mutator"); 531 assert(isReg() && "Wrong MachineOperand mutator"); [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIOptimizeExecMasking.cpp | 104 if (Src.isReg() && Src.getReg() == Exec) in isCopyFromExec() 119 if (Dst.isReg() && Dst.getReg() == Exec && MI.getOperand(1).isReg()) in isCopyToExec() 360 if (MO.isReg() && MO.isKill()) { in findInstrBackwards() 617 if (Src0->isReg()) in optimizeVCMPSaveExecSequence() 619 if (Src1->isReg()) in optimizeVCMPSaveExecSequence() 654 if (!SaveExecSrc0->isReg()) in tryRecordVCmpxAndSaveexecSequence() 709 if (Src0->isReg()) in tryRecordVCmpxAndSaveexecSequence() 712 if (Src1->isReg()) in tryRecordVCmpxAndSaveexecSequence() 738 if (XorDst.isReg() && XorDst.getReg() == Exec && XorSrc0.isReg() && in tryRecordOrSaveexecXorSequence() 739 XorSrc1.isReg() && in tryRecordOrSaveexecXorSequence() [all …]
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H A D | SIPeepholeSDWA.cpp | 90 assert(Target->isReg()); in SDWAOperand() 91 assert(Replaced->isReg()); in SDWAOperand() 247 assert(To.isReg() && From.isReg()); in copyRegOperand() 259 return LHS.isReg() && in isSameReg() 260 RHS.isReg() && in isSameReg() 289 if (!Reg->isReg()) in findSingleRegDef() 447 Operand->isReg() && in convertToSDWA() 469 if (!MO.isReg()) in convertToSDWA() 501 if (Op.isReg()) { in foldToImm() 704 if (!Op1 || !Op1->isReg() || !Op2 || !Op2->isReg()) in matchSDWAOperand() [all …]
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H A D | SIShrinkInstructions.cpp | 98 if (Src0.isReg()) { in foldImmediates() 149 if (MO.isReg()) { in shouldShrinkTrue16() 219 if (!MI.getOperand(0).isReg()) in shrinkScalarCompare() 224 if (!Src0.isReg()) in shrinkScalarCompare() 530 if (Dest->getReg().isVirtual() && SrcReg->isReg()) { in shrinkScalarLogicOp() 563 if (!MO.isReg()) in instAccessReg() 646 if (!Xop.isReg()) in matchSwap() 668 !MovY->getOperand(1).isReg() || in matchSwap() 828 if (!Src0->isReg() && Src1->isReg()) { in runOnMachineFunction() 928 if (Op0.isReg()) { in runOnMachineFunction() [all …]
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H A D | SIFoldOperands.cpp | 60 bool isReg() const { in isReg() function 358 assert(Old.isReg()); in updateOperand() 569 if (!MI->getOperand(OpNo).isReg() || !MI->getOperand(CommuteOpNo).isReg()) in tryAddToFoldList() 608 if (!OpImm.isReg() && in tryAddToFoldList() 664 assert(Sub->isReg()); in getRegSeqInit() 704 if (!OpToFold.isReg()) in tryToFoldACImm() 765 if (UseOp.isReg() && OpToFold.isReg() && in foldOperand() 1407 if (Fold.isReg()) { in foldInstOperand() 1510 if (!Src0->isReg() || !Src1->isReg() || in isClamp() 1680 if (Src0->isReg() && Src1->isReg() && Src0->getReg() == Src1->getReg() && in isOMod() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
H A D | LanaiMCCodeEmitter.cpp | 113 if (MCOp.isReg()) in getMachineOpValue() 147 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits() 151 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && in adjustPqBits() 155 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits() 193 assert(Op1.isReg() && "First operand is not register."); in getRiMemoryOpValue() 225 assert(Op1.isReg() && "First operand is not register."); in getRrMemoryOpValue() 227 assert(Op2.isReg() && "Second operand is not register."); in getRrMemoryOpValue() 264 assert(Op1.isReg() && "First operand is not register."); in getSplsOpValue() 292 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCMacroFusion.cpp | 74 if (!Op1.isReg() || !Op2.isReg()) in matchingRegOps() 106 if (!RA.isReg()) in checkOpConstraints() 115 if (!RT.isReg()) in checkOpConstraints() 172 if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() != PPC::CR0)) in checkOpConstraints() 183 if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() != PPC::CR0)) in checkOpConstraints() 207 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints() 218 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineInstr.cpp | 168 if (MO.isReg()) in removeRegOperandsFromUseLists() 174 if (MO.isReg()) in addRegOperandsToUseLists() 263 if (NewMO->isReg()) { in addOperand() 298 if (Operands[i].isReg()) in removeOperand() 641 if (!MO.isReg()) { in isIdenticalTo() 915 if (!getOperand(OpIdx).isReg()) in getRegClassConstraint() 975 assert(MO.isReg() && in getRegClassConstraintEffect() 1543 if (!Op.isReg()) in getTypeToPrint() 2181 if (DebugOp.isReg()) in BuildMI() 2196 if (DebugOp.isReg()) in BuildMI() [all …]
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H A D | MIRCanonicalizerPass.cpp | 155 if (!MO.isReg()) in rescheduleCanonically() 175 if (!MO.isReg() || !MO.getReg().isVirtual()) in rescheduleCanonically() 187 if (II->getOperand(i).isReg()) { in rescheduleCanonically() 302 if (!MI->getOperand(0).isReg()) in propagateLocalCopies() 304 if (!MI->getOperand(1).isReg()) in propagateLocalCopies() 342 if (!MO.isReg()) in doDefKillClear()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiDelaySlotFiller.cpp | 107 assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() && in runOnMachineBasicBlock() 109 RI->getOperand(1).isReg() && in runOnMachineBasicBlock() 114 RI->getOperand(0).isReg() && in runOnMachineBasicBlock() 116 RI->getOperand(1).isReg() && in runOnMachineBasicBlock() 205 if (!MO.isReg() || !(Reg = MO.getReg())) in delayHasHazard() 234 if (!MO.isReg() || !(Reg = MO.getReg())) in insertDefsUses()
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H A D | LanaiMemAluCombiner.cpp | 184 return ((Op.isReg() && Op.getReg() == Lanai::R0) || in isZeroOperand() 246 assert((AluOffset.isReg() || AluOffset.isImm()) && in insertMergedInstruction() 263 if (AluOffset.isReg()) in insertMergedInstruction() 306 if (Offset.isReg() && Offset.getReg() == Lanai::R0) in isSuitableAluInstr() 317 } else if (Op2.isReg()) { in isSuitableAluInstr() 319 if (Offset.isReg() && Op2.getReg() == Offset.getReg()) in isSuitableAluInstr() 355 if (Offset->isReg() && InstrUsesReg(First, Offset)) in findClosestSuitableAluInstr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyDebugFixup.cpp | 71 if (MI.isDebugValue() && MI.getDebugOperand(0).isReg() && in setDanglingDebugValuesUndef() 100 if (MO.isReg() && MO.getReg().isValid() && in runOnMachineFunction() 127 if (MO.isReg() && MFI.isVRegStackified(MO.getReg())) { in runOnMachineFunction() 148 if (MO.isReg() && MFI.isVRegStackified(MO.getReg())) { in runOnMachineFunction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 681 if (Op1.isReg()) { in getLoopTripCount() 711 if (EndValue->isReg()) { in getLoopTripCount() 741 if (Start->isReg()) { in computeCount() 747 if (End->isReg()) { in computeCount() 855 bool RegToReg = Start->isReg() && End->isReg(); // for (reg..reg) in computeCount() 893 if (Start->isReg()) { in computeCount() 1212 if (TripCount->isReg()) { in convertToHardwareLoop() 1415 if (!InitVal->isReg()) in loopCountMayWrapOrUnderFlow() 1499 if (!MO.isReg()) in checkForImmediate() 1580 assert(MO.isReg()); in setImmediate() [all …]
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H A D | HexagonExpandCondsets.cpp | 604 if (SO.isReg()) { in getCondTfrOpcode() 663 if (SrcOp.isReg()) { in genCondTfrFor() 702 if (Op.isReg()) in split() 712 if (ST.isReg() && SF.isReg()) { in split() 823 if (!Op.isReg()) in canMoveOver() 923 if (Op.isReg()) in predicateAt() 1014 if (!Op.isReg()) in predicate() 1103 if (Op.isReg()) in predicateInBlock() 1215 if (!S1.isReg() && !S2.isReg()) in coalesceSegments() 1244 if (S1.isReg()) { in coalesceSegments() [all …]
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H A D | HexagonVLIWPacketizer.cpp | 152 if (!MO.isReg() || !MO.isDef()) in hasWriteToReadDep() 436 if (MO.isReg() && MO.getReg() == DestReg) in canPromoteToDotCur() 584 if (MO.isReg() && MO.isDef()) in getPostIncrementOperand() 658 if (Val.isReg() && Val.getReg() != DepReg) in canPromoteToNewValueStore() 711 if (!MO.isReg()) in canPromoteToNewValueStore() 723 if (!MO.isReg()) in canPromoteToNewValueStore() 785 if (MO.isReg() && MO.getReg() == DepReg) in canPromoteToNewValueStore() 955 if (Op.isReg() && Op.getReg() && Op.isUse() && in getPredicatedRegister() 1218 if (!MO.isReg() || !MO.isDef() || !MO.isDead()) in hasDeadDependence() 1287 if (OpI.isReg()) { in hasRegMaskDependence() [all …]
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H A D | HexagonNewValueJump.cpp | 151 if (!Op.isReg() || !Op.isDef()) in INITIALIZE_PASS_DEPENDENCY() 176 if (II->getOperand(i).isReg() && in INITIALIZE_PASS_DEPENDENCY() 561 if (foundJump && !foundCompare && MI.getOperand(0).isReg() && in runOnMachineFunction() 568 isSecondOpReg = MI.getOperand(2).isReg(); in runOnMachineFunction() 597 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() && in runOnMachineFunction() 648 if (!MO.isReg() || !MO.isUse()) in runOnMachineFunction() 655 if (!Op.isReg() || !Op.isUse() || !Op.isKill()) in runOnMachineFunction() 701 if (cmpInstr->getOperand(0).isReg() && in runOnMachineFunction() 704 if (cmpInstr->getOperand(1).isReg() && in runOnMachineFunction()
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H A D | HexagonSplitDouble.cpp | 179 if (MI->getOperand(1).isReg()) in isFixedInstr() 184 if (MI->getOperand(0).isReg()) in isFixedInstr() 211 if (!Op.isReg()) in isFixedInstr() 595 if (!Op.isReg()) { in createHalfInstr() 727 assert(Op0.isReg()); in splitCombine() 735 if (!Op1.isReg()) { in splitCombine() 743 if (!Op2.isReg()) { in splitCombine() 756 assert(Op0.isReg() && Op1.isReg()); in splitExt() 779 assert(Op0.isReg() && Op1.isReg() && Op2.isImm()); in splitShift() 904 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr() [all …]
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H A D | HexagonGenMux.cpp | 170 if (!MO.isReg() || MO.isImplicit()) in getDefsUses() 207 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode() 300 Register SR1 = Src1->isReg() ? Src1->getReg() : Register(); in genMuxInBlock() 301 Register SR2 = Src2->isReg() ? Src2->getReg() : Register(); in genMuxInBlock() 365 if (!Op.isReg() || !Op.isUse()) in genMuxInBlock()
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXProxyRegErasure.cpp | 97 assert(InOp.isReg() && "ProxyReg input operand should be a register."); in replaceMachineInstructionUsage() 98 assert(OutOp.isReg() && "ProxyReg output operand should be a register."); in replaceMachineInstructionUsage() 111 if (Op.isReg() && Op.getReg() == From.getReg()) { in replaceRegisterUsage()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
H A D | AVRMCCodeEmitter.cpp | 71 assert(MI.getOperand(0).isReg() && MI.getOperand(1).isReg() && in loadStorePostEncoder() 119 assert(MO.isReg()); in encodeLDSTPtrReg() 143 assert(RegOp.isReg() && "Expected register operand"); in encodeMemri() 259 if (MO.isReg()) in getMachineOpValue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcInstPrinter.cpp | 68 if (!MI->getOperand(0).isReg()) in printSparcAliasInstr() 92 || (!MI->getOperand(0).isReg()) in printSparcAliasInstr() 118 if (MO.isReg()) { in printOperand() 156 if (Op1.isReg() && Op1.getReg() != SP::G0) { in printMemOperand() 164 PrintedFirstOperand && ((Op2.isReg() && Op2.getReg() == SP::G0) || in printMemOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/AsmParser/ |
H A D | M68kAsmParser.cpp | 155 bool isReg() const override; 311 bool M68kOperand::isReg() const { in isReg() function in M68kOperand 316 assert(isReg()); in getReg() 321 assert(isReg() && "wrong operand kind"); in addRegOperands() 579 if (Operand.isReg() && in validateTargetOperandClass() 587 if (Operand.isReg() && in validateTargetOperandClass() 594 if (Operand.isReg() && in validateTargetOperandClass() 603 if (Operand.isReg() && in validateTargetOperandClass() 610 if (Operand.isReg() && in validateTargetOperandClass() 617 if (Operand.isReg() && in validateTargetOperandClass() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 49 if (MO.isReg() || MO.isImm()) in getDirectBrEncoding() 158 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding() 171 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding() 184 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding() 196 assert(MI.getOperand(OpNo).isReg() && "Operand should be a register"); in getVSRpEvenEncoding() 206 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding() 219 assert(!MO.isReg() && "Not expecting a register for this operand."); in getImm34Encoding() 429 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); in getTLSRegEncoding() 486 if (MO.isReg()) { in getMachineOpValue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
H A D | SPIRVPreLegalizer.cpp | 76 assert(MI.getOperand(2).isReg() && "Reg operand is expected"); in addConstantsToTrack() 107 while (MI.getOperand(NumOp).isReg()) { in foldConstantsIntoIntrinsics() 131 assert(MI.getOperand(2).isReg()); in insertBitcasts() 173 if (MI->getOperand(0).isReg()) { in propagateSPIRVType() 195 MachineInstr *Def = Op.isReg() ? MRI.getVRegDef(Op.getReg()) : nullptr; in propagateSPIRVType() 382 if (!Op.isReg() || Op.isDef()) in processInstr() 477 assert(MI.getOperand(1).isReg()); in processSwitches() 484 if (MI.getOpcode() == TargetOpcode::G_SUB && MI.getOperand(1).isReg() && in processSwitches() 486 assert(MI.getOperand(0).isReg() && MI.getOperand(1).isReg()); in processSwitches() 493 if (MI.getOpcode() == TargetOpcode::G_ICMP && MI.getOperand(2).isReg() && in processSwitches() [all …]
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