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/freebsd/sys/dev/mlx4/mlx4_core/
H A Dmlx4_fw_qos.c94 if (IS_ERR(mailbox)) in mlx4_SET_PORT_PRIO2TC()
95 return PTR_ERR(mailbox); in mlx4_SET_PORT_PRIO2TC()
97 context = mailbox->buf; in mlx4_SET_PORT_PRIO2TC()
121 if (IS_ERR(mailbox)) in mlx4_SET_PORT_SCHEDULER()
124 context = mailbox->buf; in mlx4_SET_PORT_SCHEDULER()
168 if (IS_ERR(mailbox)) in mlx4_ALLOCATE_VPP_get()
202 if (IS_ERR(mailbox)) in mlx4_ALLOCATE_VPP_set()
230 if (IS_ERR(mailbox)) in mlx4_SET_VPORT_QOS_get()
233 ctx = mailbox->buf; in mlx4_SET_VPORT_QOS_get()
267 if (IS_ERR(mailbox)) in mlx4_SET_VPORT_QOS_set()
[all …]
H A Dmlx4_cq.c112 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, in mlx4_HW2SW_CQ()
120 struct mlx4_cmd_mailbox *mailbox; in mlx4_cq_modify() local
125 if (IS_ERR(mailbox)) in mlx4_cq_modify()
126 return PTR_ERR(mailbox); in mlx4_cq_modify()
128 cq_context = mailbox->buf; in mlx4_cq_modify()
148 if (IS_ERR(mailbox)) in mlx4_cq_resize()
149 return PTR_ERR(mailbox); in mlx4_cq_resize()
151 cq_context = mailbox->buf; in mlx4_cq_resize()
265 if (IS_ERR(mailbox)) { in mlx4_cq_alloc()
266 err = PTR_ERR(mailbox); in mlx4_cq_alloc()
[all …]
H A Dmlx4_srq.c75 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, srq_num, in mlx4_HW2SW_SRQ()
166 struct mlx4_cmd_mailbox *mailbox; in mlx4_srq_alloc() local
182 if (IS_ERR(mailbox)) { in mlx4_srq_alloc()
183 err = PTR_ERR(mailbox); in mlx4_srq_alloc()
187 srq_context = mailbox->buf; in mlx4_srq_alloc()
202 mlx4_free_cmd_mailbox(dev, mailbox); in mlx4_srq_alloc()
251 struct mlx4_cmd_mailbox *mailbox; in mlx4_srq_query() local
256 if (IS_ERR(mailbox)) in mlx4_srq_query()
257 return PTR_ERR(mailbox); in mlx4_srq_query()
259 srq_context = mailbox->buf; in mlx4_srq_query()
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H A Dmlx4_mcg.c195 if (IS_ERR(mailbox)) { in new_steering_entry()
199 mgm = mailbox->buf; in new_steering_entry()
344 if (IS_ERR(mailbox)) in promisc_steering_entry()
346 mgm = mailbox->buf; in promisc_steering_entry()
458 mgm = mailbox->buf; in add_promisc_qp()
588 mgm = mailbox->buf; in remove_promisc_qp()
621 mailbox); in remove_promisc_qp()
708 if (IS_ERR(mailbox)) in find_entry()
710 mgid = mailbox->buf; in find_entry()
1122 mgm = mailbox->buf; in mlx4_qp_attach_common()
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H A Dmlx4_fw.c189 if (IS_ERR(mailbox)) in mlx4_MOD_STAT_CFG()
191 inbox = mailbox->buf; in mlx4_MOD_STAT_CFG()
221 if (IS_ERR(mailbox)) in mlx4_QUERY_FUNC()
223 outbox = mailbox->buf; in mlx4_QUERY_FUNC()
555 if (IS_ERR(mailbox)) in mlx4_QUERY_FUNC_CAP()
831 if (IS_ERR(mailbox)) in mlx4_QUERY_DEV_CAP()
1179 if (IS_ERR(mailbox)) in mlx4_QUERY_PORT()
1478 if (IS_ERR(mailbox)) in mlx4_get_slave_pkey_gid_tbl_len()
1513 if (IS_ERR(mailbox)) in mlx4_map_cmd()
1631 if (IS_ERR(mailbox)) in mlx4_QUERY_FW()
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H A Dmlx4_mr.c293 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index, in mlx4_HW2SW_MPT()
324 if (IS_ERR(mailbox)) in mlx4_mr_hw_get_mpt()
325 return PTR_ERR(mailbox); in mlx4_mr_hw_get_mpt()
643 if (IS_ERR(mailbox)) { in mlx4_mr_enable()
644 err = PTR_ERR(mailbox); in mlx4_mr_enable()
765 if (IS_ERR(mailbox)) in mlx4_write_mtt()
767 inbox = mailbox->buf; in mlx4_write_mtt()
855 if (IS_ERR(mailbox)) { in mlx4_mw_enable()
856 err = PTR_ERR(mailbox); in mlx4_mw_enable()
1122 if (IS_ERR(mailbox)) { in mlx4_fmr_unmap()
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/freebsd/sys/dev/mthca/
H A Dmthca_mcg.c67 struct mthca_mailbox *mailbox; in find_mgm() local
73 if (IS_ERR(mailbox)) in find_mgm()
75 mgid = mailbox->buf; in find_mgm()
123 struct mthca_mailbox *mailbox; in mthca_multicast_attach() local
132 if (IS_ERR(mailbox)) in mthca_multicast_attach()
133 return PTR_ERR(mailbox); in mthca_multicast_attach()
134 mgm = mailbox->buf; in mthca_multicast_attach()
225 if (IS_ERR(mailbox)) in mthca_multicast_detach()
226 return PTR_ERR(mailbox); in mthca_multicast_detach()
227 mgm = mailbox->buf; in mthca_multicast_detach()
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H A Dmthca_cmd.c609 mailbox = kmalloc(sizeof *mailbox, gfp_mask); in mthca_alloc_mailbox()
610 if (!mailbox) in mthca_alloc_mailbox()
613 mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma); in mthca_alloc_mailbox()
615 kfree(mailbox); in mthca_alloc_mailbox()
619 return mailbox; in mthca_alloc_mailbox()
624 if (!mailbox) in mthca_free_mailbox()
627 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma); in mthca_free_mailbox()
628 kfree(mailbox); in mthca_free_mailbox()
1615 return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index, in mthca_HW2SW_MPT()
1782 if (!mailbox) { in mthca_MODIFY_QP()
[all …]
H A Dmthca_cmd.h283 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
285 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
292 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
294 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
296 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
298 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
306 struct mthca_mailbox *mailbox);
310 struct mthca_mailbox *mailbox, u32 optmask);
312 struct mthca_mailbox *mailbox);
318 struct mthca_mailbox *mailbox);
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/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dxlnx,zynqmp-ipi-mailbox.yaml4 $id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#
41 - xlnx,zynqmp-ipi-mailbox
42 - xlnx,versal-ipi-mailbox
80 '^mailbox@[0-9a-f]+$':
88 - xlnx,zynqmp-ipi-dest-mailbox
89 - xlnx,versal-ipi-dest-mailbox
192 zynqmp-mailbox {
200 mailbox: mailbox@ff9905c0 {
222 mailbox@ff300000 {
234 mailbox@ff340000 {
[all …]
H A Domap-mailbox.txt83 mailbox device nodes.
90 Sub-mailbox Descriptor Data
115 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
127 mailbox: mailbox@4a0f4000 {
128 compatible = "ti,omap4-mailbox";
131 ti,hwmods = "mailbox";
147 mboxes = <&mailbox &mbox_dsp>;
152 mailbox: mailbox@480c8000 {
153 compatible = "ti,omap4-mailbox";
156 ti,hwmods = "mailbox";
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H A Dmicrochip,mpfs-mailbox.yaml4 $id: http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#
7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
14 const: microchip,mpfs-mailbox
19 - description: mailbox control & data registers
20 - description: mailbox interrupt registers
23 - description: mailbox control registers
24 - description: mailbox interrupt registers
25 - description: mailbox data registers
46 mbox: mailbox@37020000 {
47 compatible = "microchip,mpfs-mailbox";
H A Dti,omap-mailbox.yaml4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
56 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
86 omap-sub-mailbox:
167 $ref: "#/$defs/omap-sub-mailbox"
182 - ti,am654-mailbox
183 - ti,am64-mailbox
198 - ti,omap4-mailbox
213 - ti,omap3-mailbox
228 - ti,omap2-mailbox
245 mailbox: mailbox@4a0f4000 {
[all …]
H A Dapple,mailbox.yaml4 $id: http://devicetree.org/schemas/mailbox/apple,mailbox.yaml#
31 - apple,t8103-asc-mailbox
32 - apple,t8112-asc-mailbox
33 - apple,t6000-asc-mailbox
34 - const: apple,asc-mailbox-v4
42 - apple,t8103-m3-mailbox
43 - apple,t8112-m3-mailbox
44 - apple,t6000-m3-mailbox
45 - const: apple,m3-mailbox-v2
81 mailbox@77408000 {
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H A Dmailbox.txt4 assign appropriate mailbox channel to client drivers.
9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
13 mailbox: mailbox {
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
27 users of these mailboxes for IPC, one for each mailbox. This shared
29 communication between the mailbox client and the remote.
36 mboxes = <&mailbox 0 &mailbox 1>;
57 mboxes = <&mailbox 0>;
H A Daltera-mailbox.txt5 - compatible : "altr,mailbox-1.0".
6 - reg : physical base address of the mailbox and length of
8 - #mbox-cells: Common mailbox binding property to identify the number
9 of cells required for the mailbox specifier. Should be 1.
16 mbox_tx: mailbox@100 {
17 compatible = "altr,mailbox-1.0";
24 mbox_rx: mailbox@200 {
25 compatible = "altr,mailbox-1.0";
35 Documentation/devicetree/bindings/mailbox/mailbox.txt for details). Each value
36 of the mboxes property should contain a phandle to the mailbox controller
H A Dxlnx,zynqmp-ipi-mailbox.txt4 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
35 - compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
43 Internal IPI mailbox node:
73 - mboxes: Standard property to specify a mailbox
74 (See ./mailbox.txt)
75 - mbox-names: List of identifier strings for each mailbox
81 compatible = "xlnx,zynqmp-ipi-mailbox";
89 /* APU<->RPU0 IPI mailbox controller */
90 ipi_mailbox_rpu0: mailbox@ff990400 {
102 /* APU<->RPU1 IPI mailbox controller */
[all …]
H A Dhisilicon,hi6220-mailbox.txt4 Hisilicon Hi6220 mailbox supports up to 32 channels. Each channel
15 - reg: Contains the mailbox register address range (base
19 - #mbox-cells: Common mailbox binding property to identify the number
20 of cells required for the mailbox specifier. Must be 3.
22 phandle: Label name of mailbox controller
27 mailbox driver uses it to acknowledge interrupt
28 - interrupts: Contains the interrupt information for the mailbox
34 - hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver
42 mailbox: mailbox@f7510000 {
58 - mboxes: Standard property to specify a Mailbox (See ./mailbox.txt)
[all …]
H A Dmicrochip,polarfire-soc-mailbox.yaml4 $id: "http://devicetree.org/schemas/mailbox/microchip,polarfire-soc-mailbox.yaml#"
7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
14 const: microchip,polarfire-soc-mailbox
18 - description: mailbox data registers
19 - description: mailbox interrupt registers
40 mbox: mailbox@37020000 {
41 compatible = "microchip,polarfire-soc-mailbox";
H A Dxgene-slimpro-mailbox.txt1 The APM X-Gene SLIMpro mailbox is used to communicate messages between
6 There are total of 8 interrupts in this mailbox. Each used for an individual
7 door bell (or mailbox channel).
12 - reg: Contains the mailbox register address range.
15 the interrupt for mailbox channel 0 and interrupt 1 for
16 mailbox channel 1 and so likewise for the reminder.
18 - #mbox-cells: only one to specify the mailbox channel number.
23 mailbox: mailbox@10540000 {
H A Dsprd-mailbox.yaml4 $id: http://devicetree.org/schemas/mailbox/sprd-mailbox.yaml#
7 title: Spreadtrum mailbox controller
17 - sprd,sc9860-mailbox
18 - sprd,sc9863a-mailbox
60 mailbox: mailbox@400a0000 {
61 compatible = "sprd,sc9860-mailbox";
H A Drockchip-mailbox.txt1 Rockchip mailbox
3 The Rockchip mailbox is used by the Rockchip CPU cores to communicate
6 Refer to ./mailbox.txt for generic information about mailbox device-tree
17 - #mbox-cells: Common mailbox binding property to identify the number
18 of cells required for the mailbox specifier. Should be 1
25 compatible = "rockchip,rk3368-mailbox";
H A Dst,sti-mailbox.yaml4 $id: http://devicetree.org/schemas/mailbox/st,sti-mailbox.yaml#
19 const: st,stih407-mailbox
26 description: name of the mailbox IP
29 description: the irq line for the RX mailbox
45 mailbox0: mailbox@8f00000 {
46 compatible = "st,stih407-mailbox";
H A Dnvidia,tegra186-hsp.yaml4 $id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
26 second cell is used to identify the mailbox that the client is going
32 mailbox to be used (based on the data size). If no flag is
33 specified then, 32-bit shared mailbox is used.
35 Defines the type of the mailbox to be used. This field should be
43 A bit mask of flags that further specify how the shared mailbox
46 Defines the direction of the mailbox. If set, the mailbox
48 cleared, the mailbox is the consumer of data sent by a
57 construct mailbox specifiers:
59 <dt-bindings/mailbox/tegra186-hsp.h>
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H A Dbrcm,bcm2835-mbox.txt1 Broadcom BCM2835 VideoCore mailbox IPC
9 - #mbox-cells: Specifies the number of cells needed to encode a mailbox
11 mailbox channel implemented by the device.
15 mailbox: mailbox@7e00b880 {
24 mboxes = <&mailbox>;

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