1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright (c) 2024, Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef _ICE_TYPE_H_
33 #define _ICE_TYPE_H_
34
35 #include "ice_defs.h"
36 #include "ice_status.h"
37 #include "ice_hw_autogen.h"
38 #include "ice_devids.h"
39 #include "ice_osdep.h"
40 #include "ice_bitops.h" /* Must come before ice_controlq.h */
41 #include "ice_lan_tx_rx.h"
42 #include "ice_ddp_common.h"
43 #include "ice_controlq.h"
44 #include "ice_flex_type.h"
45 #include "ice_protocol_type.h"
46 #include "ice_sbq_cmd.h"
47 #include "ice_vlan_mode.h"
48 #include "ice_fwlog.h"
49
ice_is_tc_ena(ice_bitmap_t bitmap,u8 tc)50 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
51 {
52 return !!(bitmap & BIT(tc));
53 }
54
55 /**
56 * DIV_S64 - Divide signed 64-bit value with signed 64-bit divisor
57 * @dividend: value to divide
58 * @divisor: value to divide by
59 *
60 * Use DIV_S64 for any 64-bit divide which operates on signed 64-bit dividends.
61 * Do not use this for unsigned 64-bit dividends as it will not produce
62 * correct results if the dividend is larger than S64_MAX.
63 */
DIV_S64(s64 dividend,s64 divisor)64 static inline s64 DIV_S64(s64 dividend, s64 divisor)
65 {
66 return dividend / divisor;
67 }
68
69 /**
70 * DIV_U64 - Divide unsigned 64-bit value by unsigned 64-bit divisor
71 * @dividend: value to divide
72 * @divisor: value to divide by
73 *
74 * Use DIV_U64 for any 64-bit divide which operates on unsigned 64-bit
75 * dividends. Do not use this for signed 64-bit dividends as it will not
76 * handle negative values correctly.
77 */
DIV_U64(u64 dividend,u64 divisor)78 static inline u64 DIV_U64(u64 dividend, u64 divisor)
79 {
80 return dividend / divisor;
81 }
82
round_up_64bit(u64 a,u32 b)83 static inline u64 round_up_64bit(u64 a, u32 b)
84 {
85 return DIV_U64(((a) + (b) / 2), (b));
86 }
87
ice_round_to_num(u32 N,u32 R)88 static inline u32 ice_round_to_num(u32 N, u32 R)
89 {
90 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
91 ((((N) + (R) - 1) / (R)) * (R)));
92 }
93
94 /* Driver always calls main vsi_handle first */
95 #define ICE_MAIN_VSI_HANDLE 0
96
97 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
98 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
99
100 /* Data type manipulation macros. */
101 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
102 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
103 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
104 #define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF))
105 #define ICE_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
106 #define ICE_LO_BYTE(x) ((u8)((x) & 0xFF))
107
108 /* debug masks - set these bits in hw->debug_mask to control output */
109 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
110 #define ICE_DBG_INIT BIT_ULL(1)
111 #define ICE_DBG_RELEASE BIT_ULL(2)
112 #define ICE_DBG_FW_LOG BIT_ULL(3)
113 #define ICE_DBG_LINK BIT_ULL(4)
114 #define ICE_DBG_PHY BIT_ULL(5)
115 #define ICE_DBG_QCTX BIT_ULL(6)
116 #define ICE_DBG_NVM BIT_ULL(7)
117 #define ICE_DBG_LAN BIT_ULL(8)
118 #define ICE_DBG_FLOW BIT_ULL(9)
119 #define ICE_DBG_DCB BIT_ULL(10)
120 #define ICE_DBG_DIAG BIT_ULL(11)
121 #define ICE_DBG_FD BIT_ULL(12)
122 #define ICE_DBG_SW BIT_ULL(13)
123 #define ICE_DBG_SCHED BIT_ULL(14)
124
125 #define ICE_DBG_RDMA BIT_ULL(15)
126 #define ICE_DBG_PKG BIT_ULL(16)
127 #define ICE_DBG_RES BIT_ULL(17)
128 #define ICE_DBG_AQ_MSG BIT_ULL(24)
129 #define ICE_DBG_AQ_DESC BIT_ULL(25)
130 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
131 #define ICE_DBG_AQ_CMD BIT_ULL(27)
132 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
133 ICE_DBG_AQ_DESC | \
134 ICE_DBG_AQ_DESC_BUF | \
135 ICE_DBG_AQ_CMD)
136 #define ICE_DBG_PARSER BIT_ULL(28)
137
138 #define ICE_DBG_USER BIT_ULL(31)
139 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
140
141 #define IS_UNICAST_ETHER_ADDR(addr) \
142 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 0))
143
144 #define IS_MULTICAST_ETHER_ADDR(addr) \
145 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 1))
146
147 /* Check whether an address is broadcast. */
148 #define IS_BROADCAST_ETHER_ADDR(addr) \
149 ((bool)((((u16 *)(addr))[0] == ((u16)0xffff))))
150
151 #define IS_ZERO_ETHER_ADDR(addr) \
152 (((bool)((((u16 *)(addr))[0] == ((u16)0x0)))) && \
153 ((bool)((((u16 *)(addr))[1] == ((u16)0x0)))) && \
154 ((bool)((((u16 *)(addr))[2] == ((u16)0x0)))))
155
156 #ifndef IS_ETHER_ADDR_EQUAL
157 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
158 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
159 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
160 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2]))))
161 #endif
162
163 enum ice_aq_res_ids {
164 ICE_NVM_RES_ID = 1,
165 ICE_SPD_RES_ID,
166 ICE_CHANGE_LOCK_RES_ID,
167 ICE_GLOBAL_CFG_LOCK_RES_ID
168 };
169
170 /* FW update timeout definitions are in milliseconds */
171 #define ICE_NVM_TIMEOUT 180000
172 #define ICE_CHANGE_LOCK_TIMEOUT 1000
173 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
174
175 struct ice_driver_ver {
176 u8 major_ver;
177 u8 minor_ver;
178 u8 build_ver;
179 u8 subbuild_ver;
180 u8 driver_string[32];
181 };
182
183 enum ice_fc_mode {
184 ICE_FC_NONE = 0,
185 ICE_FC_RX_PAUSE,
186 ICE_FC_TX_PAUSE,
187 ICE_FC_FULL,
188 ICE_FC_AUTO,
189 ICE_FC_PFC,
190 ICE_FC_DFLT
191 };
192
193 enum ice_phy_cache_mode {
194 ICE_FC_MODE = 0,
195 ICE_SPEED_MODE,
196 ICE_FEC_MODE
197 };
198
199 enum ice_fec_mode {
200 ICE_FEC_NONE = 0,
201 ICE_FEC_RS,
202 ICE_FEC_BASER,
203 ICE_FEC_AUTO,
204 ICE_FEC_DIS_AUTO
205 };
206
207 struct ice_phy_cache_mode_data {
208 union {
209 enum ice_fec_mode curr_user_fec_req;
210 enum ice_fc_mode curr_user_fc_req;
211 u16 curr_user_speed_req;
212 } data;
213 };
214
215 enum ice_set_fc_aq_failures {
216 ICE_SET_FC_AQ_FAIL_NONE = 0,
217 ICE_SET_FC_AQ_FAIL_GET,
218 ICE_SET_FC_AQ_FAIL_SET,
219 ICE_SET_FC_AQ_FAIL_UPDATE
220 };
221
222 /* These are structs for managing the hardware information and the operations */
223 /* MAC types */
224 enum ice_mac_type {
225 ICE_MAC_UNKNOWN = 0,
226 ICE_MAC_VF,
227 ICE_MAC_E810,
228 ICE_MAC_E830,
229 ICE_MAC_GENERIC,
230 ICE_MAC_GENERIC_3K,
231 ICE_MAC_GENERIC_3K_E825,
232 };
233
234 /* Media Types */
235 enum ice_media_type {
236 ICE_MEDIA_NONE = 0,
237 ICE_MEDIA_UNKNOWN,
238 ICE_MEDIA_FIBER,
239 ICE_MEDIA_BASET,
240 ICE_MEDIA_BACKPLANE,
241 ICE_MEDIA_DA,
242 ICE_MEDIA_AUI,
243 };
244
245 #define ICE_MEDIA_BASET_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_100BASE_TX | \
246 ICE_PHY_TYPE_LOW_1000BASE_T | \
247 ICE_PHY_TYPE_LOW_2500BASE_T | \
248 ICE_PHY_TYPE_LOW_5GBASE_T | \
249 ICE_PHY_TYPE_LOW_10GBASE_T | \
250 ICE_PHY_TYPE_LOW_25GBASE_T)
251
252 #define ICE_MEDIA_C2M_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC | \
253 ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC | \
254 ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC | \
255 ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC | \
256 ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC | \
257 ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC | \
258 ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC | \
259 ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC)
260
261 #define ICE_MEDIA_C2M_PHY_TYPE_HIGH_M (ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC | \
262 ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC | \
263 ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC | \
264 ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC)
265
266 #define ICE_MEDIA_OPT_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_1000BASE_SX | \
267 ICE_PHY_TYPE_LOW_1000BASE_LX | \
268 ICE_PHY_TYPE_LOW_10GBASE_SR | \
269 ICE_PHY_TYPE_LOW_10GBASE_LR | \
270 ICE_PHY_TYPE_LOW_25GBASE_SR | \
271 ICE_PHY_TYPE_LOW_25GBASE_LR | \
272 ICE_PHY_TYPE_LOW_40GBASE_SR4 | \
273 ICE_PHY_TYPE_LOW_40GBASE_LR4 | \
274 ICE_PHY_TYPE_LOW_50GBASE_SR2 | \
275 ICE_PHY_TYPE_LOW_50GBASE_LR2 | \
276 ICE_PHY_TYPE_LOW_50GBASE_SR | \
277 ICE_PHY_TYPE_LOW_50GBASE_LR | \
278 ICE_PHY_TYPE_LOW_100GBASE_SR4 | \
279 ICE_PHY_TYPE_LOW_100GBASE_LR4 | \
280 ICE_PHY_TYPE_LOW_100GBASE_SR2 | \
281 ICE_PHY_TYPE_LOW_50GBASE_FR | \
282 ICE_PHY_TYPE_LOW_100GBASE_DR)
283
284 #define ICE_MEDIA_OPT_PHY_TYPE_HIGH_M (ICE_PHY_TYPE_HIGH_200G_SR4 | \
285 ICE_PHY_TYPE_HIGH_200G_LR4 | \
286 ICE_PHY_TYPE_HIGH_200G_FR4 | \
287 ICE_PHY_TYPE_HIGH_200G_DR4 | \
288 ICE_PHY_TYPE_HIGH_400GBASE_FR8)
289
290 #define ICE_MEDIA_BP_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_1000BASE_KX | \
291 ICE_PHY_TYPE_LOW_2500BASE_KX | \
292 ICE_PHY_TYPE_LOW_5GBASE_KR | \
293 ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 | \
294 ICE_PHY_TYPE_LOW_25GBASE_KR | \
295 ICE_PHY_TYPE_LOW_25GBASE_KR_S | \
296 ICE_PHY_TYPE_LOW_25GBASE_KR1 | \
297 ICE_PHY_TYPE_LOW_40GBASE_KR4 | \
298 ICE_PHY_TYPE_LOW_50GBASE_KR2 | \
299 ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 | \
300 ICE_PHY_TYPE_LOW_100GBASE_KR4 | \
301 ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4)
302
303 #define ICE_MEDIA_BP_PHY_TYPE_HIGH_M (ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 | \
304 ICE_PHY_TYPE_HIGH_200G_KR4_PAM4)
305
306 #define ICE_MEDIA_DAC_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_10G_SFI_DA | \
307 ICE_PHY_TYPE_LOW_25GBASE_CR | \
308 ICE_PHY_TYPE_LOW_25GBASE_CR_S | \
309 ICE_PHY_TYPE_LOW_25GBASE_CR1 | \
310 ICE_PHY_TYPE_LOW_40GBASE_CR4 | \
311 ICE_PHY_TYPE_LOW_50GBASE_CR2 | \
312 ICE_PHY_TYPE_LOW_100GBASE_CR4 | \
313 ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 | \
314 ICE_PHY_TYPE_LOW_50GBASE_CP | \
315 ICE_PHY_TYPE_LOW_100GBASE_CP2)
316
317 #define ICE_MEDIA_DAC_PHY_TYPE_HIGH_M ICE_PHY_TYPE_HIGH_200G_CR4_PAM4
318
319 #define ICE_MEDIA_C2C_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_100M_SGMII | \
320 ICE_PHY_TYPE_LOW_1G_SGMII | \
321 ICE_PHY_TYPE_LOW_2500BASE_X | \
322 ICE_PHY_TYPE_LOW_10G_SFI_C2C | \
323 ICE_PHY_TYPE_LOW_25G_AUI_C2C | \
324 ICE_PHY_TYPE_LOW_40G_XLAUI | \
325 ICE_PHY_TYPE_LOW_50G_LAUI2 | \
326 ICE_PHY_TYPE_LOW_50G_AUI2 | \
327 ICE_PHY_TYPE_LOW_50G_AUI1 | \
328 ICE_PHY_TYPE_LOW_100G_CAUI4 | \
329 ICE_PHY_TYPE_LOW_100G_AUI4)
330
331 #define ICE_MEDIA_C2C_PHY_TYPE_HIGH_M (ICE_PHY_TYPE_HIGH_100G_CAUI2 | \
332 ICE_PHY_TYPE_HIGH_100G_AUI2 | \
333 ICE_PHY_TYPE_HIGH_200G_AUI4 | \
334 ICE_PHY_TYPE_HIGH_200G_AUI8)
335
336 /* Software VSI types. */
337 enum ice_vsi_type {
338 ICE_VSI_PF = 0,
339 ICE_VSI_VF = 1,
340 ICE_VSI_VMDQ2 = 2,
341 ICE_VSI_LB = 6,
342 };
343
344 struct ice_link_status {
345 /* Refer to ice_aq_phy_type for bits definition */
346 u64 phy_type_low;
347 u64 phy_type_high;
348 u8 topo_media_conflict;
349 u16 max_frame_size;
350 u16 link_speed;
351 u16 req_speeds;
352 u8 link_cfg_err;
353 u8 lse_ena; /* Link Status Event notification */
354 u8 link_info;
355 u8 an_info;
356 u8 ext_info;
357 u8 fec_info;
358 u8 pacing;
359 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
360 * ice_aqc_get_phy_caps structure
361 */
362 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
363 };
364
365 /* Different data queue types: These are mainly for SW consumption. */
366 enum ice_q {
367 ICE_DATA_Q_DOORBELL,
368 ICE_DATA_Q_CMPL,
369 ICE_DATA_Q_QUANTA,
370 ICE_DATA_Q_RX,
371 ICE_DATA_Q_TX,
372 };
373
374 /* Different reset sources for which a disable queue AQ call has to be made in
375 * order to clean the Tx scheduler as a part of the reset
376 */
377 enum ice_disq_rst_src {
378 ICE_NO_RESET = 0,
379 ICE_VM_RESET,
380 ICE_VF_RESET,
381 };
382
383 /* PHY info such as phy_type, etc... */
384 struct ice_phy_info {
385 struct ice_link_status link_info;
386 struct ice_link_status link_info_old;
387 u64 phy_type_low;
388 u64 phy_type_high;
389 enum ice_media_type media_type;
390 u8 get_link_info;
391 /* Please refer to struct ice_aqc_get_link_status_data to get
392 * detail of enable bit in curr_user_speed_req
393 */
394 u16 curr_user_speed_req;
395 enum ice_fec_mode curr_user_fec_req;
396 enum ice_fc_mode curr_user_fc_req;
397 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
398 };
399
400 #define ICE_MAX_NUM_MIRROR_RULES 64
401
402 #define ICE_L2TPV2_FLAGS_CTRL 0x8000
403 #define ICE_L2TPV2_FLAGS_LEN 0x4000
404 #define ICE_L2TPV2_FLAGS_SEQ 0x0800
405 #define ICE_L2TPV2_FLAGS_OFF 0x0200
406 #define ICE_L2TPV2_FLAGS_VER 0x0002
407
408 #define ICE_L2TPV2_PKT_LENGTH 6
409 #define ICE_PPP_PKT_LENGTH 4
410
411 /* Common HW capabilities for SW use */
412 struct ice_hw_common_caps {
413 /* Write CSR protection */
414 u64 wr_csr_prot;
415 u32 switching_mode;
416 /* switching mode supported - EVB switching (including cloud) */
417 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
418
419 /* Manageablity mode & supported protocols over MCTP */
420 u32 mgmt_mode;
421 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
422 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
423 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
424
425 u32 mgmt_protocols_mctp;
426 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
427 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
428 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
429 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
430
431 u32 os2bmc;
432 u32 valid_functions;
433 /* DCB capabilities */
434 u32 active_tc_bitmap;
435 u32 maxtc;
436
437 /* RSS related capabilities */
438 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
439 u32 rss_table_entry_width; /* RSS Entry width in bits */
440
441 /* Tx/Rx queues */
442 u32 num_rxq; /* Number/Total Rx queues */
443 u32 rxq_first_id; /* First queue ID for Rx queues */
444 u32 num_txq; /* Number/Total Tx queues */
445 u32 txq_first_id; /* First queue ID for Tx queues */
446
447 /* MSI-X vectors */
448 u32 num_msix_vectors;
449 u32 msix_vector_first_id;
450
451 /* Max MTU for function or device */
452 u32 max_mtu;
453
454 /* WOL related */
455 u32 num_wol_proxy_fltr;
456 u32 wol_proxy_vsi_seid;
457
458 /* LED/SDP pin count */
459 u32 led_pin_num;
460 u32 sdp_pin_num;
461
462 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
463 #define ICE_MAX_SUPPORTED_GPIO_LED 12
464 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
465 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
466 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
467
468 /* SR-IOV virtualization */
469 u8 sr_iov_1_1; /* SR-IOV enabled */
470
471 /* VMDQ */
472 u8 vmdq; /* VMDQ supported */
473
474 /* EVB capabilities */
475 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
476 u8 evb_802_1_qbh; /* Bridge Port Extension */
477
478 u8 dcb;
479 u8 iscsi;
480 u8 mgmt_cem;
481 u8 iwarp;
482 u8 roce_lag;
483
484 /* WoL and APM support */
485 #define ICE_WOL_SUPPORT_M BIT(0)
486 #define ICE_ACPI_PROG_MTHD_M BIT(1)
487 #define ICE_PROXY_SUPPORT_M BIT(2)
488 u8 apm_wol_support;
489 u8 acpi_prog_mthd;
490 u8 proxy_support;
491 bool sec_rev_disabled;
492 bool update_disabled;
493 bool nvm_unified_update;
494 bool netlist_auth;
495 #define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0)
496 #define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1)
497 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
498 #define ICE_NVM_MGMT_NETLIST_AUTH_SUPPORT BIT(5)
499 /* PCIe reset avoidance */
500 bool pcie_reset_avoidance; /* false: not supported, true: supported */
501 /* Post update reset restriction */
502 bool reset_restrict_support; /* false: not supported, true: supported */
503
504 /* External topology device images within the NVM */
505 #define ICE_EXT_TOPO_DEV_IMG_COUNT 4
506 u32 ext_topo_dev_img_ver_high[ICE_EXT_TOPO_DEV_IMG_COUNT];
507 u32 ext_topo_dev_img_ver_low[ICE_EXT_TOPO_DEV_IMG_COUNT];
508 u8 ext_topo_dev_img_part_num[ICE_EXT_TOPO_DEV_IMG_COUNT];
509 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_S 8
510 #define ICE_EXT_TOPO_DEV_IMG_PART_NUM_M \
511 MAKEMASK(0xFF, ICE_EXT_TOPO_DEV_IMG_PART_NUM_S)
512 bool ext_topo_dev_img_load_en[ICE_EXT_TOPO_DEV_IMG_COUNT];
513 #define ICE_EXT_TOPO_DEV_IMG_LOAD_EN BIT(0)
514 bool ext_topo_dev_img_prog_en[ICE_EXT_TOPO_DEV_IMG_COUNT];
515 #define ICE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1)
516 bool ext_topo_dev_img_ver_schema[ICE_EXT_TOPO_DEV_IMG_COUNT];
517 #define ICE_EXT_TOPO_DEV_IMG_VER_SCHEMA BIT(2)
518 bool tx_sched_topo_comp_mode_en;
519 bool dyn_flattening_en;
520 /* Support for OROM update in Recovery Mode */
521 bool orom_recovery_update;
522 bool next_cluster_id_support;
523 };
524
525 #define ICE_NAC_TOPO_PRIMARY_M BIT(0)
526 #define ICE_NAC_TOPO_DUAL_M BIT(1)
527 #define ICE_NAC_TOPO_ID_M MAKEMASK(0xf, 0)
528
529 struct ice_nac_topology {
530 u32 mode;
531 u8 id;
532 };
533
534 /* Function specific capabilities */
535 struct ice_hw_func_caps {
536 struct ice_hw_common_caps common_cap;
537 u32 num_allocd_vfs; /* Number of allocated VFs */
538 u32 vf_base_id; /* Logical ID of the first VF */
539 u32 guar_num_vsi;
540 };
541
542 /* Device wide capabilities */
543 struct ice_hw_dev_caps {
544 struct ice_hw_common_caps common_cap;
545 u32 num_vfs_exposed; /* Total number of VFs exposed */
546 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
547 u32 num_funcs;
548 struct ice_nac_topology nac_topo;
549 /* bitmap of supported sensors */
550 u32 supported_sensors;
551 #define ICE_SENSOR_SUPPORT_E810_INT_TEMP BIT(0)
552 };
553
554 /* Information about MAC such as address, etc... */
555 struct ice_mac_info {
556 u8 lan_addr[ETH_ALEN];
557 u8 perm_addr[ETH_ALEN];
558 u8 port_addr[ETH_ALEN];
559 u8 wol_addr[ETH_ALEN];
560 };
561
562 /* PCI bus types */
563 enum ice_bus_type {
564 ice_bus_unknown = 0,
565 ice_bus_pci_express,
566 ice_bus_embedded, /* Is device Embedded versus card */
567 ice_bus_reserved
568 };
569
570 /* PCI bus speeds */
571 enum ice_pcie_bus_speed {
572 ice_pcie_speed_unknown = 0xff,
573 ice_pcie_speed_2_5GT = 0x14,
574 ice_pcie_speed_5_0GT = 0x15,
575 ice_pcie_speed_8_0GT = 0x16,
576 ice_pcie_speed_16_0GT = 0x17,
577 ice_pcie_speed_32_0GT = 0x18,
578 };
579
580 /* PCI bus widths */
581 enum ice_pcie_link_width {
582 ice_pcie_lnk_width_resrv = 0x00,
583 ice_pcie_lnk_x1 = 0x01,
584 ice_pcie_lnk_x2 = 0x02,
585 ice_pcie_lnk_x4 = 0x04,
586 ice_pcie_lnk_x8 = 0x08,
587 ice_pcie_lnk_x12 = 0x0C,
588 ice_pcie_lnk_x16 = 0x10,
589 ice_pcie_lnk_x32 = 0x20,
590 ice_pcie_lnk_width_unknown = 0xff,
591 };
592
593 /* Reset types used to determine which kind of reset was requested. These
594 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
595 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
596 * because its reset source is different than the other types listed.
597 */
598 enum ice_reset_req {
599 ICE_RESET_POR = 0,
600 ICE_RESET_INVAL = 0,
601 ICE_RESET_CORER = 1,
602 ICE_RESET_GLOBR = 2,
603 ICE_RESET_EMPR = 3,
604 ICE_RESET_PFR = 4,
605 };
606
607 /* Bus parameters */
608 struct ice_bus_info {
609 enum ice_pcie_bus_speed speed;
610 enum ice_pcie_link_width width;
611 enum ice_bus_type type;
612 u16 domain_num;
613 u16 device;
614 u8 func;
615 u8 bus_num;
616 };
617
618 /* Flow control (FC) parameters */
619 struct ice_fc_info {
620 enum ice_fc_mode current_mode; /* FC mode in effect */
621 enum ice_fc_mode req_mode; /* FC mode requested by caller */
622 };
623
624 /* Option ROM version information */
625 struct ice_orom_info {
626 u8 major; /* Major version of OROM */
627 u8 patch; /* Patch version of OROM */
628 u16 build; /* Build version of OROM */
629 u32 srev; /* Security revision */
630 };
631
632 /* NVM version information */
633 struct ice_nvm_info {
634 u32 eetrack;
635 u32 srev;
636 u8 major;
637 u8 minor;
638 };
639
640 /* Minimum Security Revision information */
641 struct ice_minsrev_info {
642 u32 nvm;
643 u32 orom;
644 u8 nvm_valid : 1;
645 u8 orom_valid : 1;
646 };
647
648 /* netlist version information */
649 struct ice_netlist_info {
650 u32 major; /* major high/low */
651 u32 minor; /* minor high/low */
652 u32 type; /* type high/low */
653 u32 rev; /* revision high/low */
654 u32 hash; /* SHA-1 hash word */
655 u16 cust_ver; /* customer version */
656 };
657
658 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
659 * of the flash image.
660 */
661 enum ice_flash_bank {
662 ICE_INVALID_FLASH_BANK,
663 ICE_1ST_FLASH_BANK,
664 ICE_2ND_FLASH_BANK,
665 };
666
667 /* Enumeration of which flash bank is desired to read from, either the active
668 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
669 * code which just wants to read the active or inactive flash bank.
670 */
671 enum ice_bank_select {
672 ICE_ACTIVE_FLASH_BANK,
673 ICE_INACTIVE_FLASH_BANK,
674 };
675
676 /* information for accessing NVM, OROM, and Netlist flash banks */
677 struct ice_bank_info {
678 u32 nvm_ptr; /* Pointer to 1st NVM bank */
679 u32 nvm_size; /* Size of NVM bank */
680 u32 orom_ptr; /* Pointer to 1st OROM bank */
681 u32 orom_size; /* Size of OROM bank */
682 u32 netlist_ptr; /* Pointer to 1st Netlist bank */
683 u32 netlist_size; /* Size of Netlist bank */
684 enum ice_flash_bank nvm_bank; /* Active NVM bank */
685 enum ice_flash_bank orom_bank; /* Active OROM bank */
686 enum ice_flash_bank netlist_bank; /* Active Netlist bank */
687 };
688
689 /* Flash Chip Information */
690 struct ice_flash_info {
691 struct ice_orom_info orom; /* Option ROM version info */
692 struct ice_nvm_info nvm; /* NVM version information */
693 struct ice_netlist_info netlist;/* Netlist version info */
694 struct ice_bank_info banks; /* Flash Bank information */
695 u16 sr_words; /* Shadow RAM size in words */
696 u32 flash_size; /* Size of available flash in bytes */
697 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
698 };
699
700 struct ice_link_default_override_tlv {
701 u8 options;
702 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
703 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
704 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
705 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
706 #define ICE_LINK_OVERRIDE_EN BIT(3)
707 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
708 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
709 u8 phy_config;
710 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
711 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
712 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
713 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
714 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
715 u8 fec_options;
716 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
717 u8 rsvd1;
718 u64 phy_type_low;
719 u64 phy_type_high;
720 };
721
722 #define ICE_NVM_VER_LEN 32
723
724 /* Max number of port to queue branches w.r.t topology */
725 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
726
727 #define ice_for_each_traffic_class(_i) \
728 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
729
730 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
731 * to driver defined policy for default aggregator
732 */
733 #define ICE_INVAL_TEID 0xFFFFFFFF
734 #define ICE_DFLT_AGG_ID 0
735
736 struct ice_sched_node {
737 struct ice_sched_node *parent;
738 struct ice_sched_node *sibling; /* next sibling in the same layer */
739 struct ice_sched_node **children;
740 struct ice_aqc_txsched_elem_data info;
741 u32 agg_id; /* aggregator group ID */
742 u16 vsi_handle;
743 u8 in_use; /* suspended or in use */
744 u8 tx_sched_layer; /* Logical Layer (1-9) */
745 u8 num_children;
746 u8 tc_num;
747 u8 owner;
748 #define ICE_SCHED_NODE_OWNER_LAN 0
749 #define ICE_SCHED_NODE_OWNER_AE 1
750 #define ICE_SCHED_NODE_OWNER_RDMA 2
751 };
752
753 /* Access Macros for Tx Sched Elements data */
754 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
755 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
756 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
757 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
758 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
759 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
760 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
761 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
762 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
763 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
764 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
765
766 struct ice_sched_rl_profile {
767 u32 rate; /* In Kbps */
768 struct ice_aqc_rl_profile_elem info;
769 };
770
771 /* The aggregator type determines if identifier is for a VSI group,
772 * aggregator group, aggregator of queues, or queue group.
773 */
774 enum ice_agg_type {
775 ICE_AGG_TYPE_UNKNOWN = 0,
776 ICE_AGG_TYPE_TC,
777 ICE_AGG_TYPE_AGG, /* aggregator */
778 ICE_AGG_TYPE_VSI,
779 ICE_AGG_TYPE_QG,
780 ICE_AGG_TYPE_Q
781 };
782
783 /* Rate limit types */
784 enum ice_rl_type {
785 ICE_UNKNOWN_BW = 0,
786 ICE_MIN_BW, /* for CIR profile */
787 ICE_MAX_BW, /* for EIR profile */
788 ICE_SHARED_BW /* for shared profile */
789 };
790
791 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
792 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
793 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
794 #define ICE_SCHED_NO_PRIORITY 0
795 #define ICE_SCHED_NO_BW_WT 0
796 #define ICE_SCHED_DFLT_RL_PROF_ID 0
797 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
798 #define ICE_SCHED_DFLT_BW_WT 4
799 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
800 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
801
802 /* Access Macros for Tx Sched RL Profile data */
803 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
804 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
805 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
806 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
807 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
808
809 #define ICE_MAX_PORT_PER_PCI_DEV 8
810
811 /* The following tree example shows the naming conventions followed under
812 * ice_port_info struct for default scheduler tree topology.
813 *
814 * A tree on a port
815 * * ---> root node
816 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
817 * * * * * * * * * |
818 * / |
819 * * |
820 * / |-> num_elements (range:1 - 9)
821 * * | implies num_of_layers
822 * / |
823 * (a)* |
824 *
825 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
826 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
827 * need TEID of (a) to add queues.
828 *
829 * This tree
830 * -> has 8 branches (one for each TC)
831 * -> First branch (TC0) has 4 elements
832 * -> has 4 layers
833 * -> (a) is the topmost layer node created by firmware on branch 0
834 *
835 * Note: Above asterisk tree covers only basic terminology and scenario.
836 * Refer to the documentation for more info.
837 */
838
839 /* Data structure for saving BW information */
840 enum ice_bw_type {
841 ICE_BW_TYPE_PRIO,
842 ICE_BW_TYPE_CIR,
843 ICE_BW_TYPE_CIR_WT,
844 ICE_BW_TYPE_EIR,
845 ICE_BW_TYPE_EIR_WT,
846 ICE_BW_TYPE_SHARED,
847 ICE_BW_TYPE_CNT /* This must be last */
848 };
849
850 struct ice_bw {
851 u32 bw;
852 u16 bw_alloc;
853 };
854
855 struct ice_bw_type_info {
856 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
857 u8 generic;
858 struct ice_bw cir_bw;
859 struct ice_bw eir_bw;
860 u32 shared_bw;
861 };
862
863 /* VSI queue context structure for given TC */
864 struct ice_q_ctx {
865 u16 q_handle;
866 u32 q_teid;
867 /* bw_t_info saves queue BW information */
868 struct ice_bw_type_info bw_t_info;
869 };
870
871 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
872 struct ice_sched_vsi_info {
873 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
874 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
875 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
876 u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS];
877 /* bw_t_info saves VSI BW information */
878 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
879 };
880
881 /* CEE or IEEE 802.1Qaz ETS Configuration data */
882 struct ice_dcb_ets_cfg {
883 u8 willing;
884 u8 cbs;
885 u8 maxtcs;
886 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
887 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
888 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
889 };
890
891 /* CEE or IEEE 802.1Qaz PFC Configuration data */
892 struct ice_dcb_pfc_cfg {
893 u8 willing;
894 u8 mbc;
895 u8 pfccap;
896 u8 pfcena;
897 };
898
899 /* CEE or IEEE 802.1Qaz Application Priority data */
900 struct ice_dcb_app_priority_table {
901 u16 prot_id;
902 u8 priority;
903 u8 selector;
904 };
905
906 #define ICE_MAX_USER_PRIORITY 8
907 #define ICE_DCBX_MAX_APPS 64
908 #define ICE_DSCP_NUM_VAL 64
909 #define ICE_LLDPDU_SIZE 1500
910 #define ICE_TLV_STATUS_OPER 0x1
911 #define ICE_TLV_STATUS_SYNC 0x2
912 #define ICE_TLV_STATUS_ERR 0x4
913 #define ICE_APP_PROT_ID_FCOE 0x8906
914 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
915 #define ICE_APP_PROT_ID_ISCSI_860 0x035c
916 #define ICE_APP_PROT_ID_FIP 0x8914
917 #define ICE_APP_SEL_ETHTYPE 0x1
918 #define ICE_APP_SEL_TCPIP 0x2
919 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
920 #define ICE_CEE_APP_SEL_TCPIP 0x1
921
922 struct ice_dcbx_cfg {
923 u32 numapps;
924 u32 tlv_status; /* CEE mode TLV status */
925 struct ice_dcb_ets_cfg etscfg;
926 struct ice_dcb_ets_cfg etsrec;
927 struct ice_dcb_pfc_cfg pfc;
928 #define ICE_QOS_MODE_VLAN 0x0
929 #define ICE_QOS_MODE_DSCP 0x1
930 u8 pfc_mode;
931 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
932 /* when DSCP mapping defined by user set its bit to 1 */
933 ice_declare_bitmap(dscp_mapped, ICE_DSCP_NUM_VAL);
934 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */
935 u8 dscp_map[ICE_DSCP_NUM_VAL];
936 u8 dcbx_mode;
937 #define ICE_DCBX_MODE_CEE 0x1
938 #define ICE_DCBX_MODE_IEEE 0x2
939 u8 app_mode;
940 #define ICE_DCBX_APPS_NON_WILLING 0x1
941 };
942
943 struct ice_qos_cfg {
944 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
945 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
946 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
947 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
948 u8 is_sw_lldp : 1;
949 };
950
951 struct ice_port_info {
952 struct ice_sched_node *root; /* Root Node per Port */
953 struct ice_hw *hw; /* back pointer to HW instance */
954 u32 last_node_teid; /* scheduler last node info */
955 u16 sw_id; /* Initial switch ID belongs to port */
956 u16 pf_vf_num;
957 u8 port_state;
958 u8 loopback_mode;
959 #define ICE_SCHED_PORT_STATE_INIT 0x0
960 #define ICE_SCHED_PORT_STATE_READY 0x1
961 u8 lport;
962 #define ICE_LPORT_MASK 0xff
963 struct ice_fc_info fc;
964 struct ice_mac_info mac;
965 struct ice_phy_info phy;
966 struct ice_lock sched_lock; /* protect access to TXSched tree */
967 struct ice_sched_node *
968 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
969 struct ice_bw_type_info root_node_bw_t_info;
970 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
971 struct ice_qos_cfg qos_cfg;
972 u8 is_vf:1;
973 u8 is_custom_tx_enabled:1;
974 };
975
976 struct ice_switch_info {
977 struct LIST_HEAD_TYPE vsi_list_map_head;
978 struct ice_sw_recipe *recp_list;
979 u16 prof_res_bm_init;
980 u16 max_used_prof_index;
981
982 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
983 };
984
985 /* Enum defining the different states of the mailbox snapshot in the
986 * PF-VF mailbox overflow detection algorithm. The snapshot can be in
987 * states:
988 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot
989 * within the mailbox buffer.
990 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot
991 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the
992 * mailbox and mark any VFs sending more messages than the threshold limit set.
993 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF.
994 */
995 enum ice_mbx_snapshot_state {
996 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0,
997 ICE_MAL_VF_DETECT_STATE_TRAVERSE,
998 ICE_MAL_VF_DETECT_STATE_DETECT,
999 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF,
1000 };
1001
1002 /* Structure to hold information of the static snapshot and the mailbox
1003 * buffer data used to generate and track the snapshot.
1004 * 1. state: the state of the mailbox snapshot in the malicious VF
1005 * detection state handler ice_mbx_vf_state_handler()
1006 * 2. head : head of the mailbox snapshot in a circular mailbox buffer
1007 * 3. tail : tail of the mailbox snapshot in a circular mailbox buffer
1008 * 4. num_iterations: number of messages traversed in circular mailbox buffer
1009 * 5. num_msg_proc: number of messages processed in mailbox
1010 * 6. num_pending_arq: number of pending asynchronous messages
1011 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently
1012 * serviced work item or interrupt.
1013 */
1014 struct ice_mbx_snap_buffer_data {
1015 enum ice_mbx_snapshot_state state;
1016 u32 head;
1017 u32 tail;
1018 u32 num_iterations;
1019 u16 num_msg_proc;
1020 u16 num_pending_arq;
1021 u16 max_num_msgs_mbx;
1022 };
1023
1024 /* Structure used to track a single VF's messages on the mailbox:
1025 * 1. list_entry: linked list entry node
1026 * 2. msg_count: the number of asynchronous messages sent by this VF
1027 * 3. malicious: whether this VF has been detected as malicious before
1028 */
1029 struct ice_mbx_vf_info {
1030 struct LIST_ENTRY_TYPE list_entry;
1031 u32 msg_count;
1032 u8 malicious : 1;
1033 };
1034
1035 /* Structure to hold data relevant to the captured static snapshot
1036 * of the PF-VF mailbox.
1037 */
1038 struct ice_mbx_snapshot {
1039 struct ice_mbx_snap_buffer_data mbx_buf;
1040 struct LIST_HEAD_TYPE mbx_vf;
1041 };
1042
1043 /* Structure to hold data to be used for capturing or updating a
1044 * static snapshot.
1045 * 1. num_msg_proc: number of messages processed in mailbox
1046 * 2. num_pending_arq: number of pending asynchronous messages
1047 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently
1048 * serviced work item or interrupt.
1049 * 4. async_watermark_val: An upper threshold set by caller to determine
1050 * if the pending arq count is large enough to assume that there is
1051 * the possibility of a mailicious VF.
1052 */
1053 struct ice_mbx_data {
1054 u16 num_msg_proc;
1055 u16 num_pending_arq;
1056 u16 max_num_msgs_mbx;
1057 u16 async_watermark_val;
1058 };
1059
1060 /* PHY model */
1061 enum ice_phy_model {
1062 ICE_PHY_UNSUP = -1,
1063 ICE_PHY_E810 = 1,
1064 ICE_PHY_E822,
1065 ICE_PHY_E830,
1066 };
1067
1068 /* Port hardware description */
1069 struct ice_hw {
1070 u8 *hw_addr;
1071 void *back;
1072 struct ice_aqc_layer_props *layer_info;
1073 struct ice_port_info *port_info;
1074 /* 2D Array for each Tx Sched RL Profile type */
1075 struct ice_sched_rl_profile **cir_profiles;
1076 struct ice_sched_rl_profile **eir_profiles;
1077 struct ice_sched_rl_profile **srl_profiles;
1078 /* PSM clock frequency for calculating RL profile params */
1079 u32 psm_clk_freq;
1080 u64 debug_mask; /* BITMAP for debug mask */
1081 enum ice_mac_type mac_type;
1082
1083 u16 fw_vsi_num;
1084 /* pci info */
1085 u16 device_id;
1086 u16 vendor_id;
1087 u16 subsystem_device_id;
1088 u16 subsystem_vendor_id;
1089 u8 revision_id;
1090
1091 u8 pf_id; /* device profile info */
1092 enum ice_phy_model phy_model;
1093 u8 phy_ports;
1094 u8 max_phy_port;
1095
1096 u16 max_burst_size; /* driver sets this value */
1097
1098 /* Tx Scheduler values */
1099 u8 num_tx_sched_layers;
1100 u8 num_tx_sched_phys_layers;
1101 u8 flattened_layers;
1102 u8 max_cgds;
1103 u8 sw_entry_point_layer;
1104 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1105 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
1106 /* List contain profile ID(s) and other params per layer */
1107 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1108 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
1109 u8 evb_veb; /* true for VEB, false for VEPA */
1110 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
1111 struct ice_bus_info bus;
1112 struct ice_flash_info flash;
1113 struct ice_hw_dev_caps dev_caps; /* device capabilities */
1114 struct ice_hw_func_caps func_caps; /* function capabilities */
1115
1116 struct ice_switch_info *switch_info; /* switch filter lists */
1117
1118 /* Control Queue info */
1119 struct ice_ctl_q_info adminq;
1120 struct ice_ctl_q_info sbq;
1121 struct ice_ctl_q_info mailboxq;
1122 u8 api_branch; /* API branch version */
1123 u8 api_maj_ver; /* API major version */
1124 u8 api_min_ver; /* API minor version */
1125 u8 api_patch; /* API patch version */
1126 u8 fw_branch; /* firmware branch version */
1127 u8 fw_maj_ver; /* firmware major version */
1128 u8 fw_min_ver; /* firmware minor version */
1129 u8 fw_patch; /* firmware patch version */
1130 u32 fw_build; /* firmware build number */
1131
1132 struct ice_fwlog_cfg fwlog_cfg;
1133 bool fwlog_support_ena; /* does hardware support FW logging? */
1134
1135 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
1136 * register. Used for determining the ITR/INTRL granularity during
1137 * initialization.
1138 */
1139 #define ICE_MAX_AGG_BW_200G 0x0
1140 #define ICE_MAX_AGG_BW_100G 0X1
1141 #define ICE_MAX_AGG_BW_50G 0x2
1142 #define ICE_MAX_AGG_BW_25G 0x3
1143 /* ITR granularity for different speeds */
1144 #define ICE_ITR_GRAN_ABOVE_25 2
1145 #define ICE_ITR_GRAN_MAX_25 4
1146 /* ITR granularity in 1 us */
1147 u8 itr_gran;
1148 /* INTRL granularity for different speeds */
1149 #define ICE_INTRL_GRAN_ABOVE_25 4
1150 #define ICE_INTRL_GRAN_MAX_25 8
1151 /* INTRL granularity in 1 us */
1152 u8 intrl_gran;
1153
1154 /* true if VSIs can share unicast MAC addr */
1155 u8 umac_shared;
1156
1157 #define ICE_PHY_PER_NAC_E822 1
1158 #define ICE_MAX_QUAD 2
1159 #define ICE_QUADS_PER_PHY_E822 2
1160 #define ICE_PORTS_PER_PHY_E822 8
1161 #define ICE_PORTS_PER_QUAD 4
1162 #define ICE_PORTS_PER_PHY_E810 4
1163 #define ICE_NUM_EXTERNAL_PORTS (ICE_MAX_QUAD * ICE_PORTS_PER_QUAD)
1164
1165 /* Active package version (currently active) */
1166 struct ice_pkg_ver active_pkg_ver;
1167 u32 pkg_seg_id;
1168 u32 pkg_sign_type;
1169 u32 active_track_id;
1170 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
1171 u8 active_pkg_in_nvm;
1172
1173 /* Driver's package ver - (from the Ice Metadata section) */
1174 struct ice_pkg_ver pkg_ver;
1175 u8 pkg_name[ICE_PKG_NAME_SIZE];
1176
1177 /* Driver's Ice segment format version and id (from the Ice seg) */
1178 struct ice_pkg_ver ice_seg_fmt_ver;
1179 u8 ice_seg_id[ICE_SEG_ID_SIZE];
1180
1181 /* Pointer to the ice segment */
1182 struct ice_seg *seg;
1183
1184 /* Pointer to allocated copy of pkg memory */
1185 u8 *pkg_copy;
1186 u32 pkg_size;
1187
1188 /* tunneling info */
1189 struct ice_lock tnl_lock;
1190 struct ice_tunnel_table tnl;
1191
1192 /* HW block tables */
1193 struct ice_blk_info blk[ICE_BLK_COUNT];
1194 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
1195 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
1196 struct ice_lock rss_locks; /* protect RSS configuration */
1197 struct LIST_HEAD_TYPE rss_list_head;
1198 u16 vsi_owning_pf_lut; /* SW IDX of VSI that acquired PF RSS LUT */
1199 struct ice_mbx_snapshot mbx_snapshot;
1200 u8 dvm_ena;
1201
1202 bool subscribable_recipes_supported;
1203 bool skip_clear_pf;
1204 };
1205
1206 /* Statistics collected by each port, VSI, VEB, and S-channel */
1207 struct ice_eth_stats {
1208 u64 rx_bytes; /* gorc */
1209 u64 rx_unicast; /* uprc */
1210 u64 rx_multicast; /* mprc */
1211 u64 rx_broadcast; /* bprc */
1212 u64 rx_discards; /* rdpc */
1213 u64 rx_unknown_protocol; /* rupp */
1214 u64 tx_bytes; /* gotc */
1215 u64 tx_unicast; /* uptc */
1216 u64 tx_multicast; /* mptc */
1217 u64 tx_broadcast; /* bptc */
1218 u64 tx_discards; /* tdpc */
1219 u64 tx_errors; /* tepc */
1220 u64 rx_no_desc; /* repc */
1221 u64 rx_errors; /* repc */
1222 };
1223
1224 #define ICE_MAX_UP 8
1225
1226 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
1227 struct ice_veb_up_stats {
1228 u64 up_rx_pkts[ICE_MAX_UP];
1229 u64 up_rx_bytes[ICE_MAX_UP];
1230 u64 up_tx_pkts[ICE_MAX_UP];
1231 u64 up_tx_bytes[ICE_MAX_UP];
1232 };
1233
1234 /* Statistics collected by the MAC */
1235 struct ice_hw_port_stats {
1236 /* eth stats collected by the port */
1237 struct ice_eth_stats eth;
1238 /* additional port specific stats */
1239 u64 tx_dropped_link_down; /* tdold */
1240 u64 crc_errors; /* crcerrs */
1241 u64 illegal_bytes; /* illerrc */
1242 u64 error_bytes; /* errbc */
1243 u64 mac_local_faults; /* mlfc */
1244 u64 mac_remote_faults; /* mrfc */
1245 u64 rx_len_errors; /* rlec */
1246 u64 link_xon_rx; /* lxonrxc */
1247 u64 link_xoff_rx; /* lxoffrxc */
1248 u64 link_xon_tx; /* lxontxc */
1249 u64 link_xoff_tx; /* lxofftxc */
1250 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1251 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1252 u64 priority_xon_tx[8]; /* pxontxc[8] */
1253 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1254 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1255 u64 rx_size_64; /* prc64 */
1256 u64 rx_size_127; /* prc127 */
1257 u64 rx_size_255; /* prc255 */
1258 u64 rx_size_511; /* prc511 */
1259 u64 rx_size_1023; /* prc1023 */
1260 u64 rx_size_1522; /* prc1522 */
1261 u64 rx_size_big; /* prc9522 */
1262 u64 rx_undersize; /* ruc */
1263 u64 rx_fragments; /* rfc */
1264 u64 rx_oversize; /* roc */
1265 u64 rx_jabber; /* rjc */
1266 u64 tx_size_64; /* ptc64 */
1267 u64 tx_size_127; /* ptc127 */
1268 u64 tx_size_255; /* ptc255 */
1269 u64 tx_size_511; /* ptc511 */
1270 u64 tx_size_1023; /* ptc1023 */
1271 u64 tx_size_1522; /* ptc1522 */
1272 u64 tx_size_big; /* ptc9522 */
1273 u64 mac_short_pkt_dropped; /* mspdc */
1274 /* EEE LPI */
1275 u32 tx_lpi_status;
1276 u32 rx_lpi_status;
1277 u64 tx_lpi_count; /* etlpic */
1278 u64 rx_lpi_count; /* erlpic */
1279 };
1280
1281 enum ice_sw_fwd_act_type {
1282 ICE_FWD_TO_VSI = 0,
1283 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1284 ICE_FWD_TO_Q,
1285 ICE_FWD_TO_QGRP,
1286 ICE_DROP_PACKET,
1287 ICE_LG_ACTION,
1288 ICE_INVAL_ACT
1289 };
1290
1291 struct ice_aq_get_set_rss_lut_params {
1292 u16 vsi_handle; /* software VSI handle */
1293 u16 lut_size; /* size of the LUT buffer */
1294 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
1295 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */
1296 u8 global_lut_id; /* only valid when lut_type is global */
1297 };
1298
1299 /* Checksum and Shadow RAM pointers */
1300 #define ICE_SR_NVM_CTRL_WORD 0x00
1301 #define ICE_SR_PHY_ANALOG_PTR 0x04
1302 #define ICE_SR_OPTION_ROM_PTR 0x05
1303 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1304 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1305 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1306 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
1307 #define ICE_SR_EMP_IMAGE_PTR 0x0B
1308 #define ICE_SR_PE_IMAGE_PTR 0x0C
1309 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
1310 #define ICE_SR_MNG_CFG_PTR 0x0E
1311 #define ICE_SR_EMP_MODULE_PTR 0x0F
1312 #define ICE_SR_PBA_BLOCK_PTR 0x16
1313 #define ICE_SR_BOOT_CFG_PTR 0x132
1314 #define ICE_SR_NVM_WOL_CFG 0x19
1315 #define ICE_NVM_OROM_VER_OFF 0x02
1316 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1317 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
1318 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
1319 #define ICE_SR_NVM_MAP_VER 0x29
1320 #define ICE_SR_NVM_IMAGE_VER 0x2A
1321 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
1322 #define ICE_SR_NVM_EETRACK_LO 0x2D
1323 #define ICE_SR_NVM_EETRACK_HI 0x2E
1324 #define ICE_NVM_VER_LO_SHIFT 0
1325 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1326 #define ICE_NVM_VER_HI_SHIFT 12
1327 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1328 #define ICE_OEM_EETRACK_ID 0xffffffff
1329 #define ICE_OROM_VER_PATCH_SHIFT 0
1330 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1331 #define ICE_OROM_VER_BUILD_SHIFT 8
1332 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1333 #define ICE_OROM_VER_SHIFT 24
1334 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
1335 #define ICE_SR_VPD_PTR 0x2F
1336 #define ICE_SR_PXE_SETUP_PTR 0x30
1337 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
1338 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1339 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1340 #define ICE_SR_VLAN_CFG_PTR 0x37
1341 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1342 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1343 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1344 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1345 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
1346 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1347 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
1348 #define ICE_SR_PFA_PTR 0x40
1349 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
1350 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1351 #define ICE_SR_NVM_BANK_SIZE 0x43
1352 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1353 #define ICE_SR_OROM_BANK_SIZE 0x45
1354 #define ICE_SR_NETLIST_BANK_PTR 0x46
1355 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1356 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
1357 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
1358 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
1359 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
1360 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
1361
1362 /* CSS Header words */
1363 #define ICE_NVM_CSS_HDR_LEN_L 0x02
1364 #define ICE_NVM_CSS_HDR_LEN_H 0x03
1365 #define ICE_NVM_CSS_SREV_L 0x14
1366 #define ICE_NVM_CSS_SREV_H 0x15
1367
1368 /* Length of Authentication header section in words */
1369 #define ICE_NVM_AUTH_HEADER_LEN 0x08
1370
1371 /* The Link Topology Netlist section is stored as a series of words. It is
1372 * stored in the NVM as a TLV, with the first two words containing the type
1373 * and length.
1374 */
1375 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B
1376 #define ICE_NETLIST_TYPE_OFFSET 0x0000
1377 #define ICE_NETLIST_LEN_OFFSET 0x0001
1378
1379 /* The Link Topology section follows the TLV header. When reading the netlist
1380 * using ice_read_netlist_module, we need to account for the 2-word TLV
1381 * header.
1382 */
1383 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2)
1384
1385 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1386 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1387
1388 #define ICE_LINK_TOPO_NODE_COUNT_M MAKEMASK(0x3FF, 0)
1389
1390 /* The Netlist ID Block is located after all of the Link Topology nodes. */
1391 #define ICE_NETLIST_ID_BLK_SIZE 0x30
1392 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1393
1394 /* netlist ID block field offsets (word offsets) */
1395 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02
1396 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03
1397 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04
1398 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05
1399 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06
1400 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07
1401 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08
1402 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09
1403 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n))
1404 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F
1405
1406 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1407 #define ICE_SR_VPD_SIZE_WORDS 512
1408 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
1409 #define ICE_SR_CTRL_WORD_1_S 0x06
1410 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1411 #define ICE_SR_CTRL_WORD_VALID 0x1
1412 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
1413 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
1414 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
1415
1416 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
1417
1418 /* Shadow RAM related */
1419 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1420 #define ICE_SR_BUF_ALIGNMENT 4096
1421 #define ICE_SR_WORDS_IN_1KB 512
1422 /* Checksum should be calculated such that after adding all the words,
1423 * including the checksum word itself, the sum should be 0xBABA.
1424 */
1425 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
1426
1427 /* Link override related */
1428 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1429 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1430 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1431 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1432 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1433 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1434 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1435 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1436
1437 #define ICE_PBA_FLAG_DFLT 0xFAFA
1438 /* Hash redirection LUT for VSI - maximum array size */
1439 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
1440
1441 /*
1442 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
1443 * This is needed to determine the BAR0 space for the VFs
1444 */
1445 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
1446 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
1447 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
1448
1449 /* AQ API version for LLDP_FILTER_CONTROL */
1450 #define ICE_FW_API_LLDP_FLTR_MAJ 1
1451 #define ICE_FW_API_LLDP_FLTR_MIN 7
1452 #define ICE_FW_API_LLDP_FLTR_PATCH 1
1453
1454 /* AQ API version for report default configuration */
1455 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
1456 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
1457 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
1458
1459 /* FW branch number for hardware families */
1460 #define ICE_FW_VER_BRANCH_E82X 0
1461 #define ICE_FW_VER_BRANCH_E810 1
1462
1463 /* FW version for FEC disable in Auto FEC mode */
1464 #define ICE_FW_FEC_DIS_AUTO_MAJ 7
1465 #define ICE_FW_FEC_DIS_AUTO_MIN 0
1466 #define ICE_FW_FEC_DIS_AUTO_PATCH 5
1467 #define ICE_FW_FEC_DIS_AUTO_MAJ_E82X 7
1468 #define ICE_FW_FEC_DIS_AUTO_MIN_E82X 1
1469 #define ICE_FW_FEC_DIS_AUTO_PATCH_E82X 2
1470
1471 /* AQ API version for FW health reports */
1472 #define ICE_FW_API_HEALTH_REPORT_MAJ 1
1473 #define ICE_FW_API_HEALTH_REPORT_MIN 7
1474 #define ICE_FW_API_HEALTH_REPORT_PATCH 6
1475
1476 /* AQ API version for FW auto drop reports */
1477 #define ICE_FW_API_AUTO_DROP_MAJ 1
1478 #define ICE_FW_API_AUTO_DROP_MIN 4
1479
1480 static inline bool
ice_is_nac_dual(struct ice_hw * hw)1481 ice_is_nac_dual(struct ice_hw *hw)
1482 {
1483 return !!(hw->dev_caps.nac_topo.mode & ICE_NAC_TOPO_DUAL_M);
1484 }
1485 #endif /* _ICE_TYPE_H_ */
1486