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Searched refs:op0 (Results 1 – 14 of 14) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrFormats.td57 let Inst{3-0} = op0;
73 let Inst{3-0} = op0;
88 let Inst{3-0} = op0;
99 let Inst{3-0} = op0;
112 let Inst{3-0} = op0;
123 let Inst{3-0} = op0;
140 let Inst{3-0} = op0;
157 let Inst{3-0} = op0;
170 let Inst{3-0} = op0;
183 let Inst{3-0} = op0;
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/freebsd/sys/contrib/openzfs/include/os/linux/kernel/linux/
H A Dsimd_aarch64.h63 #define sys_reg(op0, op1, crn, crm, op2) ( \ argument
64 ((op0) << Op0_shift) | \
/freebsd/sys/contrib/zstd/lib/decompress/
H A Dhuf_decompress_amd64.S49 #define op0 rsi macro
123 movq 32(%rax), %op0
326 movq %op0, 32(%rax)
377 movq 32(%rax), %op0
432 subq %op0, %rax /* rax = oend0 - op0 */
558 movq %op0, 32(%rax)
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Driscv_vector.td1394 Operands.push_back(Ops[Offset]); // op0
1443 Operands.push_back(Ops[Offset]); // op0
1502 Operands.push_back(Ops[Offset]); // op0
1579 Operands.push_back(Ops[Offset]); // op0
1644 Operands.push_back(Ops[Offset]); // op0
1703 Operands.push_back(Ops[Offset]); // op0
1747 // Unmasked: (passthru, op0, round_mode, vl)
1766 Operands.push_back(Ops[Offset]); // op0
1889 // Unmasked: (passthru, op0, frm, vl)
1907 Operands.push_back(Ops[Offset]); // op0
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H A Driscv_sifive_vector.td182 Operands.push_back(Ops[Offset]); // op0
H A Driscv_vector_common.td294 // IntrinsicTypes is output, op0, op1 [-1, 0, 1]
/freebsd/sys/dev/mthca/
H A Dmthca_qp.c1630 u8 op0 = 0; in mthca_tavor_post_send() local
1778 op0 = mthca_opcode[wr->opcode]; in mthca_tavor_post_send()
1793 qp->send_wqe_offset) | f0 | op0, in mthca_tavor_post_send()
1945 u8 op0 = 0; in mthca_arbel_post_send() local
1958 ((qp->sq.head & 0xffff) << 8) | f0 | op0; in mthca_arbel_post_send()
2119 op0 = mthca_opcode[wr->opcode]; in mthca_arbel_post_send()
2131 dbhi = (nreq << 24) | ((qp->sq.head & 0xffff) << 8) | f0 | op0; in mthca_arbel_post_send()
/freebsd/sys/arm64/include/
H A Darmreg.h55 #define __MRS_REG(op0, op1, crn, crm, op2) \ argument
56 (((op0) << MRS_Op0_SHIFT) | ((op1) << MRS_Op1_SHIFT) | \
62 #define __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ argument
63 S##op0##_##op1##_C##crn##_C##crm##_##op2
64 #define _MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ argument
65 __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DSMEInstrFormats.td1787 class sme2_mla_long_array_index_base<bits<2> op0, bits<2> op, Operand index_ty,
1797 let Inst{23-22} = op0;
1809 def _HtoS : sme2_mla_long_array_index_base<op0, op, uimm3s2range, ZPR16,
1825 class sme2_mla_long_array_vg2_index<string mnemonic, bits<2> op0, bits<2> op>
1826 : sme2_mla_long_array_index_base<op0, op, uimm2s2range, ZZ_h_mul_r,
1861 class sme2_mla_long_array_vg4_index<string mnemonic, bits<2> op0, bits<2> op>
1862 : sme2_mla_long_array_index_base<op0, op, uimm2s2range, ZZZZ_h_mul_r,
1897 class sme2_mla_long_array<bits<2>op0, bits<2> op,
1910 let Inst{23-22} = op0;
2023 class sme2_mla_long_array_vg2_multi<string mnemonic, bits<2> op0, bits<3> op,
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H A DAArch64SystemOperands.td658 class SysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
666 let Encoding{15-14} = op0;
676 class RWSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
678 : SysReg<name, op0, op1, crn, crm, op2> {
683 class ROSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
685 : SysReg<name, op0, op1, crn, crm, op2> {
690 class WOSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
692 : SysReg<name, op0, op1, crn, crm, op2> {
H A DAArch64InstrFormats.td11647 let Inst{14} = op0;
11663 let Inst{14} = op0;
11667 class CryptoRRR_2D<bits<1> op0, bits<2>op1, string asm>
11673 class CryptoRRR_4S<bits<1> op0, bits<2>op1, string asm>
11679 class CryptoRRRTied<bits<1> op0, bits<2>op1, string asm>
11683 class CryptoRRRR<bits<2>op0, string asm, string asmops>
11689 let Inst{22-21} = op0;
11694 class CryptoRRRR_16B<bits<2>op0, string asm>
11698 class CryptoRRRR_4S<bits<2>op0, string asm>
11726 let Inst{14} = op0;
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H A DAArch64InstrInfo.td9501 // MRRS <Xt>, <Xt+1>, <sysreg|S<op0>_<op1>_<Cn>_<Cm>_<op2>>
9502 // MSRR <sysreg|S<op0>_<op1>_<Cn>_<Cm>_<op2>>, <Xt>, <Xt+1>
/freebsd/sys/fs/nfsserver/
H A Dnfs_nfsdsocket.c712 int i, lktype, op, op0 = 0, rstat, statsinprog = 0; in nfsrvd_compound() local
900 op0 = op; in nfsrvd_compound()
931 else if (i != 0 && op0 != NFSV4OP_SEQUENCE) in nfsrvd_compound()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h61 #define X86_INTRINSIC_DATA(id, type, op0, op1) \ argument
62 { Intrinsic::x86_##id, type, op0, op1 }