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/freebsd/sys/netgraph/
H A Dng_patch.c496 val.v8 = be64toh(val.v8); in do_patch()
501 val.v8 = privp->conf->ops[i].val.v8; in do_patch()
504 val.v8 += privp->conf->ops[i].val.v8; in do_patch()
507 val.v8 -= privp->conf->ops[i].val.v8; in do_patch()
510 val.v8 *= privp->conf->ops[i].val.v8; in do_patch()
513 val.v8 /= privp->conf->ops[i].val.v8; in do_patch()
519 val.v8 &= privp->conf->ops[i].val.v8; in do_patch()
522 val.v8 |= privp->conf->ops[i].val.v8; in do_patch()
525 val.v8 ^= privp->conf->ops[i].val.v8; in do_patch()
528 val.v8 <<= privp->conf->ops[i].val.v8; in do_patch()
[all …]
/freebsd/sys/crypto/openssl/aarch64/
H A Dvpaes-armv8.S235 eor v8.16b, v8.16b, v10.16b
252 eor v8.16b, v8.16b, v12.16b
261 tbl v8.16b, {v8.16b}, v4.16b
267 eor v8.16b, v8.16b, v11.16b
270 eor v8.16b, v8.16b, v12.16b
278 ushr v8.16b, v8.16b, #4
314 eor v8.16b, v8.16b, v12.16b
501 tbl v8.16b, {v8.16b},v5.16b
508 eor v8.16b, v8.16b, v9.16b
514 tbl v8.16b, {v8.16b},v5.16b
[all …]
H A Daes-gcm-armv8_64.S413 movi v8.8b, #0xc2
640 movi v8.8b, #0xc2
945 movi v8.8b, #0xc2
1386 movi v8.8b, #0xc2
1475 pmull v8.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
1609 movi v8.8b, #0xc2
1702 pmull v8.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
1935 movi v8.8b, #0xc2
1959 pmull v8.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
3567 pmull v8.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
[all …]
H A Darmv8-mont.S247 eor v8.16b,v8.16b,v8.16b
341 ins v8.d[0],v16.d[0]
366 ext v8.16b,v8.16b,v8.16b,#8
367 add v8.2d,v8.2d,v15.2d
369 ushr v8.2d,v8.2d,#16
615 ld1 {v8.2d},[x6]
795 add v8.2d,v8.2d,v15.2d
798 mov v5.16b,v8.16b
799 ext v8.16b,v8.16b,v8.16b,#8
800 add v8.2d,v8.2d,v15.2d
[all …]
H A Dpoly1305-armv8.S445 ld1 {v8.4s},[x15]
523 umlal v19.2d,v15.2s,v8.s[2]
532 umlal v20.2d,v16.2s,v8.s[2]
691 umull2 v20.2d,v16.4s,v8.4s
701 umlal2 v19.2d,v15.4s,v8.4s
712 umlal2 v21.2d,v17.4s,v8.4s
714 umlal2 v22.2d,v18.4s,v8.4s
729 umlal v20.2d,v11.2s,v8.2s
741 umlal v19.2d,v10.2s,v8.2s
751 umlal v21.2d,v12.2s,v8.2s
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dnvidia,tegra20-sdhci.txt52 configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
65 - nvidia,pad-autocal-pull-up-offset-1v8,
66 nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength
72 - nvidia,pad-autocal-pull-up-offset-1v8-timeout,
73 nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive
116 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
121 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
122 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
135 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
140 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
[all …]
H A Dnvidia,tegra20-sdhci.yaml112 nvidia,pad-autocal-pull-down-offset-1v8:
117 nvidia,pad-autocal-pull-down-offset-1v8-timeout:
140 nvidia,pad-autocal-pull-up-offset-1v8:
145 nvidia,pad-autocal-pull-up-offset-1v8-timeout:
230 - const: sdmmc-1v8
234 - const: sdmmc-1v8-drv
239 - const: sdmmc-1v8-drv
242 - const: sdmmc-1v8-drv
259 - const: sdmmc-1v8
296 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Dfoundation-v8-gicv3-psci.dts7 #include "foundation-v8.dtsi"
8 #include "foundation-v8-gicv3.dtsi"
9 #include "foundation-v8-psci.dtsi"
H A Dfoundation-v8-psci.dts7 #include "foundation-v8.dtsi"
8 #include "foundation-v8-gicv2.dtsi"
9 #include "foundation-v8-psci.dtsi"
H A Dfoundation-v8-gicv3.dts8 #include "foundation-v8.dtsi"
9 #include "foundation-v8-gicv3.dtsi"
10 #include "foundation-v8-spin-table.dtsi"
H A Dfoundation-v8.dts8 #include "foundation-v8.dtsi"
9 #include "foundation-v8-gicv2.dtsi"
10 #include "foundation-v8-spin-table.dtsi"
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dfixed-regulator.yaml118 reg_1v8: regulator-1v8 {
120 regulator-name = "1v8";
130 reg_1v8_clk: regulator-1v8-clk {
132 regulator-name = "1v8";
141 reg_1v8_domain: regulator-1v8-domain {
143 regulator-name = "1v8";
/freebsd/sys/arm/arm/
H A Dstdatomic.c113 uint8_t v8[4]; member
141 r->v8[offset] = val; in put_1()
150 return (r->v8[offset]); in get_1()
164 r->v8[offset] = bytes.out[0]; in put_2()
165 r->v8[offset + 1] = bytes.out[1]; in put_2()
178 bytes.in[0] = r->v8[offset]; in get_2()
179 bytes.in[1] = r->v8[offset + 1]; in get_2()
/freebsd/contrib/file/magic/Magdir/
H A Djavascript74 # v8 JavaScript engine bytecode
76 # URL: https://v8.dev/docs/ignition
79 # Version information is provided for some v8 versions found in NodeJS releases.
86 >>>>0 ulelong^0xC0DE0000 x v8 bytecode, external reference table size: %u bytes,
98 >>>>0 ulelong^0xC0DE0000 x v8 bytecode, external reference table size: %u bytes,
119 >>>>0 ulelong^0xC0DE0000 x v8 bytecode, external reference table size: %u bytes,
137 >>>>0 ulelong^0xC0DE0000 x v8 bytecode, external reference table size: %u bytes,
151 >>>0 ulelong^0xC0DE0000 x v8 bytecode, external reference table size: %u bytes,
/freebsd/sys/dev/altera/avgen/
H A Daltera_avgen.c87 uint64_t v8; in altera_avgen_read() local
128 v8 = bus_read_8(sc->avg_res, offset); in altera_avgen_read()
129 error = uiomove(&v8, sizeof(v8), uio); in altera_avgen_read()
149 uint64_t v8; in altera_avgen_write() local
193 error = uiomove(&v8, sizeof(v8), uio); in altera_avgen_write()
196 bus_write_8(sc->avg_res, offset, v8); in altera_avgen_write()
/freebsd/sys/contrib/libsodium/src/libsodium/crypto_pwhash/argon2/
H A Dblamka-round-ref.h27 #define BLAKE2_ROUND_NOMSG(v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, \ argument
30 G(v0, v4, v8, v12); \
36 G(v2, v7, v8, v13); \
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi6220-coresight.dtsi380 compatible = "arm,coresight-cti-v8-arch",
393 compatible = "arm,coresight-cti-v8-arch",
406 compatible = "arm,coresight-cti-v8-arch",
419 compatible = "arm,coresight-cti-v8-arch",
432 compatible = "arm,coresight-cti-v8-arch",
445 compatible = "arm,coresight-cti-v8-arch",
458 compatible = "arm,coresight-cti-v8-arch",
471 compatible = "arm,coresight-cti-v8-arch",
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64.td122 "Enable v8.2 UAO PState (FEAT_UAO)">;
358 "Enable v8.4-A Trace extension (FEAT_TRF)">;
661 "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
667 "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
672 "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions",
676 "v8.8a", "HasV8_8aOps", "true", "Support ARM v8.8a instructions",
680 "v8.9a", "HasV8_9aOps", "true", "Support ARM v8.9a instructions",
710 [//v8.1
712 //v8.2
714 //v8.3
[all …]
H A DAArch64SystemOperands.td76 // v8.9a/v9.4a FEAT_ATS1A
442 // v8.5a Spectre Mitigation
445 // v8.5a Memory Tagging Extension
448 // v8.8a Non-Maskable Interrupts
834 // v8.2a "RAS extension" registers
1442 // v8.2a registers
1517 // v8.4a RAS registers
1525 // v8.4a MPAM registers
1768 // v8.4a MPAM and SME registers
1774 // v8.8a Non-Maskable Interrupts
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcoresight-cti.yaml32 are implementation defined, except when the CTI is connected to an ARM v8
35 In this case the ARM v8 architecture defines the required signal connections
36 between CTI and the CPU core and ETM if present. In the case of a v8
38 indicate this feature (arm,coresight-cti-v8-arch).
88 - const: arm,coresight-cti-v8-arch
99 base cti node if compatible string arm,coresight-cti-v8-arch is used,
115 compatible string arm,coresight-cti-v8-arch used. If the associated
217 const: arm,coresight-cti-v8-arch
235 # v8 architecturally defined CTI - CPU + ETM connections generated by the
236 # driver according to the v8 architecture specification.
[all …]
H A Darm,coresight-cti.yaml31 are implementation defined, except when the CTI is connected to an ARM v8
34 In this case the ARM v8 architecture defines the required signal connections
35 between CTI and the CPU core and ETM if present. In the case of a v8
37 indicate this feature (arm,coresight-cti-v8-arch).
87 - const: arm,coresight-cti-v8-arch
114 arm,coresight-cti-v8-arch used. If the associated device has not been
233 const: arm,coresight-cti-v8-arch
251 # v8 architecturally defined CTI - CPU + ETM connections generated by the
252 # driver according to the v8 architecture specification.
255 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
/freebsd/crypto/openssh/regress/unittests/sshbuf/
H A Dtest_sshbuf_getput_basic.c35 u_char v8; in sshbuf_getput_basic_tests() local
183 ASSERT_INT_EQ(sshbuf_get_u8(p1, &v8), 0); in sshbuf_getput_basic_tests()
184 ASSERT_U8_EQ(v8, 0x11); in sshbuf_getput_basic_tests()
186 ASSERT_INT_EQ(sshbuf_get_u8(p1, &v8), 0); in sshbuf_getput_basic_tests()
187 ASSERT_U8_EQ(v8, 0x22); in sshbuf_getput_basic_tests()
193 r = sshbuf_get_u8(p1, &v8); in sshbuf_getput_basic_tests()
536 ASSERT_INT_EQ(sshbuf_peek_u8(p1, 0, &v8), 0); in sshbuf_getput_basic_tests()
537 ASSERT_U8_EQ(v8, 0x11); in sshbuf_getput_basic_tests()
538 ASSERT_INT_EQ(sshbuf_peek_u8(p1, 9, &v8), 0); in sshbuf_getput_basic_tests()
539 ASSERT_U8_EQ(v8, 0x99); in sshbuf_getput_basic_tests()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra234-p3701-0008.dtsi105 vdd_1v8_ao: regulator-vdd-1v8-ao {
113 vdd_1v8_hs: regulator-vdd-1v8-hs {
121 vdd_1v8_ls: regulator-vdd-1v8-ls {
H A Dtegra234-p3701-0000.dtsi93 vdd_1v8_ls: regulator-vdd-1v8-ls {
101 vdd_1v8_hs: regulator-vdd-1v8-hs {
109 vdd_1v8_ao: regulator-vdd-1v8-ao {
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsAArch64.def82 TARGET_BUILTIN(__builtin_arm_jcvt, "Zid", "nc", "v8.3a")
117 TARGET_BUILTIN(__builtin_arm_rint32zf, "ff", "", "v8.5a")
118 TARGET_BUILTIN(__builtin_arm_rint32z, "dd", "", "v8.5a")
119 TARGET_BUILTIN(__builtin_arm_rint64zf, "ff", "", "v8.5a")
120 TARGET_BUILTIN(__builtin_arm_rint64z, "dd", "", "v8.5a")
121 TARGET_BUILTIN(__builtin_arm_rint32xf, "ff", "", "v8.5a")
122 TARGET_BUILTIN(__builtin_arm_rint32x, "dd", "", "v8.5a")
123 TARGET_BUILTIN(__builtin_arm_rint64xf, "ff", "", "v8.5a")
124 TARGET_BUILTIN(__builtin_arm_rint64x, "dd", "", "v8.5a")

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