1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at 9 * http://www.opensource.org/licenses/cddl1.txt. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2004-2011 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 * Copyright 2020 RackTop Systems, Inc. 26 */ 27 28 #ifndef _EMLXS_HW_H 29 #define _EMLXS_HW_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define MAX_VPORTS 256 /* Max virtual ports per HBA */ 36 /* (includes physical port) */ 37 #define MAX_VPORTS_LIMITED 101 38 39 #define FC_MAX_TRANSFER 0x40000 /* Max transfer size per */ 40 /* operation */ 41 42 #define MAX_RINGS_AVAILABLE 4 /* # rings available */ 43 #define MAX_RINGS 4 /* Max # rings used */ 44 45 #define PCB_SIZE 128 46 47 #define SLIM_IOCB_CMD_R0_ENTRIES 128 /* SLI FCP cmd ring entries */ 48 #define SLIM_IOCB_RSP_R0_ENTRIES 128 /* SLI FCP rsp ring entries */ 49 #define SLIM_IOCB_CMD_R1_ENTRIES 128 /* SLI IP cmd ring entries */ 50 #define SLIM_IOCB_RSP_R1_ENTRIES 128 /* SLI IP rsp ring entries */ 51 #define SLIM_IOCB_CMD_R2_ENTRIES 128 /* SLI ELS cmd ring entries */ 52 #define SLIM_IOCB_RSP_R2_ENTRIES 128 /* SLI ELS rspe ring entries */ 53 #define SLIM_IOCB_CMD_R3_ENTRIES 128 /* SLI CT cmd ring entries */ 54 #define SLIM_IOCB_RSP_R3_ENTRIES 128 /* SLI CT rsp ring entries */ 55 56 /* 57 * Total: 184 Cmd's + 184 Rsp's = 368 58 * Command and response entry counts are not required to be equal 59 */ 60 61 #define SLIM_IOCB_CMD_ENTRIES (SLIM_IOCB_CMD_R0_ENTRIES + \ 62 SLIM_IOCB_CMD_R1_ENTRIES + \ 63 SLIM_IOCB_CMD_R2_ENTRIES + \ 64 SLIM_IOCB_CMD_R3_ENTRIES) 65 66 #define SLIM_IOCB_RSP_ENTRIES (SLIM_IOCB_RSP_R0_ENTRIES + \ 67 SLIM_IOCB_RSP_R1_ENTRIES + \ 68 SLIM_IOCB_RSP_R2_ENTRIES + \ 69 SLIM_IOCB_RSP_R3_ENTRIES) 70 71 #define SLIM_IOCB_ENTRIES (SLIM_IOCB_CMD_ENTRIES + \ 72 SLIM_IOCB_RSP_ENTRIES) 73 74 75 /* SLI1 Definitions */ 76 #define SLI_SLIM1_SIZE 4096 /* Fixed size memory */ 77 78 79 /* SLI2 Definitions */ 80 #define SLI2_IOCB_CMD_SIZE 32 81 #define SLI2_IOCB_RSP_SIZE 32 82 #define SLI2_IOCB_MAX_SIZE ((SLI2_IOCB_CMD_SIZE * \ 83 SLIM_IOCB_CMD_ENTRIES) + \ 84 (SLI2_IOCB_RSP_SIZE * \ 85 SLIM_IOCB_RSP_ENTRIES)) 86 #define SLI2_SLIM2_SIZE (MBOX_SIZE + MBOX_EXTENSION_SIZE + \ 87 PCB_SIZE + SLI2_IOCB_MAX_SIZE) 88 89 90 /* SLI3 Definitions */ 91 #define SLI3_MAX_BDE 7 92 #define SLI3_IOCB_CMD_SIZE 128 93 #define SLI3_IOCB_RSP_SIZE 64 94 #define SLI3_IOCB_MAX_SIZE ((SLI3_IOCB_CMD_SIZE * \ 95 SLIM_IOCB_CMD_ENTRIES) + \ 96 (SLI3_IOCB_RSP_SIZE * \ 97 SLIM_IOCB_RSP_ENTRIES)) 98 #define SLI3_SLIM2_SIZE (MBOX_SIZE + MBOX_EXTENSION_SIZE + \ 99 PCB_SIZE + SLI3_IOCB_MAX_SIZE) 100 101 #define SLI_SLIM2_SIZE SLI3_SLIM2_SIZE 102 #define SLI_IOCB_MAX_SIZE SLI3_IOCB_MAX_SIZE 103 104 105 /* These two are defined to indicate FCP cmd or non FCP cmd */ 106 #define FC_FCP_CMD 0 107 #define FC_FCT_CMD 0 108 #define FC_IP_CMD 1 109 #define FC_ELS_CMD 2 110 #define FC_CT_CMD 3 111 112 #define FC_NFCP_CMD 1 /* could be a bit mask */ 113 114 #define FC_MAXRETRY 3 /* max retries for ELS commands */ 115 #define FC_FCP_RING 0 /* use ring 0 for FCP initiator cmds */ 116 #define FC_FCT_RING 0 /* use ring 0 for FCP target cmds */ 117 118 #define FC_IP_RING 1 /* use ring 1 for IP commands */ 119 #define FC_ELS_RING 2 /* use ring 2 for ELS commands */ 120 #define FC_CT_RING 3 /* use ring 3 for CT commands */ 121 122 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 123 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 124 #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */ 125 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 126 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG */ 127 /* iocb */ 128 #define FF_REG_AREA_SIZE 256 /* size, in bytes, of i/o register */ 129 /* area */ 130 131 /* 132 * Miscellaneous stuff.... 133 */ 134 135 #define MAX_NODE_THROTTLE 2048 136 137 /* HBA Mgmt */ 138 #define FDMI_DID ((uint32_t)0xfffffa) 139 #define NAMESERVER_DID ((uint32_t)0xfffffc) 140 #define SCR_DID ((uint32_t)0xfffffd) 141 #define FABRIC_DID ((uint32_t)0xfffffe) 142 #define BCAST_DID ((uint32_t)0xffffff) 143 #define MASK_DID ((uint32_t)0xffffff) 144 #define CT_DID_MASK ((uint32_t)0xffff00) 145 #define FABRIC_DID_MASK ((uint32_t)0xfff000) 146 #define WELL_KNOWN_DID_MASK ((uint32_t)0xfffff0) 147 148 #define EMLXS_MENLO_DID ((uint32_t)0x00fc0e) 149 150 #define OWN_CHIP 1 /* IOCB / Mailbox is owned by FireFly */ 151 #define OWN_HOST 0 /* IOCB / Mailbox is owned by Host */ 152 #define END_OF_CHAIN 0 153 154 155 /* defines for type field in fc header */ 156 #define EMLXS_MENLO_TYPE 0xFE 157 158 /* defines for rctl field in fc header */ 159 #define FC_DEV_DATA 0x0 160 #define FC_UNSOL_CTL 0x2 161 #define FC_SOL_CTL 0x3 162 #define FC_UNSOL_DATA 0x4 163 #define FC_FCP_CMND 0x6 164 #define FC_ELS_REQ 0x22 165 #define FC_ELS_RSP 0x23 166 #define FC_NET_HDR 0x20 /* network headers for Dfctl field */ 167 168 /* 169 * Common Transport structures and definitions 170 * 171 */ 172 #define EMLXS_COMMAND 0 173 #define EMLXS_RESPONSE 1 174 175 typedef union CtRevisionId 176 { 177 /* Structure is in Big Endian format */ 178 struct 179 { 180 uint32_t Revision:8; 181 uint32_t InId:24; 182 } bits; 183 uint32_t word; 184 } CtRevisionId_t; 185 186 typedef union CtCommandResponse 187 { 188 /* Structure is in Big Endian format */ 189 struct 190 { 191 uint32_t CmdRsp:16; 192 uint32_t Size:16; 193 } bits; 194 uint32_t word; 195 } CtCommandResponse_t; 196 197 typedef struct SliCtRequest 198 { 199 /* Structure is in Big Endian format */ 200 CtRevisionId_t RevisionId; 201 uint8_t FsType; 202 uint8_t FsSubType; 203 uint8_t Options; 204 uint8_t Rsrvd1; 205 CtCommandResponse_t CommandResponse; 206 uint8_t Rsrvd2; 207 uint8_t ReasonCode; 208 uint8_t Explanation; 209 uint8_t VendorUnique; 210 211 union 212 { 213 uint32_t data; 214 uint32_t PortID; 215 216 struct gid 217 { 218 uint8_t PortType; /* for GID_PT requests */ 219 uint8_t DomainScope; 220 uint8_t AreaScope; 221 uint8_t Fc4Type; /* for GID_FT requests */ 222 } gid; 223 struct rft 224 { 225 uint32_t PortId; /* For RFT_ID requests */ 226 #ifdef EMLXS_BIG_ENDIAN 227 uint32_t rsvd0:16; 228 uint32_t rsvd1:7; 229 uint32_t fcpReg:1; /* Type 8 */ 230 uint32_t rsvd2:2; 231 uint32_t ipReg:1; /* Type 5 */ 232 uint32_t rsvd3:5; 233 #endif 234 #ifdef EMLXS_LITTLE_ENDIAN 235 uint32_t rsvd0:16; 236 uint32_t fcpReg:1; /* Type 8 */ 237 uint32_t rsvd1:7; 238 uint32_t rsvd3:5; 239 uint32_t ipReg:1; /* Type 5 */ 240 uint32_t rsvd2:2; 241 #endif 242 uint32_t rsvd[7]; 243 } rft; 244 245 struct rsnn 246 { 247 uint8_t wwnn[8]; 248 uint8_t snn_len; 249 char snn[256]; 250 } rsnn; 251 252 struct rspn 253 { 254 uint32_t PortId; 255 uint8_t spn_len; 256 char spn[256]; 257 } rspn; 258 } un; 259 } SliCtRequest_t; 260 typedef SliCtRequest_t SLI_CT_REQUEST; 261 262 #define SLI_CT_REVISION 1 263 264 265 /* 266 * FsType Definitions 267 */ 268 269 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 270 #define SLI_CT_TIME_SERVICE 0xFB 271 #define SLI_CT_DIRECTORY_SERVICE 0xFC 272 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 273 274 /* 275 * Directory Service Subtypes 276 */ 277 278 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 279 280 /* 281 * Response Codes 282 */ 283 284 #define SLI_CT_RESPONSE_FS_RJT 0x8001 285 #define SLI_CT_RESPONSE_FS_ACC 0x8002 286 287 /* 288 * Reason Codes 289 */ 290 291 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 292 #define SLI_CT_INVALID_COMMAND 0x01 293 #define SLI_CT_INVALID_VERSION 0x02 294 #define SLI_CT_LOGICAL_ERROR 0x03 295 #define SLI_CT_INVALID_IU_SIZE 0x04 296 #define SLI_CT_LOGICAL_BUSY 0x05 297 #define SLI_CT_PROTOCOL_ERROR 0x07 298 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 299 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 300 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 301 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 302 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 303 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 304 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 305 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 306 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 307 #define SLI_CT_VENDOR_UNIQUE 0xff 308 309 /* 310 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 311 */ 312 313 #define SLI_CT_NO_PORT_ID 0x01 314 #define SLI_CT_NO_PORT_NAME 0x02 315 #define SLI_CT_NO_NODE_NAME 0x03 316 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 317 #define SLI_CT_NO_IP_ADDRESS 0x05 318 #define SLI_CT_NO_IPA 0x06 319 #define SLI_CT_NO_FC4_TYPES 0x07 320 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 321 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 322 #define SLI_CT_NO_PORT_TYPE 0x0A 323 #define SLI_CT_ACCESS_DENIED 0x10 324 #define SLI_CT_INVALID_PORT_ID 0x11 325 #define SLI_CT_DATABASE_EMPTY 0x12 326 327 #ifdef EMLXS_BIG_ENDIAN 328 #define CT_CMD_MASK 0xffff0000 329 #endif 330 331 #ifdef EMLXS_LITTLE_ENDIAN 332 #define CT_CMD_MASK 0xffff 333 #endif 334 335 /* 336 * Management Server Interface Command Codes 337 */ 338 339 #define MS_GTIN 0x0100 340 #define MS_GIEL 0x0101 341 #define MS_GIET 0x0111 342 #define MS_GDID 0x0112 343 #define MS_GMID 0x0113 344 #define MS_GFN 0x0114 345 #define MS_GIELN 0x0115 346 #define MS_GMAL 0x0116 347 #define MS_GIEIL 0x0117 348 #define MS_GPL 0x0118 349 #define MS_GPT 0x0121 350 #define MS_GPPN 0x0122 351 #define MS_GAPNL 0x0124 352 #define MS_GPS 0x0126 353 #define MS_GPSC 0x0127 354 #define MS_GATIN 0x0128 355 #define MS_GSES 0x0130 356 #define MS_GPLNL 0x0191 357 #define MS_GPLT 0x0192 358 #define MS_GPLML 0x0193 359 #define MS_GPAB 0x0197 360 #define MS_GNPL 0x01A1 361 #define MS_GPNL 0x01A2 362 #define MS_GPFCP 0x01A4 363 #define MS_GPLI 0x01A5 364 #define MS_GNID 0x01B1 365 #define MS_RIELN 0x0215 366 #define MS_RPL 0x0280 367 #define MS_RPLN 0x0291 368 #define MS_RPLT 0x0292 369 #define MS_RPLM 0x0293 370 #define MS_RPAB 0x0298 371 #define MS_RPFCP 0x029A 372 #define MS_RPLI 0x029B 373 #define MS_DPL 0x0380 374 #define MS_DPLN 0x0391 375 #define MS_DPLM 0x0392 376 #define MS_DPLML 0x0393 377 #define MS_DPLI 0x0394 378 #define MS_DPAB 0x0395 379 #define MS_DPALL 0x039F 380 381 /* 382 * Name Server Command Codes 383 */ 384 #define SLI_CTNS_GA_NXT 0x0100 385 #define SLI_CTNS_GPN_ID 0x0112 386 #define SLI_CTNS_GNN_ID 0x0113 387 #define SLI_CTNS_GCS_ID 0x0114 388 #define SLI_CTNS_GFT_ID 0x0117 389 #define SLI_CTNS_GSPN_ID 0x0118 390 #define SLI_CTNS_GPT_ID 0x011A 391 #define SLI_CTNS_GID_PN 0x0121 392 #define SLI_CTNS_GID_NN 0x0131 393 #define SLI_CTNS_GIP_NN 0x0135 394 #define SLI_CTNS_GIPA_NN 0x0136 395 #define SLI_CTNS_GSNN_NN 0x0139 396 #define SLI_CTNS_GNN_IP 0x0153 397 #define SLI_CTNS_GIPA_IP 0x0156 398 #define SLI_CTNS_GID_FT 0x0171 399 #define SLI_CTNS_GID_PT 0x01A1 400 #define SLI_CTNS_RPN_ID 0x0212 401 #define SLI_CTNS_RNN_ID 0x0213 402 #define SLI_CTNS_RCS_ID 0x0214 403 #define SLI_CTNS_RFT_ID 0x0217 404 #define SLI_CTNS_RSPN_ID 0x0218 405 #define SLI_CTNS_RPT_ID 0x021A 406 #define SLI_CTNS_RIP_NN 0x0235 407 #define SLI_CTNS_RIPA_NN 0x0236 408 #define SLI_CTNS_RSNN_NN 0x0239 409 #define SLI_CTNS_DA_ID 0x0300 410 411 #define SLI_CT_LOOPBACK 0xFCFC 412 413 414 /* 415 * Port Types 416 */ 417 418 #define SLI_CTPT_N_PORT 0x01 419 #define SLI_CTPT_NL_PORT 0x02 420 #define SLI_CTPT_FNL_PORT 0x03 421 #define SLI_CTPT_IP 0x04 422 #define SLI_CTPT_FCP 0x08 423 #define SLI_CTPT_NX_PORT 0x7F 424 #define SLI_CTPT_F_PORT 0x81 425 #define SLI_CTPT_FL_PORT 0x82 426 #define SLI_CTPT_E_PORT 0x84 427 428 #define SLI_CT_LAST_ENTRY 0x80000000 429 430 /* ===================================================================== */ 431 432 /* 433 * Start FireFly Register definitions 434 */ 435 436 /* PCI register offsets */ 437 #define MEM_ADDR_OFFSET 0x10 /* SLIM base memory address */ 438 #define MEMH_OFFSET 0x14 /* SLIM base memory high address */ 439 #define REG_ADDR_OFFSET 0x18 /* REGISTER base memory address */ 440 #define REGH_OFFSET 0x1c /* REGISTER base memory high address */ 441 #define IO_ADDR_OFFSET 0x20 /* BIU I/O registers */ 442 #define REGIOH_OFFSET 0x24 /* REGISTER base io high address */ 443 444 #define CMD_REG_OFFSET 0x4 /* PCI command configuration */ 445 446 /* General PCI Register Definitions */ 447 /* Refer To The PCI Specification For Detailed Explanations */ 448 449 #define PCI_VENDOR_ID_REGISTER 0x00 /* PCI Vendor ID Reg */ 450 #define PCI_DEVICE_ID_REGISTER 0x02 /* PCI Device ID Reg */ 451 #define PCI_CONFIG_ID_REGISTER 0x00 /* PCI Configuration ID Reg */ 452 #define PCI_COMMAND_REGISTER 0x04 /* PCI Command Reg */ 453 #define PCI_STATUS_REGISTER 0x06 /* PCI Status Reg */ 454 #define PCI_REV_ID_REGISTER 0x08 /* PCI Revision ID Reg */ 455 #define PCI_CLASS_CODE_REGISTER 0x09 /* PCI Class Code Reg */ 456 #define PCI_CACHE_LINE_REGISTER 0x0C /* PCI Cache Line Reg */ 457 #define PCI_LATENCY_TMR_REGISTER 0x0D /* PCI Latency Timer Reg */ 458 #define PCI_HEADER_TYPE_REGISTER 0x0E /* PCI Header Type Reg */ 459 #define PCI_BIST_REGISTER 0x0F /* PCI Built-In SelfTest Reg */ 460 #define PCI_BAR_0_REGISTER 0x10 /* PCI Base Address Reg 0 */ 461 #define PCI_BAR_1_REGISTER 0x14 /* PCI Base Address Reg 1 */ 462 #define PCI_BAR_2_REGISTER 0x18 /* PCI Base Address Reg 2 */ 463 #define PCI_BAR_3_REGISTER 0x1C /* PCI Base Address Reg 3 */ 464 #define PCI_BAR_4_REGISTER 0x20 /* PCI Base Address Reg 4 */ 465 #define PCI_BAR_5_REGISTER 0x24 /* PCI Base Address Reg 5 */ 466 #define PCI_SSID_REGISTER 0x2C 467 #define PCI_SSVID_REGISTER 0x2C 468 #define PCI_SSDID_REGISTER 0x2E 469 #define PCI_EXPANSION_ROM 0x30 /* PCI Expansion ROM Base Reg */ 470 #define PCI_CAP_POINTER 0x34 471 472 /* PCI capatability registers are defined in pci.h */ 473 #define PCI_CAP_ID_SHIFT 0 474 #define PCI_CAP_ID_MASK 0xff 475 #define PCI_CAP_NEXT_PTR_SHIFT 8 476 #define PCI_CAP_NEXT_PTR_MASK 0xff 477 478 /* PCI extended capatability registers are defined in pcie.h */ 479 #define PCI_EXT_CAP_MAX_PTR 0x30 480 481 #define PCI_EXT_CAP_ID_MRIOV 0x0000 /* ??? */ 482 #define PCI_EXT_CAP_ID_SRIOV 0x0010 483 #define PCI_EXT_CAP_ID_11 0x0011 484 #define PCI_EXT_CAP_ID_12 0x0012 485 #define PCI_EXT_CAP_ID_13 0x0013 486 #define PCI_EXT_CAP_ID_14 0x0014 487 #define PCI_EXT_CAP_ID_15 0x0015 488 #define PCI_EXT_CAP_ID_16 0x0016 489 #define PCI_EXT_CAP_ID_TPH 0x0017 490 #define PCI_EXT_CAP_ID_18 0x0018 491 #define PCI_EXT_CAP_ID_SEC_PCI 0x0019 492 493 /* Vendor Specific (VS) register */ 494 #define PCI_VS_SLI_INTF_OFFSET 4 495 496 /* PCI access methods */ 497 #define P_CONF_T1 1 498 #define P_CONF_T2 2 499 500 /* max number of pci buses */ 501 #define MAX_PCI_BUSES 0xFF 502 503 /* number of PCI config bytes to access */ 504 #define PCI_BYTE 1 505 #define PCI_WORD 2 506 #define PCI_DWORD 4 507 508 /* PCI related constants */ 509 #define CMD_IO_ENBL 0x0001 510 #define CMD_MEM_ENBL 0x0002 511 #define CMD_BUS_MASTER 0x0004 512 #define CMD_MWI 0x0010 513 #define CMD_PARITY_CHK 0x0040 514 #define CMD_SERR_ENBL 0x0100 515 516 #define CMD_CFG_VALUE 0x156 /* mem enable, master, MWI, SERR, PERR */ 517 518 /* PCI addresses */ 519 #define PCI_SPACE_ENABLE 0x0CF8 520 #define CF1_CONFIG_ADDR_REGISTER 0x0CF8 521 #define CF1_CONFIG_DATA_REGISTER 0x0CFC 522 #define CF2_FORWARD_REGISTER 0x0CFA 523 #define CF2_BASE_ADDRESS 0xC000 524 525 526 #define DEFAULT_PCI_LATENCY_CLOCKS 0xf8 /* 0xF8 is a special value */ 527 /* for FF11.1N6 firmware. */ 528 /* Use 0x80 for pre-FF11.1N6 */ 529 /* &N7, etc */ 530 #define PCI_LATENCY_VALUE 0xf8 531 532 533 534 /* ==== Register Bit Definitions ==== */ 535 536 /* Used by SBUS adapter */ 537 /* SBUS Control Register */ 538 #define SBUS_CTRL_REG_OFFSET 0 /* Word offset from reg base addr */ 539 540 #define SBUS_CTRL_SBRST 0x00000001 /* Bit 0 */ 541 #define SBUS_CTRL_BKOFF 0x00000002 /* Bit 1 */ 542 #define SBUS_CTRL_ENP 0x00000004 /* Bit 2 */ 543 #define SBUS_CTRL_EN64 0x00000008 /* Bit 3 */ 544 #define SBUS_CTRL_SIR_1 0x00000010 /* Bit [6:4] IRL 1, */ 545 /* lowset priority */ 546 #define SBUS_CTRL_SIR_2 0x00000020 547 #define SBUS_CTRL_SIR_3 0x00000030 548 #define SBUS_CTRL_SIR_4 0x00000040 549 #define SBUS_CTRL_SIR_5 0x00000050 550 #define SBUS_CTRL_SIR_6 0x00000060 551 #define SBUS_CTRL_SIR_7 0x00000070 /* IRL 7, highest priority */ 552 553 /* SBUS Status Register */ 554 #define SBUS_STAT_REG_OFFSET 1 /* Word offset from reg base addr */ 555 #define SBUS_STAT_IP 0x00000001 /* Bit 0 */ 556 #define SBUS_STAT_LERR 0x00000002 /* Bit 1 */ 557 #define SBUS_STAT_SBPE 0x00000004 /* Bit 2 */ 558 #define SBUS_STAT_TE 0x00000008 /* Bit 3 */ 559 #define SBUS_STAT_WPE 0x00000010 /* Bit 4 */ 560 #define SBUS_STAT_PERR 0x00000020 /* Bit 5 */ 561 #define SBUS_STAT_SERR 0x00000040 /* Bit 6 */ 562 #define SBUS_STAT_PTA 0x00000080 /* Bit 7 */ 563 564 /* SBUS Update Register */ 565 #define SBUS_UPDATE_REG_OFFSET 2 /* Word offfset from reg base addr */ 566 567 #define SBUS_UPDATE_DATA 0x00000001 /* Bit 0 */ 568 #define SBUS_UPDATE_SPCLK 0x00000002 /* Bit 1 */ 569 #define SBUS_UPDATE_SPCE 0x00000004 /* Bit 2 */ 570 #define SBUS_UPDATE_SPRST 0x00000008 /* Bit 3 */ 571 #define SBUS_UPDATE_SPWE 0x00000010 /* Bit 4 */ 572 #define SBUS_UPDATE_LDFPGA 0x00000080 /* Bit 7 */ 573 574 /* Host Attention Register */ 575 576 #define HA_REG_OFFSET 0 /* Word offset from register base address */ 577 578 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 579 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 580 #define HA_R0ATT 0x00000008 /* Bit 3 */ 581 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 582 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 583 #define HA_R1ATT 0x00000080 /* Bit 7 */ 584 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 585 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 586 #define HA_R2ATT 0x00000800 /* Bit 11 */ 587 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 588 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 589 #define HA_R3ATT 0x00008000 /* Bit 15 */ 590 #define HA_LATT 0x20000000 /* Bit 29 */ 591 #define HA_MBATT 0x40000000 /* Bit 30 */ 592 #define HA_ERATT 0x80000000 /* Bit 31 */ 593 594 595 #ifdef MSI_SUPPORT 596 597 598 /* Host attention interrupt map */ 599 #define EMLXS_MSI_MAP8 {0, HA_R0ATT, HA_R1ATT, HA_R2ATT, \ 600 HA_R3ATT, HA_LATT, HA_MBATT, HA_ERATT} 601 #define EMLXS_MSI_MAP4 {0, HA_R0ATT, HA_R1ATT, HA_R2ATT, 0, 0, 0, 0} 602 #define EMLXS_MSI_MAP2 {0, HA_R0ATT, 0, 0, 0, 0, 0, 0} 603 #define EMLXS_MSI_MAP1 {0, 0, 0, 0, 0, 0, 0, 0} 604 605 /* MSI 0 interrupt mask */ 606 #define EMLXS_MSI0_MASK8 0 607 #define EMLXS_MSI0_MASK4 (HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA| \ 608 HC_ERINT_ENA) 609 #define EMLXS_MSI0_MASK2 (HC_R1INT_ENA|HC_R2INT_ENA|HC_R3INT_ENA| \ 610 HC_MBINT_ENA|HC_LAINT_ENA|HC_ERINT_ENA) 611 #define EMLXS_MSI0_MASK1 (HC_R0INT_ENA|HC_R1INT_ENA|HC_R2INT_ENA| \ 612 HC_R3INT_ENA|HC_MBINT_ENA|HC_LAINT_ENA| \ 613 HC_ERINT_ENA) 614 615 616 #define EMLXS_MSI_MAX_INTRS 8 617 618 #define EMLXS_MSI_MODE1 0 619 #define EMLXS_MSI_MODE2 1 620 #define EMLXS_MSI_MODE4 2 621 #define EMLXS_MSI_MODE8 3 622 #define EMLXS_MSI_MODES 4 623 624 #endif /* MSI_SUPPORT */ 625 626 627 #define IO_THROTTLE_RESERVE 12 628 629 630 631 632 /* Chip Attention Register */ 633 634 #define CA_REG_OFFSET 1 /* Word offset from register base address */ 635 636 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 637 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 638 #define CA_R0ATT 0x00000008 /* Bit 3 */ 639 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 640 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 641 #define CA_R1ATT 0x00000080 /* Bit 7 */ 642 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 643 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 644 #define CA_R2ATT 0x00000800 /* Bit 11 */ 645 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 646 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 647 #define CA_R3ATT 0x00008000 /* Bit 15 */ 648 #define CA_MBATT 0x40000000 /* Bit 30 */ 649 650 /* Host Status Register */ 651 652 #define HS_REG_OFFSET 2 /* Word offset from register base address */ 653 654 #define HS_OVERTEMP 0x00000100 /* Bit 8 */ 655 #define HS_MBRDY 0x00400000 /* Bit 22 */ 656 #define HS_FFRDY 0x00800000 /* Bit 23 */ 657 #define HS_FFER8 0x01000000 /* Bit 24 */ 658 #define HS_FFER7 0x02000000 /* Bit 25 */ 659 #define HS_FFER6 0x04000000 /* Bit 26 */ 660 #define HS_FFER5 0x08000000 /* Bit 27 */ 661 #define HS_FFER4 0x10000000 /* Bit 28 */ 662 #define HS_FFER3 0x20000000 /* Bit 29 */ 663 #define HS_FFER2 0x40000000 /* Bit 30 */ 664 #define HS_FFER1 0x80000000 /* Bit 31 */ 665 #define HS_FFERM 0xFF000000 /* Mask for error bits 31:24 */ 666 667 /* Host Control Register */ 668 669 #define HC_REG_OFFSET 3 /* Word offset from register base address */ 670 671 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 672 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 673 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 674 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 675 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 676 #define HC_INITHBI 0x02000000 /* Bit 25 */ 677 #define HC_INITMB 0x04000000 /* Bit 26 */ 678 #define HC_INITFF 0x08000000 /* Bit 27 */ 679 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 680 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 681 682 /* BIU Configuration Register */ 683 684 #define BC_REG_OFFSET 4 /* Word offset from register base address */ 685 686 #define BC_BSE 0x00000001 /* Bit 0 */ 687 #define BC_BSE_SWAP 0x01000000 /* Bit 0 - swapped */ 688 689 /* 690 * End FireFly Register definitions 691 */ 692 693 /* 694 * Start SLI 4 section. 695 */ 696 697 /* PCI Config Register offsets */ 698 #define PCICFG_UE_STATUS_LO_OFFSET 0xA0 /* Error Indication - low */ 699 #define PCICFG_UE_STATUS_HI_OFFSET 0xA4 /* Error Indication - high */ 700 #define PCICFG_UE_MASK_LO_OFFSET 0xA8 /* Error mask - low */ 701 #define PCICFG_UE_MASK_HI_OFFSET 0xAC /* Error mask - high */ 702 #define PCICFG_UE_STATUS_ONLINE1 0xB0 /* Error status1 */ 703 #define PCICFG_UE_STATUS_ONLINE2 0xB4 /* Error status2 */ 704 705 /* BAR1 and BAR2 register offsets */ 706 707 /* BAR1 offsets for principal registers */ 708 #define CSR_ISR0_OFFSET 0x0C18 /* CSR for EQ interrupt indications */ 709 #define CSR_IMR0_OFFSET 0x0C48 /* CSR for EQ interrupt masking */ 710 #define CSR_ISCR0_OFFSET 0x0C78 /* CSR for EQ interrupt clearing */ 711 712 #define ISR0_EQ0_INDC 0x00000001 /* Indication bit for EQ0 */ 713 #define ISR0_EQ1_INDC 0x00000002 /* Indication bit for EQ1 */ 714 #define ISR0_EQ2_INDC 0x00000004 /* Indication bit for EQ2 */ 715 #define ISR0_EQ3_INDC 0x00000008 /* Indication bit for EQ3 */ 716 #define ISR0_EQ4_INDC 0x00000010 /* Indication bit for EQ4 */ 717 #define ISR0_EQ5_INDC 0x00000020 /* Indication bit for EQ5 */ 718 #define ISR0_EQ6_INDC 0x00000040 /* Indication bit for EQ6 */ 719 #define ISR0_EQ7_INDC 0x00000080 /* Indication bit for EQ7 */ 720 721 /* MPU EP Semaphore register (ARM POST) */ 722 #define CSR_MPU_EP_SEMAPHORE_OFFSET 0x00AC 723 724 /* SLI Status register */ 725 #define SLI_STATUS_ERROR 0x80000000 /* b31 */ 726 #define SLI_STATUS_BE 0x40000000 /* b30 big endian */ 727 #define SLI_STATUS_OTI 0x20000000 /* b29 over temp */ 728 729 #define SLI_STATUS_DUMP_LOCATION 0x04000000 730 #define SLI_STATUS_DUMP_IMAGE_PRESENT 0x02000000 /* b25 */ 731 #define SLI_STATUS_RESET_NEEDED 0x01000000 /* b24 */ 732 #define SLI_STATUS_READY 0x00800000 /* b23 */ 733 #define SLI_STATUS_INTERRUPT_DISABLE 0x00400000 734 #define SLI_STATUS_FDP 0x00200000 /* b21 func dump present */ 735 736 /* SLI Control register */ 737 #define SLI_CNTL_BE 0x40000000 738 #define SLI_CNTL_INIT_PORT 0x08000000 739 740 /* SLI PHYDEV Control register */ 741 #define SLI_PHYDEV_RERROR 0x80000000 742 #define SLI_PHYDEV_INP 0x40000000 743 #define SLI_PHYDEV_IPLD 0x00008000 744 #define SLI_PHYDEV_GPC 0x00004000 745 #define SLI_PHYDEV_GP 0x00002000 746 747 #define SLI_PHYDEV_RC_MASK 0x00000700 748 #define SLI_PHYDEV_RC_UNKNOWN 0x00000000 749 #define SLI_PHYDEV_RC_PROFILE 0x00000100 750 #define SLI_PHYDEV_RC_FACTORY 0x00000200 751 752 #define SLI_PHYDEV_FRL_MASK 0x000000F0 753 #define SLI_PHYDEV_FRL_ALL 0x00000000 754 #define SLI_PHYDEV_FRL_FCOE 0x00000010 755 756 #define SLI_PHYDEV_LC 0x00000008 757 #define SLI_PHYDEV_DD 0x00000004 758 #define SLI_PHYDEV_FRST 0x00000002 759 #define SLI_PHYDEV_DRST 0x00000001 760 761 /* POST Stages of interest */ 762 #define ARM_POST_FATAL 0x80000000 763 #define ARM_POST_READY 0xc000 764 #define ARM_POST_MASK 0xffff 765 #define ARM_UNRECOVERABLE_ERROR 0xf000 766 767 #define MPU_EP_DL 0x04000000 /* Driverloadedbitmask */ 768 #define MPU_EP_ORI 0x08000000 /* OptionROMinstalledbitmask */ 769 #define MPU_EP_IPC 0x10000000 /* IPaddressconflictmask */ 770 #define MPU_EP_NIP 0x20000000 /* NoIPaddressmask */ 771 #define MPU_EP_BFW 0x40000000 /* BackupFWinusemask */ 772 #define MPU_EP_ERR 0x80000000 /* POSTfatalerrormask */ 773 774 /* physical devices BAR2 offsets for principal doorbell registers */ 775 776 #define PD_RQ_DB_OFFSET 0x00A0 /* Doorbell notify of posted RQEs */ 777 #define PD_WQ_DB_OFFSET 0x0040 /* Doorbell notify of posted WQEs */ 778 #define PD_CQ_DB_OFFSET 0x0120 /* Doorbell notify of processed CQEs or EQEs */ 779 #define PD_MQ_DB_OFFSET 0x0140 /* Doorbell notify of posted MQEs */ 780 781 #define PD_MB_DB_OFFSET 0x0160 /* Doorbell Bootstrap Mailbox */ 782 783 /* physical devices BAR1 offsets for principal doorbell registers */ 784 785 #define PD_IF6_RQ_DB_OFFSET 0x0080 /* Doorbell notify of posted RQEs */ 786 #define PD_IF6_WQ_DB_OFFSET 0x0040 /* Doorbell notify of posted WQEs */ 787 #define PD_IF6_CQ_DB_OFFSET 0x00C0 /* Doorbell notify of processed CQEs */ 788 #define PD_IF6_EQ_DB_OFFSET 0x0120 /* Doorbell notify of processed EQEs */ 789 #define PD_IF6_MQ_DB_OFFSET 0x0160 /* Doorbell notify of posted MQEs */ 790 791 /* physical devices BAR0 offsets for principal doorbell registers */ 792 793 #define SLIPORT_SEMAPHORE_OFFSET 0x0400 794 #define SLIPORT_STATUS_OFFSET 0x0404 795 #define SLIPORT_CONTROL_OFFSET 0x0408 796 #define SLIPORT_ERROR1_OFFSET 0x040C 797 #define SLIPORT_ERROR2_OFFSET 0x0410 798 #define PHYSDEV_CONTROL_OFFSET 0x0414 799 #define SLIPORT_EQDELAY_OFFSET 0x0418 800 801 /* Doorbell definitions */ 802 803 /* Defines for MQ doorbell */ 804 #define MQ_DB_POP_SHIFT 16 /* shift for entries popped */ 805 #define MQ_DB_POP_MASK 0x1FFF0000 /* Mask for number of entries popped */ 806 807 /* Defines for CQ doorbell */ 808 #define CQ_DB_POP_SHIFT 16 /* shift for entries popped */ 809 #define CQ_DB_POP_MASK 0x1FFF0000 /* Mask for number of entries popped */ 810 #define CQ_DB_REARM 0x20000000 /* Bit 29, rearm */ 811 #define CQ_ID_LO_BITS 10 /* num of id bits that are "low" */ 812 #define CQ_DB_ID_LO_MASK ((1 << CQ_ID_LO_BITS) - 1) 813 #define CQ_DB_ID_HI_SHIFT 11 814 #define CQ_DB_ID_HI_MASK (0x1F << CQ_DB_ID_HI_SHIFT) 815 816 /* Defines for EQ doorbell */ 817 #define EQ_DB_CLEAR 0x00000200 /* Bit 9, designates clear EQ ISR */ 818 #define EQ_DB_EVENT 0x00000400 /* Bit 10, designates EQ */ 819 #define EQ_DB_POP_SHIFT 16 /* shift for entries popped */ 820 #define EQ_DB_POP_MASK 0x1FFF0000 /* Mask for number of entries popped */ 821 #define EQ_DB_REARM 0x20000000 /* Bit 29, rearm */ 822 #define EQ_ID_LO_BITS 9 /* num of id bits that are "low" */ 823 #define EQ_DB_ID_LO_MASK ((1 << EQ_ID_LO_BITS) - 1) 824 #define EQ_DB_ID_HI_SHIFT 11 825 #define EQ_DB_ID_HI_MASK (0x1F << EQ_DB_ID_HI_SHIFT) 826 827 /* Defines for WQ doorbell */ 828 #define WQ_DB_POST_SHIFT 24 829 #define WQ_DB_POST_MASK (0xFF << WQ_DB_POST_SHIFT) 830 #define WQ_DB_IDX_SHIFT 16 831 #define WQ_DB_IDX_MASK (0xFF << WQ_DB_IDX_SHIFT) 832 833 /* bootstrap mailbox doorbell defines */ 834 #define BMBX_READY 0x00000001 /* Mask for Port Ready bit */ 835 #define BMBX_ADDR_HI 0x00000002 /* Mask for Addr Hi bit */ 836 #define BMBX_ADDR 0xFFFFFFFC /* Mask for Addr bits */ 837 838 /* Sizeof bootstrap mailbox */ 839 #define EMLXS_BOOTSTRAP_MB_SIZE 256 840 841 #define FW_INITIALIZE_WORD0 0xFF1234FF /* Initialize bootstrap wd 0 */ 842 #define FW_INITIALIZE_WORD1 0xFF5678FF /* Initialize bootstrap wd 1 */ 843 844 #define FW_DEINITIALIZE_WORD0 0xFFAABBFF /* DeInitialize bootstrap wd 0 */ 845 #define FW_DEINITIALIZE_WORD1 0xFFCCDDFF /* DeInitialize bootstrap wd 1 */ 846 847 /* ===================================================================== */ 848 849 /* 850 * Start of FCP specific structures 851 */ 852 853 typedef struct emlxs_fcp_rsp 854 { 855 uint32_t rspRsvd1; /* FC Word 0, byte 0:3 */ 856 uint32_t rspRsvd2; /* FC Word 1, byte 0:3 */ 857 858 uint8_t rspStatus0; /* FCP_STATUS byte 0 (reserved) */ 859 uint8_t rspStatus1; /* FCP_STATUS byte 1 (reserved) */ 860 uint8_t rspStatus2; /* FCP_STATUS byte 2 field validity */ 861 #define RSP_LEN_VALID 0x01 /* bit 0 */ 862 #define SNS_LEN_VALID 0x02 /* bit 1 */ 863 #define RESID_OVER 0x04 /* bit 2 */ 864 #define RESID_UNDER 0x08 /* bit 3 */ 865 866 uint8_t rspStatus3; /* FCP_STATUS byte 3 SCSI status byte */ 867 #define SCSI_STAT_GOOD 0x00 868 #define SCSI_STAT_CHECK_COND 0x02 869 #define SCSI_STAT_COND_MET 0x04 870 #define SCSI_STAT_BUSY 0x08 871 #define SCSI_STAT_INTERMED 0x10 872 #define SCSI_STAT_INTERMED_CM 0x14 873 #define SCSI_STAT_RES_CNFLCT 0x18 874 #define SCSI_STAT_CMD_TERM 0x22 875 #define SCSI_STAT_QUE_FULL 0x28 876 #define SCSI_STAT_ACA_ACTIVE 0x30 877 #define SCSI_STAT_TASK_ABORT 0x40 878 879 uint32_t rspResId; /* Residual xfer if RESID_xxxx set */ 880 /* in fcpStatus2. */ 881 /* Received in Big Endian format */ 882 uint32_t rspSnsLen; /* Length of sense data in fcpSnsInfo */ 883 /* Received in Big Endian format */ 884 uint32_t rspRspLen; /* Length of FCP response data */ 885 /* in fcpRspInfo */ 886 /* Received in Big Endian format */ 887 888 uint8_t rspInfo0; /* FCP_RSP_INFO byte 0 (reserved) */ 889 uint8_t rspInfo1; /* FCP_RSP_INFO byte 1 (reserved) */ 890 uint8_t rspInfo2; /* FCP_RSP_INFO byte 2 (reserved) */ 891 uint8_t rspInfo3; /* FCP_RSP_INFO RSP_CODE byte 3 */ 892 893 #define RSP_NO_FAILURE 0x00 894 #define RSP_DATA_BURST_ERR 0x01 895 #define RSP_CMD_FIELD_ERR 0x02 896 #define RSP_RO_MISMATCH_ERR 0x03 897 #define RSP_TM_NOT_SUPPORTED 0x04 /* Task mgmt function not supported */ 898 #define RSP_TM_NOT_COMPLETED 0x05 /* Task mgmt function not performed */ 899 900 uint32_t rspInfoRsvd; /* FCP_RSP_INFO bytes 4-7 (reserved) */ 901 902 /* 903 * Define maximum size of SCSI Sense buffer. 904 * Seagate never issues more than 18 bytes of Sense data 905 */ 906 #define MAX_FCP_SNS 128 907 uint8_t rspSnsInfo[MAX_FCP_SNS]; 908 } emlxs_fcp_rsp; 909 typedef emlxs_fcp_rsp FCP_RSP; 910 911 912 typedef struct emlxs_fcp_cmd 913 { 914 uint32_t fcpLunMsl; /* most significant lun word */ 915 uint32_t fcpLunLsl; /* least significant lun word */ 916 917 /* 918 * # of bits to shift lun id to end up in right payload word, 919 * little endian = 8, big = 16. 920 */ 921 #ifdef EMLXS_LITTLE_ENDIAN 922 #define FC_LUN_SHIFT 8 923 #define FC_ADDR_MODE_SHIFT 0 924 #endif 925 #ifdef EMLXS_BIG_ENDIAN 926 #define FC_LUN_SHIFT 16 927 #define FC_ADDR_MODE_SHIFT 24 928 #endif 929 930 uint8_t fcpCntl0; /* FCP_CNTL byte 0 (reserved) */ 931 uint8_t fcpCntl1; /* FCP_CNTL byte 1 task codes */ 932 #define SIMPLE_Q 0x00 933 #define HEAD_OF_Q 0x01 934 #define ORDERED_Q 0x02 935 #define ACA_Q 0x04 936 #define UNTAGGED 0x05 937 938 uint8_t fcpCntl2; /* FCP_CTL byte 2 task management */ 939 /* codes */ 940 #define ABORT_TASK_SET 0x02 /* Bit 1 */ 941 #define CLEAR_TASK_SET 0x04 /* bit 2 */ 942 #define LUN_RESET 0x10 /* bit 4 */ 943 #define TARGET_RESET 0x20 /* bit 5 */ 944 #define CLEAR_ACA 0x40 /* bit 6 */ 945 #define TERMINATE_TASK 0x80 /* bit 7 */ 946 947 uint8_t fcpCntl3; 948 #define WRITE_DATA 0x01 /* Bit 0 */ 949 #define READ_DATA 0x02 /* Bit 1 */ 950 951 uint8_t fcpCdb[16]; /* SRB cdb field is copied here */ 952 uint32_t fcpDl; /* Total transfer length */ 953 } emlxs_fcp_cmd_t; 954 typedef emlxs_fcp_cmd_t FCP_CMND; 955 956 957 958 959 /* SCSI INQUIRY Command Structure */ 960 961 typedef struct emlxs_inquiryDataType 962 { 963 uint8_t DeviceType:5; 964 uint8_t DeviceTypeQualifier:3; 965 966 uint8_t DeviceTypeModifier:7; 967 uint8_t RemovableMedia:1; 968 969 uint8_t Versions; 970 uint8_t ResponseDataFormat; 971 uint8_t AdditionalLength; 972 uint8_t Reserved[2]; 973 974 uint8_t SoftReset:1; 975 uint8_t CommandQueue:1; 976 uint8_t Reserved2:1; 977 uint8_t LinkedCommands:1; 978 uint8_t Synchronous:1; 979 uint8_t Wide16Bit:1; 980 uint8_t Wide32Bit:1; 981 uint8_t RelativeAddressing:1; 982 983 uint8_t VendorId[8]; 984 uint8_t ProductId[16]; 985 uint8_t ProductRevisionLevel[4]; 986 uint8_t VendorSpecific[20]; 987 uint8_t Reserved3[40]; 988 } emlxs_inquiry_data_type_t; 989 typedef emlxs_inquiry_data_type_t INQUIRY_DATA_DEF; 990 991 992 typedef struct emlxs_read_capacity_data 993 { 994 uint32_t LogicalBlockAddress; 995 uint32_t BytesPerBlock; 996 } emlxs_read_capacity_data_t; 997 typedef emlxs_read_capacity_data_t READ_CAPACITY_DATA_DEF; 998 999 1000 /* SCSI CDB command codes */ 1001 #define FCP_SCSI_FORMAT_UNIT 0x04 1002 #define FCP_SCSI_INQUIRY 0x12 1003 #define FCP_SCSI_MODE_SELECT 0x15 1004 #define FCP_SCSI_MODE_SENSE 0x1A 1005 #define FCP_SCSI_PAUSE_RESUME 0x4B 1006 #define FCP_SCSI_PLAY_AUDIO 0x45 1007 #define FCP_SCSI_PLAY_AUDIO_EXT 0xA5 1008 #define FCP_SCSI_PLAY_AUDIO_MSF 0x47 1009 #define FCP_SCSI_PLAY_AUDIO_TRK_INDX 0x48 1010 #define FCP_SCSI_PREVENT_ALLOW_REMOVAL 0x1E 1011 #define FCP_SCSI_READ_CMD 0x08 1012 #define FCP_SCSI_READ_BUFFER 0x3C 1013 #define FCP_SCSI_READ_CAPACITY 0x25 1014 #define FCP_SCSI_READ_DEFECT_LIST 0x37 1015 #define FCP_SCSI_READ_EXTENDED 0x28 1016 #define FCP_SCSI_READ_HEADER 0x44 1017 #define FCP_SCSI_READ_LONG 0xE8 1018 #define FCP_SCSI_READ_SUB_CHANNEL 0x42 1019 #define FCP_SCSI_READ_TOC 0x43 1020 #define FCP_SCSI_REASSIGN_BLOCK 0x07 1021 #define FCP_SCSI_RECEIVE_DIAGNOSTIC_RESULTS 0x1C 1022 #define FCP_SCSI_RELEASE_UNIT 0x17 1023 #define FCP_SCSI_REPORT_LUNS 0xa0 1024 #define FCP_SCSI_REQUEST_SENSE 0x03 1025 #define FCP_SCSI_RESERVE_UNIT 0x16 1026 #define FCP_SCSI_REZERO_UNIT 0x01 1027 #define FCP_SCSI_SEEK 0x0B 1028 #define FCP_SCSI_SEEK_EXTENDED 0x2B 1029 #define FCP_SCSI_SEND_DIAGNOSTIC 0x1D 1030 #define FCP_SCSI_START_STOP_UNIT 0x1B 1031 #define FCP_SCSI_TEST_UNIT_READY 0x00 1032 #define FCP_SCSI_VERIFY 0x2F 1033 #define FCP_SCSI_WRITE_CMD 0x0A 1034 #define FCP_SCSI_WRITE_AND_VERIFY 0x2E 1035 #define FCP_SCSI_WRITE_BUFFER 0x3B 1036 #define FCP_SCSI_WRITE_EXTENDED 0x2A 1037 #define FCP_SCSI_WRITE_LONG 0xEA 1038 #define FCP_SCSI_RELEASE_LUNR 0xBB 1039 #define FCP_SCSI_RELEASE_LUNV 0xBF 1040 1041 #define HPVA_SETPASSTHROUGHMODE 0x27 1042 #define HPVA_EXECUTEPASSTHROUGH 0x29 1043 #define HPVA_CREATELUN 0xE2 1044 #define HPVA_SETLUNSECURITYLIST 0xED 1045 #define HPVA_SETCLOCK 0xF9 1046 #define HPVA_RECOVER 0xFA 1047 #define HPVA_GENERICSERVICEOUT 0xFD 1048 1049 #define DMEP_EXPORT_IN 0x85 1050 #define DMEP_EXPORT_OUT 0x89 1051 1052 #define MDACIOCTL_DIRECT_CMD 0x22 1053 #define MDACIOCTL_STOREIMAGE 0x2C 1054 #define MDACIOCTL_WRITESIGNATURE 0xA6 1055 #define MDACIOCTL_SETREALTIMECLOCK 0xAC 1056 #define MDACIOCTL_PASS_THRU_CDB 0xAD 1057 #define MDACIOCTL_PASS_THRU_INITIATE 0xAE 1058 #define MDACIOCTL_CREATENEWCONF 0xC0 1059 #define MDACIOCTL_ADDNEWCONF 0xC4 1060 #define MDACIOCTL_MORE 0xC6 1061 #define MDACIOCTL_SETPHYSDEVPARAMETER 0xC8 1062 #define MDACIOCTL_SETLOGDEVPARAMETER 0xCF 1063 #define MDACIOCTL_SETCONTROLLERPARAMETER 0xD1 1064 #define MDACIOCTL_WRITESANMAP 0xD4 1065 #define MDACIOCTL_SETMACADDRESS 0xD5 1066 1067 /* 1068 * End of FCP specific structures 1069 */ 1070 1071 #define FL_ALPA 0x00 /* AL_PA of FL_Port */ 1072 1073 /* Fibre Channel Service Parameter definitions */ 1074 1075 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 1076 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 1077 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 1078 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 1079 1080 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 1081 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 1082 #define FC_PH3 0x20 /* FC-PH-3 version */ 1083 1084 #define FF_FRAME_SIZE 2048 1085 1086 1087 typedef struct emlxs_rings 1088 { 1089 #ifdef EMLXS_BIG_ENDIAN 1090 uint32_t crReserved:16; 1091 uint32_t crBegin:8; 1092 uint32_t crEnd:8; /* Low order bit first word */ 1093 uint32_t rrReserved:16; 1094 uint32_t rrBegin:8; 1095 uint32_t rrEnd:8; /* Low order bit second word */ 1096 #endif 1097 #ifdef EMLXS_LITTLE_ENDIAN 1098 uint32_t crEnd:8; /* Low order bit first word */ 1099 uint32_t crBegin:8; 1100 uint32_t crReserved:16; 1101 uint32_t rrEnd:8; /* Low order bit second word */ 1102 uint32_t rrBegin:8; 1103 uint32_t rrReserved:16; 1104 #endif 1105 } emlxs_rings_t; 1106 typedef emlxs_rings_t RINGS; 1107 1108 1109 typedef struct emlxs_ring_def 1110 { 1111 #ifdef EMLXS_BIG_ENDIAN 1112 uint16_t offCiocb; 1113 uint16_t numCiocb; 1114 uint16_t offRiocb; 1115 uint16_t numRiocb; 1116 #endif 1117 #ifdef EMLXS_LITTLE_ENDIAN 1118 uint16_t numCiocb; 1119 uint16_t offCiocb; 1120 uint16_t numRiocb; 1121 uint16_t offRiocb; 1122 #endif 1123 } emlxs_ring_def_t; 1124 typedef emlxs_ring_def_t RING_DEF; 1125 1126 /* 1127 * The following F.C. frame stuctures are defined in Big Endian format. 1128 */ 1129 1130 typedef struct emlxs_name_type 1131 { 1132 #ifdef EMLXS_BIG_ENDIAN 1133 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 1134 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 */ 1135 /* of IEEE ext */ 1136 #endif 1137 #ifdef EMLXS_LITTLE_ENDIAN 1138 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 8:11 */ 1139 /* of IEEE ext */ 1140 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 1141 #endif 1142 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 1143 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 1144 #define NAME_FC_TYPE 0x3 /* FC native name type */ 1145 #define NAME_IP_TYPE 0x4 /* IP address */ 1146 #define NAME_CCITT_TYPE 0xC 1147 #define NAME_CCITT_GR_TYPE 0xE 1148 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, */ 1149 /* IEEE extended Lsb */ 1150 uint8_t IEEE[6]; /* FC IEEE address */ 1151 } emlxs_name_type_t; 1152 typedef emlxs_name_type_t NAME_TYPE; 1153 1154 1155 /* 1156 * Word 1 Bit 31 in common service parameter is overloaded. 1157 * Word 1 Bit 31 in FLOGI/FDISC request is multiple NPort request 1158 * Word 1 Bit 31 in FLOGI/FDISC response is clean address bit 1159 */ 1160 #define CLEAN_ADDRESS_BIT reqMultipleNPort /* Word 1, bit 31 */ 1161 1162 typedef struct emlxs_csp 1163 { 1164 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 1165 uint8_t fcphLow; 1166 uint8_t bbCreditMsb; 1167 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 1168 #ifdef EMLXS_BIG_ENDIAN 1169 uint16_t reqMultipleNPort:1; /* FC Word 1, bit 31 */ 1170 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 1171 uint16_t rspMultipleNPort:1; /* FC Word 1, bit 29 */ 1172 uint16_t fPort:1; /* FC Word 1, bit 28 */ 1173 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 1174 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 1175 uint16_t multicast:1; /* FC Word 1, bit 25 */ 1176 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 1177 1178 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 1179 uint16_t simplex:1; /* FC Word 1, bit 22 */ 1180 1181 uint16_t fcsp_support:1; /* FC Word 1, bit 21 */ 1182 uint16_t word1Reserved20:1; /* FC Word 1, bit 20 */ 1183 uint16_t word1Reserved19:1; /* FC Word 1, bit 19 */ 1184 1185 uint16_t dhd:1; /* FC Word 1, bit 18 */ 1186 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 1187 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 1188 #endif 1189 #ifdef EMLXS_LITTLE_ENDIAN 1190 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 1191 uint16_t multicast:1; /* FC Word 1, bit 25 */ 1192 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 1193 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 1194 uint16_t fPort:1; /* FC Word 1, bit 28 */ 1195 uint16_t rspMultipleNPort:1; /* FC Word 1, bit 29 */ 1196 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 1197 uint16_t reqMultipleNPort:1; /* FC Word 1, bit 31 */ 1198 1199 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 1200 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 1201 uint16_t dhd:1; /* FC Word 1, bit 18 */ 1202 1203 uint16_t word1Reserved19:1; /* FC Word 1, bit 19 */ 1204 uint16_t word1Reserved20:1; /* FC Word 1, bit 20 */ 1205 uint16_t fcsp_support:1; /* FC Word 1, bit 21 */ 1206 1207 uint16_t simplex:1; /* FC Word 1, bit 22 */ 1208 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 1209 #endif 1210 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 1211 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 1212 union 1213 { 1214 struct 1215 { 1216 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 1217 1218 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 1219 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 1220 1221 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 1222 } nPort; 1223 uint32_t r_a_tov; /* R_A_TOV must be in Big */ 1224 /* Endian format */ 1225 } w2; 1226 1227 uint32_t e_d_tov; /* E_D_TOV must be in Big */ 1228 /* Endian format */ 1229 } emlxs_csp_t; 1230 typedef emlxs_csp_t CSP; 1231 1232 1233 typedef struct emlxs_class_parms 1234 { 1235 #ifdef EMLXS_BIG_ENDIAN 1236 uint8_t classValid:1; /* FC Word 0, bit 31 */ 1237 uint8_t intermix:1; /* FC Word 0, bit 30 */ 1238 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 1239 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 1240 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 1241 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 1242 #endif 1243 #ifdef EMLXS_LITTLE_ENDIAN 1244 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 1245 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 1246 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 1247 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 1248 uint8_t intermix:1; /* FC Word 0, bit 30 */ 1249 uint8_t classValid:1; /* FC Word 0, bit 31 */ 1250 1251 #endif 1252 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 1253 #ifdef EMLXS_BIG_ENDIAN 1254 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 1255 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 1256 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 1257 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 1258 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 1259 #endif 1260 #ifdef EMLXS_LITTLE_ENDIAN 1261 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 1262 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 1263 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 1264 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 1265 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 1266 #endif 1267 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 1268 #ifdef EMLXS_BIG_ENDIAN 1269 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 1270 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 1271 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 1272 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 1273 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 1274 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 1275 #endif 1276 #ifdef EMLXS_LITTLE_ENDIAN 1277 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 1278 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 1279 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 1280 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 1281 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 1282 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 1283 #endif 1284 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 1285 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 1286 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 1287 1288 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 1289 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 1290 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 1291 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 1292 1293 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 1294 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 1295 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 1296 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 1297 } emlxs_class_parms_t; 1298 typedef emlxs_class_parms_t CLASS_PARMS; 1299 1300 1301 typedef struct emlxs_serv_parms 1302 { /* Structure is in Big Endian format */ 1303 CSP cmn; 1304 NAME_TYPE portName; 1305 NAME_TYPE nodeName; 1306 CLASS_PARMS cls1; 1307 CLASS_PARMS cls2; 1308 CLASS_PARMS cls3; 1309 CLASS_PARMS cls4; 1310 uint8_t vendorVersion[16]; 1311 } emlxs_serv_parms_t; 1312 typedef emlxs_serv_parms_t SERV_PARM; 1313 1314 typedef struct 1315 { 1316 union 1317 { 1318 uint32_t word0; 1319 struct 1320 { 1321 #ifdef EMLXS_BIG_ENDIAN 1322 uint32_t rsvd0:8; /* Word 0, Byte 3 */ 1323 uint32_t oui:24; /* Elx Organization */ 1324 /* Unique ID (0000C9) */ 1325 #endif 1326 #ifdef EMLXS_LITTLE_ENDIAN 1327 uint32_t oui:24; /* Elx Organization */ 1328 /* Unique ID (0000C9) */ 1329 uint32_t rsvd0:8; /* Word 0, Byte 3 */ 1330 #endif 1331 } w0; 1332 } un0; 1333 union 1334 { 1335 uint32_t word1; 1336 struct 1337 { 1338 #ifdef EMLXS_BIG_ENDIAN 1339 uint32_t vport:1; /* Word 1, Bit 31 */ 1340 uint32_t rsvd1:31; /* Word 1, Bit 0-30 */ 1341 #endif 1342 #ifdef EMLXS_LITTLE_ENDIAN 1343 uint32_t rsvd1:31; /* Word 1, Bit 0-30 */ 1344 uint32_t vport:1; /* Word 1, Bit 31 */ 1345 #endif 1346 } w1; 1347 } un1; 1348 uint8_t rsvd2[8]; 1349 } emlxs_vvl_fmt_t; 1350 1351 #define VALID_VENDOR_VERSION cmn.rspMultipleNPort 1352 1353 1354 1355 /* 1356 * Extended Link Service LS_COMMAND codes (Payload BYTE 0) 1357 */ 1358 #ifdef EMLXS_BIG_ENDIAN 1359 #define ELS_CMD_SHIFT 24 1360 #define ELS_CMD_MASK 0xff000000 1361 #define ELS_RSP_MASK 0xff000000 1362 #define ELS_CMD_LS_RJT 0x01000000 1363 #define ELS_CMD_ACC 0x02000000 1364 #define ELS_CMD_PLOGI 0x03000000 1365 #define ELS_CMD_FLOGI 0x04000000 1366 #define ELS_CMD_LOGO 0x05000000 1367 #define ELS_CMD_ABTX 0x06000000 1368 #define ELS_CMD_RCS 0x07000000 1369 #define ELS_CMD_RES 0x08000000 1370 #define ELS_CMD_RSS 0x09000000 1371 #define ELS_CMD_RSI 0x0A000000 1372 #define ELS_CMD_ESTS 0x0B000000 1373 #define ELS_CMD_ESTC 0x0C000000 1374 #define ELS_CMD_ADVC 0x0D000000 1375 #define ELS_CMD_RTV 0x0E000000 1376 #define ELS_CMD_RLS 0x0F000000 1377 #define ELS_CMD_ECHO 0x10000000 1378 #define ELS_CMD_TEST 0x11000000 1379 #define ELS_CMD_RRQ 0x12000000 1380 #define ELS_CMD_REC 0x13000000 1381 #define ELS_CMD_PRLI 0x20000000 1382 #define ELS_CMD_PRLO 0x21000000 1383 #define ELS_CMD_SCN 0x22000000 1384 #define ELS_CMD_TPLS 0x23000000 1385 #define ELS_CMD_GPRLO 0x24000000 1386 #define ELS_CMD_GAID 0x30000000 1387 #define ELS_CMD_FACT 0x31000000 1388 #define ELS_CMD_FDACT 0x32000000 1389 #define ELS_CMD_NACT 0x33000000 1390 #define ELS_CMD_NDACT 0x34000000 1391 #define ELS_CMD_QoSR 0x40000000 1392 #define ELS_CMD_RVCS 0x41000000 1393 #define ELS_CMD_PDISC 0x50000000 1394 #define ELS_CMD_FDISC 0x51000000 1395 #define ELS_CMD_ADISC 0x52000000 1396 #define ELS_CMD_FARP 0x54000000 1397 #define ELS_CMD_FARPR 0x55000000 1398 #define ELS_CMD_FAN 0x60000000 1399 #define ELS_CMD_RSCN 0x61000000 1400 #define ELS_CMD_SCR 0x62000000 1401 #define ELS_CMD_LINIT 0x70000000 1402 #define ELS_CMD_RNID 0x78000000 1403 #define ELS_CMD_AUTH 0x90000000 1404 #endif 1405 1406 #ifdef EMLXS_LITTLE_ENDIAN 1407 #define ELS_CMD_SHIFT 0 1408 #define ELS_CMD_MASK 0xff 1409 #define ELS_RSP_MASK 0xff 1410 #define ELS_CMD_LS_RJT 0x01 1411 #define ELS_CMD_ACC 0x02 1412 #define ELS_CMD_PLOGI 0x03 1413 #define ELS_CMD_FLOGI 0x04 1414 #define ELS_CMD_LOGO 0x05 1415 #define ELS_CMD_ABTX 0x06 1416 #define ELS_CMD_RCS 0x07 1417 #define ELS_CMD_RES 0x08 1418 #define ELS_CMD_RSS 0x09 1419 #define ELS_CMD_RSI 0x0A 1420 #define ELS_CMD_ESTS 0x0B 1421 #define ELS_CMD_ESTC 0x0C 1422 #define ELS_CMD_ADVC 0x0D 1423 #define ELS_CMD_RTV 0x0E 1424 #define ELS_CMD_RLS 0x0F 1425 #define ELS_CMD_ECHO 0x10 1426 #define ELS_CMD_TEST 0x11 1427 #define ELS_CMD_RRQ 0x12 1428 #define ELS_CMD_REC 0x13 1429 #define ELS_CMD_PRLI 0x20 1430 #define ELS_CMD_PRLO 0x21 1431 #define ELS_CMD_SCN 0x22 1432 #define ELS_CMD_TPLS 0x23 1433 #define ELS_CMD_GPRLO 0x24 1434 #define ELS_CMD_GAID 0x30 1435 #define ELS_CMD_FACT 0x31 1436 #define ELS_CMD_FDACT 0x32 1437 #define ELS_CMD_NACT 0x33 1438 #define ELS_CMD_NDACT 0x34 1439 #define ELS_CMD_QoSR 0x40 1440 #define ELS_CMD_RVCS 0x41 1441 #define ELS_CMD_PDISC 0x50 1442 #define ELS_CMD_FDISC 0x51 1443 #define ELS_CMD_ADISC 0x52 1444 #define ELS_CMD_FARP 0x54 1445 #define ELS_CMD_FARPR 0x55 1446 #define ELS_CMD_FAN 0x60 1447 #define ELS_CMD_RSCN 0x61 1448 #define ELS_CMD_SCR 0x62 1449 #define ELS_CMD_LINIT 0x70 1450 #define ELS_CMD_RNID 0x78 1451 #define ELS_CMD_AUTH 0x90 1452 #endif 1453 1454 1455 /* 1456 * LS_RJT Payload Definition 1457 */ 1458 1459 typedef struct _LS_RJT 1460 { /* Structure is in Big Endian format */ 1461 union 1462 { 1463 uint32_t lsRjtError; 1464 struct 1465 { 1466 uint8_t lsRjtRsvd0; /* FC Word 0, */ 1467 /* bit 24:31 */ 1468 1469 uint8_t lsRjtRsnCode; /* FC Word 0, */ 1470 /* bit 16:23 */ 1471 /* LS_RJT reason codes */ 1472 #define LSRJT_INVALID_CMD 0x01 1473 #define LSRJT_LOGICAL_ERR 0x03 1474 #define LSRJT_LOGICAL_BSY 0x05 1475 #define LSRJT_PROTOCOL_ERR 0x07 1476 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 1477 #define LSRJT_CMD_UNSUPPORTED 0x0B 1478 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 1479 1480 uint8_t lsRjtRsnCodeExp; /* FC Word 0, */ 1481 /* bit 8:15 */ 1482 /* LS_RJT reason explanation */ 1483 #define LSEXP_NOTHING_MORE 0x00 1484 #define LSEXP_SPARM_OPTIONS 0x01 1485 #define LSEXP_SPARM_ICTL 0x03 1486 #define LSEXP_SPARM_RCTL 0x05 1487 #define LSEXP_SPARM_RCV_SIZE 0x07 1488 #define LSEXP_SPARM_CONCUR_SEQ 0x09 1489 #define LSEXP_SPARM_CREDIT 0x0B 1490 #define LSEXP_INVALID_PNAME 0x0D 1491 #define LSEXP_INVALID_NNAME 0x0E 1492 #define LSEXP_INVALID_CSP 0x0F 1493 #define LSEXP_INVALID_ASSOC_HDR 0x11 1494 #define LSEXP_ASSOC_HDR_REQ 0x13 1495 #define LSEXP_INVALID_O_SID 0x15 1496 #define LSEXP_INVALID_OX_RX 0x17 1497 #define LSEXP_CMD_IN_PROGRESS 0x19 1498 #define LSEXP_INVALID_NPORT_ID 0x1F 1499 #define LSEXP_INVALID_SEQ_ID 0x21 1500 #define LSEXP_INVALID_XCHG 0x23 1501 #define LSEXP_INACTIVE_XCHG 0x25 1502 #define LSEXP_RQ_REQUIRED 0x27 1503 #define LSEXP_OUT_OF_RESOURCE 0x29 1504 #define LSEXP_CANT_GIVE_DATA 0x2A 1505 #define LSEXP_REQ_UNSUPPORTED 0x2C 1506 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 1507 } b; 1508 } un; 1509 } LS_RJT; 1510 1511 1512 /* 1513 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 1514 */ 1515 1516 typedef struct _LOGO 1517 { /* Structure is in Big Endian format */ 1518 union 1519 { 1520 uint32_t nPortId32; /* Access nPortId as a word */ 1521 struct 1522 { 1523 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 1524 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 1525 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 1526 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 1527 } b; 1528 } un; 1529 NAME_TYPE portName; /* N_port name field */ 1530 } LOGO; 1531 1532 1533 /* 1534 * FCP Login (PRLI Request / ACC) Payload Definition 1535 */ 1536 1537 #define PRLX_PAGE_LEN 0x10 1538 #define TPRLO_PAGE_LEN 0x14 1539 1540 typedef struct _PRLI 1541 { /* Structure is in Big Endian format */ 1542 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 1543 1544 #define PRLI_FCP_TYPE 0x08 1545 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 1546 1547 #ifdef EMLXS_BIG_ENDIAN 1548 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1549 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1550 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 1551 1552 /* ACC = imagePairEstablished */ 1553 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 1554 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1555 /* ACC ONLY */ 1556 #endif 1557 #ifdef EMLXS_LITTLE_ENDIAN 1558 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1559 /* ACC ONLY */ 1560 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 1561 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 1562 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1563 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1564 /* ACC = imagePairEstablished */ 1565 #endif 1566 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 1567 #define PRLI_NO_RESOURCES 0x2 1568 #define PRLI_INIT_INCOMPLETE 0x3 1569 #define PRLI_NO_SUCH_PA 0x4 1570 #define PRLI_PREDEF_CONFIG 0x5 1571 #define PRLI_PARTIAL_SUCCESS 0x6 1572 #define PRLI_INVALID_PAGE_CNT 0x7 1573 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 1574 1575 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 1576 1577 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 1578 1579 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 1580 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 1581 #ifdef EMLXS_BIG_ENDIAN 1582 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 1583 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 1584 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 1585 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 1586 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 1587 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 1588 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 1589 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 1590 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 1591 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 1592 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 1593 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 1594 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 1595 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 1596 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 1597 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 1598 #endif 1599 #ifdef EMLXS_LITTLE_ENDIAN 1600 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 1601 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 1602 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 1603 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 1604 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 1605 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 1606 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 1607 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 1608 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 1609 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 1610 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 1611 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 1612 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 1613 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 1614 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 1615 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 1616 #endif 1617 } PRLI; 1618 1619 /* 1620 * FCP Logout (PRLO Request / ACC) Payload Definition 1621 */ 1622 1623 typedef struct _PRLO 1624 { /* Structure is in Big Endian format */ 1625 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 1626 1627 #define PRLO_FCP_TYPE 0x08 1628 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 1629 1630 #ifdef EMLXS_BIG_ENDIAN 1631 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1632 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1633 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 1634 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1635 /* ACC ONLY */ 1636 #endif 1637 #ifdef EMLXS_LITTLE_ENDIAN 1638 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, */ 1639 /* ACC ONLY */ 1640 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 1641 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 1642 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 1643 #endif 1644 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 1645 #define PRLO_NO_SUCH_IMAGE 0x4 1646 #define PRLO_INVALID_PAGE_CNT 0x7 1647 1648 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 1649 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 1650 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 1651 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 1652 } PRLO; 1653 1654 1655 typedef struct _ADISC 1656 { /* Structure is in Big Endian format */ 1657 uint32_t hardAL_PA; 1658 NAME_TYPE portName; 1659 NAME_TYPE nodeName; 1660 uint32_t DID; 1661 } ADISC; 1662 1663 1664 typedef struct _FARP 1665 { /* Structure is in Big Endian format */ 1666 uint32_t Mflags:8; 1667 uint32_t Odid:24; 1668 #define FARP_NO_ACTION 0 /* FARP information enclosed, no action */ 1669 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 1670 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 1671 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 1672 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not supported */ 1673 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not supported */ 1674 uint32_t Rflags:8; 1675 uint32_t Rdid:24; 1676 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 1677 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 1678 NAME_TYPE OportName; 1679 NAME_TYPE OnodeName; 1680 NAME_TYPE RportName; 1681 NAME_TYPE RnodeName; 1682 uint8_t Oipaddr[16]; 1683 uint8_t Ripaddr[16]; 1684 } FARP; 1685 1686 typedef struct _FAN 1687 { /* Structure is in Big Endian format */ 1688 uint32_t Fdid; 1689 NAME_TYPE FportName; 1690 NAME_TYPE FnodeName; 1691 } FAN; 1692 1693 typedef struct _SCR 1694 { /* Structure is in Big Endian format */ 1695 uint8_t resvd1; 1696 uint8_t resvd2; 1697 uint8_t resvd3; 1698 uint8_t Function; 1699 #define SCR_FUNC_FABRIC 0x01 1700 #define SCR_FUNC_NPORT 0x02 1701 #define SCR_FUNC_FULL 0x03 1702 #define SCR_CLEAR 0xff 1703 } SCR; 1704 1705 typedef struct _RNID_TOP_DISC 1706 { 1707 NAME_TYPE portName; 1708 uint8_t resvd[8]; 1709 uint32_t unitType; 1710 #define RNID_HBA 0x7 1711 #define RNID_HOST 0xa 1712 #define RNID_DRIVER 0xd 1713 uint32_t physPort; 1714 uint32_t attachedNodes; 1715 uint16_t ipVersion; 1716 #define RNID_IPV4 0x1 1717 #define RNID_IPV6 0x2 1718 uint16_t UDPport; 1719 uint8_t ipAddr[16]; 1720 uint16_t resvd1; 1721 uint16_t flags; 1722 #define RNID_TD_SUPPORT 0x1 1723 #define RNID_LP_VALID 0x2 1724 } RNID_TOP_DISC; 1725 1726 typedef struct _RNID 1727 { /* Structure is in Big Endian format */ 1728 uint8_t Format; 1729 #define RNID_TOPOLOGY_DISC 0xdf 1730 uint8_t CommonLen; 1731 uint8_t resvd1; 1732 uint8_t SpecificLen; 1733 NAME_TYPE portName; 1734 NAME_TYPE nodeName; 1735 union 1736 { 1737 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 1738 } un; 1739 } RNID; 1740 1741 typedef struct _RRQ 1742 { /* Structure is in Big Endian format */ 1743 uint32_t SID; 1744 uint16_t Oxid; 1745 uint16_t Rxid; 1746 uint8_t resv[32]; /* optional association hdr */ 1747 } RRQ; 1748 1749 1750 /* This is used for RSCN command */ 1751 typedef struct _D_ID 1752 { /* Structure is in Big Endian format */ 1753 union 1754 { 1755 uint32_t word; 1756 struct 1757 { 1758 #ifdef EMLXS_BIG_ENDIAN 1759 uint8_t resv; 1760 uint8_t domain; 1761 uint8_t area; 1762 uint8_t id; 1763 #endif 1764 #ifdef EMLXS_LITTLE_ENDIAN 1765 uint8_t id; 1766 uint8_t area; 1767 uint8_t domain; 1768 uint8_t resv; 1769 #endif 1770 } b; 1771 } un; 1772 } D_ID; 1773 1774 /* 1775 * Structure to define all ELS Payload types 1776 */ 1777 1778 typedef struct _ELS_PKT 1779 { /* Structure is in Big Endian format */ 1780 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 1781 uint8_t elsByte1; 1782 uint8_t elsByte2; 1783 uint8_t elsByte3; 1784 union 1785 { 1786 LS_RJT lsRjt; /* Payload for LS_RJT */ 1787 SERV_PARM logi; /* Payload for PLOGI, FLOGI */ 1788 /* PDISC, ACC */ 1789 LOGO logo; /* Payload for PLOGO, FLOGO */ 1790 /* ACC */ 1791 PRLI prli; /* Payload for PRLI/ACC */ 1792 PRLO prlo; /* Payload for PRLO/ACC */ 1793 ADISC adisc; /* Payload for ADISC/ACC */ 1794 FARP farp; /* Payload for FARP/ACC */ 1795 FAN fan; /* Payload for FAN */ 1796 SCR scr; /* Payload for SCR/ACC */ 1797 RRQ rrq; /* Payload for RRQ */ 1798 RNID rnid; /* Payload for RNID */ 1799 uint8_t pad[128 - 4]; /* Pad out to payload of */ 1800 /* 128 bytes */ 1801 } un; 1802 } ELS_PKT; 1803 1804 1805 typedef struct 1806 { 1807 uint32_t bdeAddress; 1808 #ifdef EMLXS_BIG_ENDIAN 1809 uint32_t bdeReserved:4; 1810 uint32_t bdeAddrHigh:4; 1811 uint32_t bdeSize:24; 1812 #endif 1813 #ifdef EMLXS_LITTLE_ENDIAN 1814 uint32_t bdeSize:24; 1815 uint32_t bdeAddrHigh:4; 1816 uint32_t bdeReserved:4; 1817 #endif 1818 } ULP_BDE; 1819 1820 typedef struct ULP_BDE_64 1821 { /* SLI-2 */ 1822 union ULP_BDE_TUS 1823 { 1824 uint32_t w; 1825 struct 1826 { 1827 #ifdef EMLXS_BIG_ENDIAN 1828 uint32_t bdeFlags:8; /* BDE Flags 0 IS A */ 1829 /* SUPPORTED VALUE !! */ 1830 uint32_t bdeSize:24; /* buff size in bytes */ 1831 #endif 1832 #ifdef EMLXS_LITTLE_ENDIAN 1833 uint32_t bdeSize:24; /* buff size in bytes */ 1834 uint32_t bdeFlags:8; /* BDE Flags 0 IS A */ 1835 /* SUPPORTED VALUE !! */ 1836 #endif 1837 #define BUFF_USE_RSVD 0x01 /* bdeFlags */ 1838 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */ 1839 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */ 1840 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, */ 1841 /* 0=xmit buffer */ 1842 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr */ 1843 /* 0=64 bit addr */ 1844 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */ 1845 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */ 1846 #define BUFF_TYPE_INVALID 0x80 /* "" "" */ 1847 } f; 1848 } tus; 1849 uint32_t addrLow; 1850 uint32_t addrHigh; 1851 } ULP_BDE64; 1852 1853 #define BDE64_SIZE_WORD 0 1854 #define BPL64_SIZE_WORD 0x40 1855 1856 /* ULP */ 1857 typedef struct ULP_BPL_64 1858 { 1859 ULP_BDE64 fccmd_payload; 1860 ULP_BDE64 fcrsp_payload; 1861 ULP_BDE64 fcdat_payload; 1862 ULP_BDE64 pat0; 1863 } ULP_BPL64; 1864 1865 typedef struct ULP_BDL 1866 { /* SLI-2 */ 1867 #ifdef EMLXS_BIG_ENDIAN 1868 uint32_t bdeFlags:8; /* BDL Flags */ 1869 uint32_t bdeSize:24; /* Size of BDL array in host */ 1870 /* memory (bytes) */ 1871 #endif 1872 #ifdef EMLXS_LITTLE_ENDIAN 1873 uint32_t bdeSize:24; /* Size of BDL array in host */ 1874 /* memory (bytes) */ 1875 uint32_t bdeFlags:8; /* BDL Flags */ 1876 #endif 1877 uint32_t addrLow; /* Address 0:31 */ 1878 uint32_t addrHigh; /* Address 32:63 */ 1879 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1880 } ULP_BDL; 1881 1882 typedef struct ULP_SGE_64 1883 { /* SLI-4 */ 1884 uint32_t addrHigh; /* Address 32:63 */ 1885 uint32_t addrLow; /* Address 0:31 */ 1886 #ifdef EMLXS_BIG_ENDIAN 1887 uint32_t last:1; /* Last entry in SGL */ 1888 uint32_t type:4; 1889 uint32_t offset:27; 1890 #endif 1891 #ifdef EMLXS_LITTLE_ENDIAN 1892 uint32_t offset:27; 1893 uint32_t type:4; 1894 uint32_t last:1; /* Last entry in SGL */ 1895 #endif 1896 #define EMLXS_SGE_TYPE_DATA 0x0 1897 #define EMLXS_SGE_TYPE_DIF 0x4 1898 #define EMLXS_SGE_TYPE_LSP 0x5 1899 #define EMLXS_SGE_TYPE_ENC_DIF 0x6 1900 #define EMLXS_SGE_TYPE_ENC_SEED 0x7 1901 #define EMLXS_SGE_TYPE_SEED 0x8 1902 #define EMLXS_SGE_TYPE_ENC 0x9 1903 #define EMLXS_SGE_TYPE_SKIP 0xC 1904 1905 uint32_t length; 1906 #define EMLXS_MAX_SGE_SIZE 0x10000 /* 64K max length */ 1907 } ULP_SGE64; 1908 1909 #define EMLXS_XFER_RDY_SIZE 12 /* Payload size of a FCP Transfer Ready */ 1910 1911 typedef struct _BE_PHYS_ADDR 1912 { 1913 uint32_t addrLow; 1914 uint32_t addrHigh; 1915 } BE_PHYS_ADDR; 1916 1917 1918 typedef struct 1919 { 1920 void *fc_mptr; 1921 struct emlxs_memseg *segment; /* Parent segment */ 1922 1923 void *virt; /* virtual address ptr */ 1924 uint64_t phys; /* mapped address */ 1925 uint32_t size; 1926 1927 void *data_handle; 1928 void *dma_handle; 1929 uint32_t tag; 1930 uint32_t flag; 1931 #define MAP_POOL_ALLOCATED 0x00000001 1932 #define MAP_BUF_ALLOCATED 0x00000002 1933 #define MAP_TABLE_ALLOCATED 0x00000004 1934 1935 #ifdef SFCT_SUPPORT 1936 void *fct_private; 1937 #endif /* SFCT_SUPPORT */ 1938 } MATCHMAP; 1939 1940 1941 /* 1942 * This file defines the Header File for the FDMI HBA Management Service 1943 */ 1944 1945 /* 1946 * FDMI HBA MAnagement Operations Command Codes 1947 */ 1948 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 1949 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 1950 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 1951 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 1952 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 1953 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */ 1954 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 1955 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 1956 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 1957 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 1958 1959 /* 1960 * Management Service Subtypes 1961 */ 1962 #define SLI_CT_FDMI_SUBTYPES 0x10 1963 1964 1965 /* 1966 * HBA Management Service Reject Code 1967 */ 1968 #define REJECT_CODE 0x9 /* Unable to perform command request */ 1969 1970 /* 1971 * HBA Management Service Reject Reason Code 1972 * Please refer to the Reason Codes above 1973 */ 1974 1975 /* 1976 * HBA Attribute Types 1977 */ 1978 #define NODE_NAME 0x1 1979 #define MANUFACTURER 0x2 1980 #define SERIAL_NUMBER 0x3 1981 #define MODEL 0x4 1982 #define MODEL_DESCRIPTION 0x5 1983 #define HARDWARE_VERSION 0x6 1984 #define DRIVER_VERSION 0x7 1985 #define OPTION_ROM_VERSION 0x8 1986 #define FIRMWARE_VERSION 0x9 1987 #define VENDOR_SPECIFIC 0xa 1988 #define DRV_NAME 0xb 1989 #define OS_NAME_VERSION 0xc 1990 #define MAX_CT_PAYLOAD_LEN 0xd 1991 1992 /* 1993 * Port Attrubute Types 1994 */ 1995 #define SUPPORTED_FC4_TYPES 0x1 1996 #define SUPPORTED_SPEED 0x2 1997 #define PORT_SPEED 0x3 1998 #define MAX_FRAME_SIZE 0x4 1999 #define OS_DEVICE_NAME 0x5 2000 2001 union AttributesDef 2002 { 2003 /* Structure is in Big Endian format */ 2004 struct 2005 { 2006 uint32_t AttrType:16; 2007 uint32_t AttrLen:16; 2008 } bits; 2009 uint32_t word; 2010 }; 2011 2012 /* 2013 * HBA Attribute Entry (8 - 260 bytes) 2014 */ 2015 typedef struct 2016 { 2017 union AttributesDef ad; 2018 union 2019 { 2020 uint32_t VendorSpecific; 2021 uint32_t SupportSpeed; 2022 uint32_t PortSpeed; 2023 uint32_t MaxFrameSize; 2024 uint32_t MaxCTPayloadLen; 2025 uint8_t SupportFC4Types[32]; 2026 uint8_t OsDeviceName[256]; 2027 uint8_t Manufacturer[64]; 2028 uint8_t SerialNumber[64]; 2029 uint8_t Model[256]; 2030 uint8_t ModelDescription[256]; 2031 uint8_t HardwareVersion[256]; 2032 uint8_t DriverVersion[256]; 2033 uint8_t OptionROMVersion[256]; 2034 uint8_t FirmwareVersion[256]; 2035 uint8_t DriverName[256]; 2036 NAME_TYPE NodeName; 2037 } un; 2038 } ATTRIBUTE_ENTRY, *PATTRIBUTE_ENTRY; 2039 2040 2041 /* 2042 * HBA Attribute Block 2043 */ 2044 typedef struct 2045 { 2046 uint32_t EntryCnt; /* Number of HBA attribute entries */ 2047 ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 2048 } ATTRIBUTE_BLOCK, *PATTRIBUTE_BLOCK; 2049 2050 2051 /* 2052 * Port Entry 2053 */ 2054 typedef struct 2055 { 2056 NAME_TYPE PortName; 2057 } PORT_ENTRY, *PPORT_ENTRY; 2058 2059 /* 2060 * HBA Identifier 2061 */ 2062 typedef struct 2063 { 2064 NAME_TYPE PortName; 2065 } HBA_IDENTIFIER, *PHBA_IDENTIFIER; 2066 2067 /* 2068 * Registered Port List Format 2069 */ 2070 typedef struct 2071 { 2072 uint32_t EntryCnt; 2073 PORT_ENTRY pe; /* Variable-length array */ 2074 } REG_PORT_LIST, *PREG_PORT_LIST; 2075 2076 /* 2077 * Register HBA(RHBA) 2078 */ 2079 typedef struct 2080 { 2081 HBA_IDENTIFIER hi; 2082 REG_PORT_LIST rpl; /* variable-length array */ 2083 } REG_HBA, *PREG_HBA; 2084 2085 /* 2086 * Register HBA Attributes (RHAT) 2087 */ 2088 typedef struct 2089 { 2090 NAME_TYPE HBA_PortName; 2091 ATTRIBUTE_BLOCK ab; 2092 } REG_HBA_ATTRIBUTE, *PREG_HBA_ATTRIBUTE; 2093 2094 /* 2095 * Register Port Attributes (RPA) 2096 */ 2097 typedef struct 2098 { 2099 NAME_TYPE HBA_PortName; 2100 NAME_TYPE PortName; 2101 ATTRIBUTE_BLOCK ab; 2102 } REG_PORT_ATTRIBUTE, *PREG_PORT_ATTRIBUTE; 2103 2104 /* 2105 * Get Registered HBA List (GRHL) Accept Payload Format 2106 */ 2107 typedef struct 2108 { 2109 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Ids */ 2110 NAME_TYPE HBA_PortName; /* Variable-length array */ 2111 } GRHL_ACC_PAYLOAD, *PGRHL_ACC_PAYLOAD; 2112 2113 /* 2114 * Get Registered Port List (GRPL) Accept Payload Format 2115 */ 2116 typedef struct 2117 { 2118 uint32_t RPL_Entry_Cnt; /* No of Reg Port Entries */ 2119 PORT_ENTRY eg_Port_Entry[1]; /* Variable-length array */ 2120 } GRPL_ACC_PAYLOAD, *PGRPL_ACC_PAYLOAD; 2121 2122 /* 2123 * Get Port Attributes (GPAT) Accept Payload Format 2124 */ 2125 2126 typedef struct 2127 { 2128 ATTRIBUTE_BLOCK pab; 2129 } GPAT_ACC_PAYLOAD, *PGPAT_ACC_PAYLOAD; 2130 2131 /* 2132 * Use for Firmware DownLoad 2133 */ 2134 2135 /* download.h */ 2136 2137 #define REDUCED_SRAM_CFG 0x7FFFC /* 9802DC */ 2138 #define FULL_SRAM_CFG 0x13FFFC /* 9802 */ 2139 2140 #define SLI_FW_TYPE_SHIFT(x) ((x << 20)) 2141 #define SLI_FW_ADAPTER_TYPE_MASK 0x00f00000 2142 #define SLI_FW_TYPE_6000 SLI_FW_TYPE_SHIFT(0) 2143 #define SLI_FW_TYPE_7000 SLI_FW_TYPE_SHIFT(1) 2144 #define SLI_FW_TYPE_8000 SLI_FW_TYPE_SHIFT(2) 2145 #define SLI_FW_TYPE_850 SLI_FW_TYPE_SHIFT(3) 2146 #define SLI_FW_TYPE_9000 SLI_FW_TYPE_SHIFT(4) 2147 #define SLI_FW_TYPE_950 SLI_FW_TYPE_SHIFT(5) 2148 #define SLI_FW_TYPE_9802 SLI_FW_TYPE_SHIFT(6) /* [022702] */ 2149 #define SLI_FW_TYPE_982 SLI_FW_TYPE_SHIFT(7) 2150 #define SLI_FW_TYPE_10000 SLI_FW_TYPE_SHIFT(8) 2151 #define SLI_FW_TYPE_1050 SLI_FW_TYPE_SHIFT(9) 2152 #define SLI_FW_TYPE_X1000 SLI_FW_TYPE_SHIFT(0xa) 2153 #define SLI_FW_TYPE_101 SLI_FW_TYPE_SHIFT(0xb) /* LP101 */ 2154 2155 2156 typedef enum emlxs_prog_type 2157 { 2158 TEST_PROGRAM, /* 0 */ 2159 UTIL_PROGRAM, /* 1 */ 2160 FUNC_FIRMWARE, /* 2 */ 2161 BOOT_BIOS, /* 3 */ 2162 CONFIG_DATA, /* 4 */ 2163 SEQUENCER_CODE, /* 5 */ 2164 SLI1_OVERLAY, /* 6 */ 2165 SLI2_OVERLAY, /* 7 */ 2166 GASKET, /* 8 */ 2167 HARDWARE_IMAGE, /* 9 */ 2168 SBUS_FCODE, /* A */ 2169 SLI3_OVERLAY, /* B */ 2170 RESERVED_C, 2171 RESERVED_D, 2172 SLI4_OVERLAY, /* E */ 2173 KERNEL_CODE, /* F */ 2174 MAX_PROG_TYPES 2175 } emlxs_prog_type_t; 2176 2177 2178 typedef struct emlxs_fw_file 2179 { 2180 uint32_t version; 2181 uint32_t revcomp; 2182 char label[16]; 2183 uint32_t offset; 2184 } emlxs_fw_file_t; 2185 2186 typedef struct emlxs_fw_image 2187 { 2188 emlxs_fw_file_t awc; 2189 emlxs_fw_file_t bwc; 2190 emlxs_fw_file_t dwc; 2191 emlxs_fw_file_t prog[MAX_PROG_TYPES]; 2192 } emlxs_fw_image_t; 2193 2194 2195 2196 #define NOP_IMAGE_TYPE 0xe1a00000 2197 2198 #define FLASH_BASE_ADR 0x01400000 2199 #define DL_FROM_SLIM_OFFSET MBOX_EXTENSION_OFFSET 2200 2201 #ifdef MBOX_EXT_SUPPORT 2202 #define DL_SLIM_SEG_BYTE_COUNT MBOX_EXTENSION_SIZE 2203 #else 2204 #define DL_SLIM_SEG_BYTE_COUNT 128 2205 #endif /* MBOX_EXT_SUPPORT */ 2206 2207 #define SLI_CKSUM_LENGTH 4 2208 #define SLI_CKSUM_SEED 0x55555555 2209 #define SLI_CKSUM_ERR 0x1982abcd 2210 2211 #define AIF_NOOP 0xe1a00000 2212 #define AIF_BLAL 0xeb000000 2213 #define OS_EXIT 0xef000011 2214 #define OS_GETENV 0xef000010 2215 #define AIF_IMAGEBASE 0x00008000 2216 #define AIF_BLZINIT 0xeb00000c 2217 #define DEBUG_TASK 0xef041d41 2218 #define AIF_DBG_SRC 2 2219 #define AIF_DBG_LL 1 2220 #define AIF_DATABASAT 0x100 2221 2222 #define JEDEC_ID_ADDRESS 0x0080001c 2223 #define MAX_RBUS_SRAM_SIZE_ADR 0x788 2224 #define MAX_IBUS_SRAM_SIZE_ADR 0x78c 2225 #define FULL_RBUS_SRAM_CFG 0x7fffc 2226 #define FULL_IBUS_SRAM_CFG 0x187fffc 2227 #define REDUCED_RBUS_SRAM_CFG 0x5fffc 2228 #define REDUCED_IBUS_SRAM_CFG 0x183fffc 2229 2230 #define FULL_SRAM_CFG_PROG_ID 1 2231 #define REDUCED_SRAM_CFG_PROG_ID 2 2232 #define OTHER_SRAM_CFG_PROG_ID 3 2233 2234 #define NO_FLASH_MEM_AVAIL 0xf1 2235 2236 #define PROG_TYPE_MASK 0xff000000 2237 #define PROG_TYPE_SHIFT 24 2238 2239 #define FLASH_LOAD_LIST_ADR 0x79c 2240 #define RAM_LOAD_ENTRY_SIZE 9 2241 #define FLASH_LOAD_ENTRY_SIZE 6 2242 #define RAM_LOAD_ENTRY_TYPE 0 2243 #define FLASH_LOAD_ENTRY_TYPE 1 2244 2245 #define CFG_DATA_NO_REGION -3 2246 2247 #define SLI_IMAGE_START 0x20080 2248 #define SLI_VERSION_LOC 0x270 2249 2250 2251 #define SLI_HW_REVISION_CHECK(x, y) ((x & 0xf0) == y) 2252 #define SLI_FCODE_REVISION_CHECK(x, y) (x == y) 2253 2254 2255 /* ************ OBJ firmware ************** */ 2256 #define OBJ_MAX_XFER_SIZE 32768 2257 2258 2259 /* ************ BladeEngine ************** */ 2260 #define BE_SIGNATURE "ServerEngines" 2261 #define BE_DIR_SIGNATURE "*** SE FLAS" 2262 #define BE_BUILD_SIZE 24 2263 #define BE_VERSION_SIZE 32 2264 #define BE_COOKIE_SIZE 32 2265 #define BE_CONTROLLER_SIZE 8 2266 #define BE_FLASH_ENTRIES 32 2267 #define BE_MAX_XFER_SIZE 32768 /* 4K aligned */ 2268 2269 /* ************** BE3 **************** */ 2270 #define BE3_SIGNATURE_SIZE 52 2271 #define BE3_MAX_IMAGE_HEADERS 32 2272 2273 typedef struct emlxs_be3_image_header 2274 { 2275 uint32_t id; 2276 #define UFI_BE3_FLASH_ID 0x01 2277 2278 uint32_t offset; 2279 uint32_t length; 2280 uint32_t checksum; 2281 uint8_t version[BE_VERSION_SIZE]; 2282 2283 } emlxs_be3_image_header_t; 2284 2285 typedef struct emlxs_be3_ufi_header 2286 { 2287 char signature[BE3_SIGNATURE_SIZE]; 2288 uint32_t ufi_version; 2289 uint32_t file_length; 2290 uint32_t checksum; 2291 uint32_t antidote; 2292 uint32_t image_cnt; 2293 char build[BE_BUILD_SIZE]; 2294 uint8_t resv1[32]; 2295 2296 } emlxs_be3_ufi_header_t; 2297 2298 typedef struct emlxs_be3_ufi_controller 2299 { 2300 uint32_t vendor_id; 2301 uint32_t device_id; 2302 uint32_t sub_vendor_id; 2303 uint32_t sub_device_id; 2304 2305 } emlxs_be3_ufi_controller_t; 2306 2307 typedef struct emlxs_be3_flash_header 2308 { 2309 uint32_t format_rev; 2310 uint32_t checksum; 2311 uint32_t antidote; 2312 uint32_t entry_count; 2313 emlxs_be3_ufi_controller_t controller[BE_CONTROLLER_SIZE]; 2314 uint32_t resv0; 2315 uint32_t resv1; 2316 uint32_t resv2; 2317 uint32_t resv3; 2318 } emlxs_be3_flash_header_t; 2319 2320 typedef struct emlxs_be3_flash_entry 2321 { 2322 uint32_t type; 2323 uint32_t offset; 2324 uint32_t block_size; 2325 uint32_t image_size; 2326 uint32_t checksum; 2327 uint32_t entry_point; 2328 uint32_t resv0; 2329 uint32_t resv1; 2330 char version[BE_VERSION_SIZE]; 2331 2332 } emlxs_be3_flash_entry_t; 2333 2334 typedef struct emlxs_be3_flash_dir 2335 { 2336 char cookie[BE_COOKIE_SIZE]; 2337 emlxs_be3_flash_header_t header; 2338 emlxs_be3_flash_entry_t entry[BE_FLASH_ENTRIES]; 2339 2340 } emlxs_be3_flash_dir_t; 2341 2342 typedef struct emlxs_be3_ncsi_header { 2343 uint32_t magic; 2344 uint8_t hdr_len; 2345 uint8_t type; 2346 uint16_t hdr_ver; 2347 uint16_t rsvd0; 2348 uint16_t load_offset; 2349 uint32_t len; 2350 uint32_t flash_offset; 2351 uint8_t ver[16]; 2352 uint8_t name[24]; 2353 uint32_t img_cksum; 2354 uint32_t rsvd1; 2355 uint32_t hdr_cksum; 2356 } emlxs_be3_ncsi_header_t; 2357 2358 2359 /* ************** BE2 **************** */ 2360 #define BE2_SIGNATURE_SIZE 32 2361 2362 2363 typedef struct emlxs_be2_ufi_controller 2364 { 2365 uint32_t vendor_id; 2366 uint32_t device_id; 2367 uint32_t sub_vendor_id; 2368 uint32_t sub_device_id; 2369 2370 } emlxs_be2_ufi_controller_t; 2371 2372 typedef struct emlxs_be2_ufi_header 2373 { 2374 char signature[BE2_SIGNATURE_SIZE]; 2375 uint32_t checksum; 2376 uint32_t antidote; 2377 emlxs_be2_ufi_controller_t controller; 2378 uint32_t file_length; 2379 uint32_t chunk_num; 2380 uint32_t chunk_cnt; 2381 uint32_t image_cnt; 2382 char build[BE_BUILD_SIZE]; 2383 2384 } emlxs_be2_ufi_header_t; 2385 2386 typedef struct emlxs_be2_flash_header /* 96 bytes */ 2387 { 2388 uint32_t format_rev; 2389 uint32_t checksum; 2390 uint32_t antidote; 2391 uint32_t build_num; 2392 emlxs_be2_ufi_controller_t controller[BE_CONTROLLER_SIZE]; 2393 uint32_t active_entry_mask; 2394 uint32_t valid_entry_mask; 2395 uint32_t orig_content_mask; 2396 uint32_t resv0; 2397 uint32_t resv1; 2398 uint32_t resv2; 2399 uint32_t resv3; 2400 uint32_t resv4; 2401 2402 } emlxs_be2_flash_header_t; 2403 2404 typedef struct emlxs_be2_flash_entry 2405 { 2406 uint32_t type; 2407 uint32_t offset; 2408 uint32_t pad_size; 2409 uint32_t image_size; 2410 uint32_t checksum; 2411 uint32_t entry_point; 2412 uint32_t resv0; 2413 uint32_t resv1; 2414 char version[BE_VERSION_SIZE]; 2415 2416 } emlxs_be2_flash_entry_t; 2417 2418 typedef struct emlxs_be2_flash_dir 2419 { 2420 char cookie[BE_COOKIE_SIZE]; 2421 emlxs_be2_flash_header_t header; 2422 emlxs_be2_flash_entry_t entry[BE_FLASH_ENTRIES]; 2423 2424 } emlxs_be2_flash_dir_t; 2425 2426 2427 /* FLASH ENTRY TYPES */ 2428 #define BE_FLASHTYPE_NCSI_FIRMWARE 0x10 /* BE3 */ 2429 #define BE_FLASHTYPE_PXE_BIOS 0x20 2430 #define BE_FLASHTYPE_FCOE_BIOS 0x21 2431 #define BE_FLASHTYPE_ISCSI_BIOS 0x22 2432 #define BE_FLASHTYPE_FLASH_ISM 0x30 /* BE3 */ 2433 #define BE_FLASHTYPE_ISCSI_FIRMWARE 0xA0 2434 #define BE_FLASHTYPE_ISCSI_FIRMWARE_COMP 0xA1 2435 #define BE_FLASHTYPE_FCOE_FIRMWARE 0xA2 2436 #define BE_FLASHTYPE_FCOE_FIRMWARE_COMP 0xA3 2437 #define BE_FLASHTYPE_ISCSI_BACKUP 0xB0 2438 #define BE_FLASHTYPE_ISCSI_BACKUP_COMP 0xB1 2439 #define BE_FLASHTYPE_FCOE_BACKUP 0xB2 2440 #define BE_FLASHTYPE_FCOE_BACKUP_COMP 0xB3 2441 #define BE_FLASHTYPE_PHY_FIRMWARE 0xC0 /* 10Base-T */ 2442 #define BE_FLASHTYPE_REDBOOT 0xE0 2443 2444 /* Flash types in download order */ 2445 typedef enum emlxs_be_flashtypes 2446 { 2447 PHY_FIRMWARE_FLASHTYPE, 2448 NCSI_FIRMWARE_FLASHTYPE, 2449 ISCSI_FIRMWARE_FLASHTYPE, 2450 ISCSI_BACKUP_FLASHTYPE, 2451 FCOE_FIRMWARE_FLASHTYPE, 2452 FCOE_BACKUP_FLASHTYPE, 2453 ISCSI_BIOS_FLASHTYPE, 2454 FCOE_BIOS_FLASHTYPE, 2455 PXE_BIOS_FLASHTYPE, 2456 REDBOOT_FLASHTYPE, 2457 BE_MAX_FLASHTYPES 2458 2459 } emlxs_be_flashtypes_t; 2460 2461 /* Driver level constructs */ 2462 typedef struct emlxs_be_fw_file 2463 { 2464 uint32_t be_version; 2465 uint32_t ufi_plus; 2466 2467 uint32_t type; 2468 uint32_t image_offset; 2469 uint32_t image_size; 2470 uint32_t block_size; 2471 uint32_t block_crc; 2472 uint32_t load_address; /* BE3 */ 2473 char label[BE_VERSION_SIZE]; 2474 } emlxs_be_fw_file_t; 2475 2476 typedef struct emlxs_be_fw_image 2477 { 2478 uint32_t be_version; 2479 uint32_t ufi_plus; 2480 2481 uint32_t fcoe_version; 2482 char fcoe_label[BE_VERSION_SIZE]; 2483 2484 uint32_t iscsi_version; 2485 char iscsi_label[BE_VERSION_SIZE]; 2486 2487 emlxs_be_fw_file_t file[BE_MAX_FLASHTYPES]; 2488 } emlxs_be_fw_image_t; 2489 2490 2491 typedef struct emlxs_obj_header 2492 { 2493 uint32_t FileSize; 2494 2495 #ifdef EMLXS_BIG_ENDIAN 2496 uint16_t MagicNumHi; 2497 uint16_t MagicNumLo; 2498 2499 uint32_t FileType:8; 2500 uint32_t Id:8; 2501 uint32_t rsvd0:16; 2502 #endif 2503 2504 #ifdef EMLXS_LITTLE_ENDIAN 2505 uint16_t MagicNumLo; 2506 uint16_t MagicNumHi; 2507 2508 uint32_t rsvd0:16; 2509 uint32_t Id:8; 2510 uint32_t FileType:8; 2511 #endif 2512 2513 #define OBJ_MAGIC_NUM_HI 0xFEAA 2514 #define OBJ_MAGIC_NUM_LO 0x0001 2515 #define OBJ_MAGIC_NUM_LO_G6 0x0003 2516 #define OBJ_MAGIC_NUM_LO_G7 0x0005 2517 #define OBJ_MAGIC_NUM_LO_G7P 0x0020 2518 2519 #define OBJ_GRP_FILE_TYPE 0xF7 2520 2521 #define OBJ_LANCER_ID 0xA2 2522 2523 char RevName[128]; 2524 char Date[12]; 2525 char Revision[32]; 2526 } emlxs_obj_header_t; 2527 2528 2529 #ifdef __cplusplus 2530 } 2531 #endif 2532 2533 #endif /* _EMLXS_HW_H */ 2534