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Searched refs:DC1 (Results 1 – 18 of 18) sorted by relevance

/illumos-gate/usr/src/lib/libmvec/common/vis/
H A D__vhypot.S54 #define DC1 %f46 macro
277 fcmple32 DC1,%f50,%o3 ! (2_0) c0 = vis_fcmple32(DC1,x);
279 fcmple32 DC1,%f34,%o0 ! (2_0) c2 = vis_fcmple32(DC1,y);
313 fcmple32 DC1,%f18,%o3 ! (3_1) c0 = vis_fcmple32(DC1,x);
315 fcmple32 DC1,%f30,%o0 ! (3_1) c2 = vis_fcmple32(DC1,y);
357 fcmple32 DC1,%f20,%g5 ! (0_0) c0 = vis_fcmple32(DC1,x);
360 fcmple32 DC1,%f40,%o2 ! (0_0) c2 = vis_fcmple32(DC1,y);
413 fcmple32 DC1,%f36,%g1 ! (1_0) c0 = vis_fcmple32(DC1,x);
416 fcmple32 DC1,%f54,%g5 ! (1_0) c2 = vis_fcmple32(DC1,y);
473 fcmple32 DC1,%f50,%o3 ! (2_0) c0 = vis_fcmple32(DC1,x);
[all …]
H A D__vsqrtf_ultra3.S184 for %f60,DC1,%f40 ! (2_0) db0 = vis_for(db0,DC1);
216 for %f58,DC1,%f48 ! (3_1) db0 = vis_for(db0,DC1);
300 faddd %f52,DC1,%f58 ! (2_1) res0 += DC1;
337 faddd %f54,DC1,%f58 ! (3_1) res0 += DC1;
375 faddd %f52,DC1,%f54 ! (4_1) res0 += DC1;
423 faddd %f52,DC1,%f34 ! (0_1) res0 += DC1;
463 faddd %f48,DC1,%f58 ! (1_1) res0 += DC1;
503 faddd %f52,DC1,%f58 ! (2_1) res0 += DC1;
543 faddd %f54,DC1,%f58 ! (3_1) res0 += DC1;
583 faddd %f52,DC1,%f54 ! (4_1) res0 += DC1;
[all …]
H A D__vrsqrt.S238 for %f16,DC1,%f44 ! (6_1) res = vis_for(res,DC1);
272 for %f16,DC1,%f28 ! (0_0) res = vis_for(res,DC1);
309 for %f16,DC1,%f44 ! (1_0) res = vis_for(res,DC1);
347 for %f16,DC1,%f28 ! (2_0) res = vis_for(res,DC1);
390 for %f16,DC1,%f44 ! (3_0) res = vis_for(res,DC1);
436 for %f16,DC1,%f24 ! (4_0) res = vis_for(res,DC1);
484 for %f16,DC1,%f28 ! (5_0) res = vis_for(res,DC1);
550 for %f16,DC1,%f44 ! (6_1) res = vis_for(res,DC1);
610 for %f16,DC1,%f28 ! (0_0) res = vis_for(res,DC1);
670 for %f16,DC1,%f44 ! (1_0) res = vis_for(res,DC1);
[all …]
H A D__vhypotf.S297 for %f60,DC1,%f46 ! (3_1) h0 = vis_for(h0,DC1);
334 for %f60,DC1,%f46 ! (4_1) h0 = vis_for(h0,DC1);
414 faddd %f40,DC1,%f40 ! (3_1) res0 += DC1;
472 faddd %f58,DC1,%f36 ! (4_2) res0 += DC1;
527 faddd %f38,DC1,%f36 ! (0_1) res0 += DC1;
581 faddd %f44,DC1,%f44 ! (1_1) res0 += DC1;
636 faddd %f54,DC1,%f36 ! (2_1) res0 += DC1;
687 faddd %f40,DC1,%f40 ! (3_1) res0 += DC1;
733 faddd %f58,DC1,%f36 ! (4_2) res0 += DC1;
762 faddd %f38,DC1,%f36 ! (0_1) res0 += DC1;
[all …]
H A D__vrhypotf.S198 #define DC1 %f8 macro
429 for %f30,DC1,%f28 ! (3_1) hyp0 = vis_for(hyp0,DC1);
468 for %f30,DC1,%f28 ! (4_1) hyp0 = vis_for(hyp0,DC1);
510 for %f30,DC1,%f28 ! (0_0) hyp0 = vis_for(hyp0,DC1);
556 for %f30,DC1,%f28 ! (1_0) hyp0 = vis_for(hyp0,DC1);
617 for %f30,DC1,%f28 ! (2_1) hyp0 = vis_for(hyp0,DC1);
672 for %f30,DC1,%f28 ! (3_1) hyp0 = vis_for(hyp0,DC1);
727 for %f30,DC1,%f28 ! (4_1) hyp0 = vis_for(hyp0,DC1);
782 for %f30,DC1,%f28 ! (0_0) hyp0 = vis_for(hyp0,DC1);
837 for %f30,DC1,%f28 ! (1_0) hyp0 = vis_for(hyp0,DC1);
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H A D__vatanf.S40 .word 0x00020000, 0x00000000 ! DC1
171 #define DC1 %f60 macro
219 ! y = vis_fpadd32(x,DC1);
274 ldd [%l2+24],DC1
324 fpadd32 %f22,DC1,%f24 ! (0_0) y = vis_fpadd32(x,dconst1);
347 fpadd32 %f20,DC1,%f24 ! (1_0) y = vis_fpadd32(x,dconst1);
371 fpadd32 %f18,DC1,%f24 ! (2_0) y = vis_fpadd32(x,dconst1);
406 fpadd32 %f16,DC1,%f24 ! (3_0) y = vis_fpadd32(x,dconst1);
444 fpadd32 %f14,DC1,%f24 ! (4_0) y = vis_fpadd32(x,dconst1);
485 fpadd32 %f36,DC1,%f24 ! (5_0) y = vis_fpadd32(x,dconst1);
[all …]
/illumos-gate/usr/src/uts/sun4u/sys/
H A Dopl.h84 DC1, enumerator
/illumos-gate/usr/src/uts/sun4u/opl/os/
H A Dopl.c88 { "DC1", OPL_MAX_BOARDS_DC1, DC1, STD_DISPATCH_TABLE },
924 case DC1: in plat_get_cpu_unum()
/illumos-gate/usr/src/data/locale/data/
H A Dwidths.txt4756 <CJK_UNIFIED_IDEOGRAPH-3DC1> 2
12938 <CJK_UNIFIED_IDEOGRAPH-5DC1> 2
17034 <CJK_UNIFIED_IDEOGRAPH-6DC1> 2
21130 <CJK_UNIFIED_IDEOGRAPH-7DC1> 2
25226 <CJK_UNIFIED_IDEOGRAPH-8DC1> 2
29322 <CJK_UNIFIED_IDEOGRAPH-9DC1> 2
H A Dzh_CN.GB18030.src9808 <CJK_UNIFIED_IDEOGRAPH-3DC1>;/
17926 <CJK_UNIFIED_IDEOGRAPH-5DC1>;/
22022 <CJK_UNIFIED_IDEOGRAPH-6DC1>;/
26118 <CJK_UNIFIED_IDEOGRAPH-7DC1>;/
30214 <CJK_UNIFIED_IDEOGRAPH-8DC1>;/
34310 <CJK_UNIFIED_IDEOGRAPH-9DC1>;/
64077 <CJK_UNIFIED_IDEOGRAPH-3DC1>;/
72259 <CJK_UNIFIED_IDEOGRAPH-5DC1>;/
76355 <CJK_UNIFIED_IDEOGRAPH-6DC1>;/
80451 <CJK_UNIFIED_IDEOGRAPH-7DC1>;/
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H A Dzh_CN.UTF-8.src54705 <CJK_UNIFIED_IDEOGRAPH-8DC1> <X7EE8>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-8DC…
65918 <CJK_UNIFIED_IDEOGRAPH-5DC1> <XC0E9>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-5DC…
70612 <CJK_UNIFIED_IDEOGRAPH-6DC1> <XDC37>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-6DC…
70623 <CJK_UNIFIED_IDEOGRAPH-7DC1> <XDC48>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-7DC…
78394 <CJK_UNIFIED_IDEOGRAPH-9DC1> "<XFAEB><X0800>";<X05>;"<X05><XC0>";<CJK_UNIFI…
H A Dzh_SG.UTF-8.src54705 <CJK_UNIFIED_IDEOGRAPH-8DC1> <X7EE8>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-8DC…
65918 <CJK_UNIFIED_IDEOGRAPH-5DC1> <XC0E9>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-5DC…
70612 <CJK_UNIFIED_IDEOGRAPH-6DC1> <XDC37>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-6DC…
70623 <CJK_UNIFIED_IDEOGRAPH-7DC1> <XDC48>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-7DC…
78394 <CJK_UNIFIED_IDEOGRAPH-9DC1> "<XFAEB><X0800>";<X05>;"<X05><XC0>";<CJK_UNIFI…
H A DGB18030.cm14040 <CJK_UNIFIED_IDEOGRAPH-3DC1> \x82\x31\xEB\…
40359 <CJK_UNIFIED_IDEOGRAPH-5DC1> \x8E\x5F
42982 <CJK_UNIFIED_IDEOGRAPH-6DC1> \x9B\xF9
49486 <CJK_UNIFIED_IDEOGRAPH-7DC1> \xBE\x66
54852 <CJK_UNIFIED_IDEOGRAPH-8DC1> \xDA\x95
60878 <CJK_UNIFIED_IDEOGRAPH-9DC1> \xFA\x5E
H A DUTF-8.cm14609 <CJK_UNIFIED_IDEOGRAPH-3DC1> \xE3\xB7\x81
22791 <CJK_UNIFIED_IDEOGRAPH-5DC1> \xE5\xB7\x81
26887 <CJK_UNIFIED_IDEOGRAPH-6DC1> \xE6\xB7\x81
30983 <CJK_UNIFIED_IDEOGRAPH-7DC1> \xE7\xB7\x81
35079 <CJK_UNIFIED_IDEOGRAPH-8DC1> \xE8\xB7\x81
39175 <CJK_UNIFIED_IDEOGRAPH-9DC1> \xE9\xB7\x81
72861 <TANGUT_IDEOGRAPH-17DC1> \xF0\x97\xB7\…
84596 <CJK_UNIFIED_IDEOGRAPH-20DC1> \xF0\xA0\xB7\…
88692 <CJK_UNIFIED_IDEOGRAPH-21DC1> \xF0\xA1\xB7\…
92788 <CJK_UNIFIED_IDEOGRAPH-22DC1> \xF0\xA2\xB7\…
[all …]
H A Dja_JP.UTF-8.src69324 <CJK_UNIFIED_IDEOGRAPH-9DC1> <XFA4E>;<X05>;<X05>;<CJK_UNIFIED_IDEOGRAPH-9DC1>
H A Dko_KR.UTF-8.src49063 …NIFIED_IDEOGRAPH-9DC1> "<X781C><X788F><X78B3>";"<X05><X05><X7D><XB4>";"<X05><X05><X0…
/illumos-gate/usr/src/data/terminfo/
H A Dtermcap.src9424 # No delays specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
9441 # delays are specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
9614 # delays are specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
10132 # require/do not require receipt of a DC1 from host after each LF*
10642 # "stty ixon -ixany" to enable DC3/DC1 flow control!
14412 # Delays not specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
14492 # delays are specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
14534 # delays are specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
14920 # The modem interface is permitted to discard LF (maybe DC1), otherwise
14938 # Enable DC3/DC1 flow control with "stty ixon -ixany".
[all …]
H A Dterminfo.src10642 # No delays specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
10661 # delays are specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
10894 # delays are specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
11470 # require/do not require receipt of a DC1 from host after each LF*
12033 # "stty ixon -ixany" to enable DC3/DC1 flow control!
16277 # Delays not specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
16365 # delays are specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
16410 # delays are specified; use "stty ixon -ixany" to enable DC3/DC1 flow control!
16838 # The modem interface is permitted to discard LF (maybe DC1), otherwise
16859 # Enable DC3/DC1 flow control with "stty ixon -ixany".
[all …]