1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, v.1, (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://opensource.org/licenses/CDDL-1.0. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014-2017 Cavium, Inc. 24 * The contents of this file are subject to the terms of the Common Development 25 * and Distribution License, v.1, (the "License"). 26 27 * You may not use this file except in compliance with the License. 28 29 * You can obtain a copy of the License at available 30 * at http://opensource.org/licenses/CDDL-1.0 31 32 * See the License for the specific language governing permissions and 33 * limitations under the License. 34 */ 35 36 #ifndef __ECORE_HSI_ETH__ 37 #define __ECORE_HSI_ETH__ 38 /************************************************************************/ 39 /* Add include to common eth target for both eCore and protocol driver */ 40 /************************************************************************/ 41 #include "eth_common.h" 42 43 /* 44 * The eth storm context for the Tstorm 45 */ 46 struct tstorm_eth_conn_st_ctx 47 { 48 __le32 reserved[4]; 49 }; 50 51 /* 52 * The eth storm context for the Pstorm 53 */ 54 struct pstorm_eth_conn_st_ctx 55 { 56 __le32 reserved[8]; 57 }; 58 59 /* 60 * The eth storm context for the Xstorm 61 */ 62 struct xstorm_eth_conn_st_ctx 63 { 64 __le32 reserved[60]; 65 }; 66 67 struct e4_xstorm_eth_conn_ag_ctx 68 { 69 u8 reserved0 /* cdu_validation */; 70 u8 eth_state /* state */; 71 u8 flags0; 72 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 73 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 74 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 75 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1 76 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 77 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2 78 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 79 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 80 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 81 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4 82 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 83 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5 84 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 85 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6 86 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 87 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7 88 u8 flags1; 89 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 90 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0 91 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 92 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1 93 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 94 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2 95 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 96 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3 97 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 98 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4 99 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 100 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5 101 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 102 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 103 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 104 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 105 u8 flags2; 106 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 107 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 108 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 109 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 110 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 111 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 112 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 113 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 114 u8 flags3; 115 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 116 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 117 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 118 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 119 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 120 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 121 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 122 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 123 u8 flags4; 124 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 125 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 126 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 127 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 128 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 129 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 130 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 131 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 132 u8 flags5; 133 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 134 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 135 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 136 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2 137 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 138 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4 139 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 140 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6 141 u8 flags6; 142 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 143 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 144 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 145 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 146 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 147 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4 148 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 149 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 150 u8 flags7; 151 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 152 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 153 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 154 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2 155 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 156 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4 157 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 158 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6 159 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 160 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7 161 u8 flags8; 162 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 163 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0 164 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 165 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1 166 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 167 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2 168 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 169 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3 170 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 171 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4 172 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 173 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5 174 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 175 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6 176 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 177 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 178 u8 flags9; 179 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 180 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 181 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 182 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 183 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 184 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 185 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 186 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 187 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 188 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 189 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 190 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 191 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 192 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 193 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 194 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 195 u8 flags10; 196 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 197 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 198 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 199 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 200 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 201 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 202 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 203 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 204 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 205 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 206 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 207 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 208 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 209 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 210 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 211 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 212 u8 flags11; 213 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 214 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 215 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 216 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1 217 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 218 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 219 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 220 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3 221 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 222 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4 223 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 224 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5 225 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 226 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 227 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 228 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7 229 u8 flags12; 230 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 231 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0 232 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 233 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1 234 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 235 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 236 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 237 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 238 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 239 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4 240 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 241 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5 242 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 243 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6 244 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 245 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7 246 u8 flags13; 247 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 248 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0 249 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 250 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1 251 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 252 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 253 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 254 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 255 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 256 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 257 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 258 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 259 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 260 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 261 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 262 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 263 u8 flags14; 264 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 265 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 266 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 267 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 268 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 269 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 270 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 271 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 272 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 273 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 274 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 275 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 276 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 277 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 278 u8 edpm_event_id /* byte2 */; 279 __le16 physical_q0 /* physical_q0 */; 280 __le16 e5_reserved1 /* physical_q1 */; 281 __le16 edpm_num_bds /* physical_q2 */; 282 __le16 tx_bd_cons /* word3 */; 283 __le16 tx_bd_prod /* word4 */; 284 __le16 tx_class /* word5 */; 285 __le16 conn_dpi /* conn_dpi */; 286 u8 byte3 /* byte3 */; 287 u8 byte4 /* byte4 */; 288 u8 byte5 /* byte5 */; 289 u8 byte6 /* byte6 */; 290 __le32 reg0 /* reg0 */; 291 __le32 reg1 /* reg1 */; 292 __le32 reg2 /* reg2 */; 293 __le32 reg3 /* reg3 */; 294 __le32 reg4 /* reg4 */; 295 __le32 reg5 /* cf_array0 */; 296 __le32 reg6 /* cf_array1 */; 297 __le16 word7 /* word7 */; 298 __le16 word8 /* word8 */; 299 __le16 word9 /* word9 */; 300 __le16 word10 /* word10 */; 301 __le32 reg7 /* reg7 */; 302 __le32 reg8 /* reg8 */; 303 __le32 reg9 /* reg9 */; 304 u8 byte7 /* byte7 */; 305 u8 byte8 /* byte8 */; 306 u8 byte9 /* byte9 */; 307 u8 byte10 /* byte10 */; 308 u8 byte11 /* byte11 */; 309 u8 byte12 /* byte12 */; 310 u8 byte13 /* byte13 */; 311 u8 byte14 /* byte14 */; 312 u8 byte15 /* byte15 */; 313 u8 e5_reserved /* e5_reserved */; 314 __le16 word11 /* word11 */; 315 __le32 reg10 /* reg10 */; 316 __le32 reg11 /* reg11 */; 317 __le32 reg12 /* reg12 */; 318 __le32 reg13 /* reg13 */; 319 __le32 reg14 /* reg14 */; 320 __le32 reg15 /* reg15 */; 321 __le32 reg16 /* reg16 */; 322 __le32 reg17 /* reg17 */; 323 __le32 reg18 /* reg18 */; 324 __le32 reg19 /* reg19 */; 325 __le16 word12 /* word12 */; 326 __le16 word13 /* word13 */; 327 __le16 word14 /* word14 */; 328 __le16 word15 /* word15 */; 329 }; 330 331 /* 332 * The eth storm context for the Ystorm 333 */ 334 struct ystorm_eth_conn_st_ctx 335 { 336 __le32 reserved[8]; 337 }; 338 339 struct e4_ystorm_eth_conn_ag_ctx 340 { 341 u8 byte0 /* cdu_validation */; 342 u8 state /* state */; 343 u8 flags0; 344 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 345 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 346 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 347 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 348 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */ 349 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2 350 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */ 351 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4 352 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 353 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 354 u8 flags1; 355 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf0en */ 356 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0 357 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 358 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1 359 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 360 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 361 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 362 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 363 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 364 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 365 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 366 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 367 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 368 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 369 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 370 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 371 u8 tx_q0_int_coallecing_timeset /* byte2 */; 372 u8 byte3 /* byte3 */; 373 __le16 word0 /* word0 */; 374 __le32 terminate_spqe /* reg0 */; 375 __le32 reg1 /* reg1 */; 376 __le16 tx_bd_cons_upd /* word1 */; 377 __le16 word2 /* word2 */; 378 __le16 word3 /* word3 */; 379 __le16 word4 /* word4 */; 380 __le32 reg2 /* reg2 */; 381 __le32 reg3 /* reg3 */; 382 }; 383 384 struct e4_tstorm_eth_conn_ag_ctx 385 { 386 u8 byte0 /* cdu_validation */; 387 u8 byte1 /* state */; 388 u8 flags0; 389 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 390 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 391 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 392 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 393 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 394 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 395 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 396 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 397 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 398 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 399 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 400 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 401 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 402 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 403 u8 flags1; 404 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 405 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 406 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 407 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 408 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 409 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 410 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 411 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 412 u8 flags2; 413 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 414 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 415 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 416 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 417 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 418 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 419 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 420 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 421 u8 flags3; 422 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 423 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 424 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 425 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 426 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 427 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 428 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 429 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 430 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 431 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 432 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 433 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 434 u8 flags4; 435 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 436 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 437 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 438 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 439 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 440 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 441 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 442 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 443 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 444 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 445 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 446 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 447 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 448 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 449 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 450 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 451 u8 flags5; 452 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 453 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 454 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 455 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 456 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 457 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 458 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 459 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 460 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 461 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 462 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */ 463 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 464 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 465 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 466 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 467 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 468 __le32 reg0 /* reg0 */; 469 __le32 reg1 /* reg1 */; 470 __le32 reg2 /* reg2 */; 471 __le32 reg3 /* reg3 */; 472 __le32 reg4 /* reg4 */; 473 __le32 reg5 /* reg5 */; 474 __le32 reg6 /* reg6 */; 475 __le32 reg7 /* reg7 */; 476 __le32 reg8 /* reg8 */; 477 u8 byte2 /* byte2 */; 478 u8 byte3 /* byte3 */; 479 __le16 rx_bd_cons /* word0 */; 480 u8 byte4 /* byte4 */; 481 u8 byte5 /* byte5 */; 482 __le16 rx_bd_prod /* word1 */; 483 __le16 word2 /* conn_dpi */; 484 __le16 word3 /* word3 */; 485 __le32 reg9 /* reg9 */; 486 __le32 reg10 /* reg10 */; 487 }; 488 489 struct e4_ustorm_eth_conn_ag_ctx 490 { 491 u8 byte0 /* cdu_validation */; 492 u8 byte1 /* state */; 493 u8 flags0; 494 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 495 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 496 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 497 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 498 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 /* timer0cf */ 499 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2 500 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 /* timer1cf */ 501 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4 502 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 503 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 504 u8 flags1; 505 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 506 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 507 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 /* cf4 */ 508 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 509 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 /* cf5 */ 510 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 511 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf6 */ 512 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 513 u8 flags2; 514 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf0en */ 515 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 516 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 517 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1 518 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 519 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 520 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 521 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3 522 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 /* cf4en */ 523 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4 524 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 /* cf5en */ 525 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5 526 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf6en */ 527 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6 528 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 529 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 530 u8 flags3; 531 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 532 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 533 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 534 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 535 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 536 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 537 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 538 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 539 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 540 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 541 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 542 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 543 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 544 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 545 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 546 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 547 u8 byte2 /* byte2 */; 548 u8 byte3 /* byte3 */; 549 __le16 word0 /* conn_dpi */; 550 __le16 tx_bd_cons /* word1 */; 551 __le32 reg0 /* reg0 */; 552 __le32 reg1 /* reg1 */; 553 __le32 reg2 /* reg2 */; 554 __le32 tx_int_coallecing_timeset /* reg3 */; 555 __le16 tx_drv_bd_cons /* word2 */; 556 __le16 rx_drv_cqe_cons /* word3 */; 557 }; 558 559 /* 560 * The eth storm context for the Ustorm 561 */ 562 struct ustorm_eth_conn_st_ctx 563 { 564 __le32 reserved[40]; 565 }; 566 567 /* 568 * The eth storm context for the Mstorm 569 */ 570 struct mstorm_eth_conn_st_ctx 571 { 572 __le32 reserved[8]; 573 }; 574 575 /* 576 * eth connection context 577 */ 578 struct eth_conn_context 579 { 580 struct tstorm_eth_conn_st_ctx tstorm_st_context /* tstorm storm context */; 581 struct regpair tstorm_st_padding[2] /* padding */; 582 struct pstorm_eth_conn_st_ctx pstorm_st_context /* pstorm storm context */; 583 struct xstorm_eth_conn_st_ctx xstorm_st_context /* xstorm storm context */; 584 struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 585 struct ystorm_eth_conn_st_ctx ystorm_st_context /* ystorm storm context */; 586 struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 587 struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 588 struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 589 struct ustorm_eth_conn_st_ctx ustorm_st_context /* ustorm storm context */; 590 struct mstorm_eth_conn_st_ctx mstorm_st_context /* mstorm storm context */; 591 }; 592 593 594 /* 595 * Ethernet filter types: mac/vlan/pair 596 */ 597 enum eth_error_code 598 { 599 ETH_OK=0x00 /* command succeeded */, 600 ETH_FILTERS_MAC_ADD_FAIL_FULL /* mac add filters command failed due to cam full state */, 601 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2 /* mac add filters command failed due to mtt2 full state */, 602 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2 /* mac add filters command failed due to duplicate mac address */, 603 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2 /* mac add filters command failed due to duplicate mac address */, 604 ETH_FILTERS_MAC_DEL_FAIL_NOF /* mac delete filters command failed due to not found state */, 605 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2 /* mac delete filters command failed due to not found state */, 606 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2 /* mac delete filters command failed due to not found state */, 607 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC /* mac add filters command failed due to MAC Address of 00:00:00:00:00:00 */, 608 ETH_FILTERS_VLAN_ADD_FAIL_FULL /* vlan add filters command failed due to cam full state */, 609 ETH_FILTERS_VLAN_ADD_FAIL_DUP /* vlan add filters command failed due to duplicate VLAN filter */, 610 ETH_FILTERS_VLAN_DEL_FAIL_NOF /* vlan delete filters command failed due to not found state */, 611 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1 /* vlan delete filters command failed due to not found state */, 612 ETH_FILTERS_PAIR_ADD_FAIL_DUP /* pair add filters command failed due to duplicate request */, 613 ETH_FILTERS_PAIR_ADD_FAIL_FULL /* pair add filters command failed due to full state */, 614 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC /* pair add filters command failed due to full state */, 615 ETH_FILTERS_PAIR_DEL_FAIL_NOF /* pair add filters command failed due not found state */, 616 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1 /* pair add filters command failed due not found state */, 617 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC /* pair add filters command failed due to MAC Address of 00:00:00:00:00:00 */, 618 ETH_FILTERS_VNI_ADD_FAIL_FULL /* vni add filters command failed due to cam full state */, 619 ETH_FILTERS_VNI_ADD_FAIL_DUP /* vni add filters command failed due to duplicate VNI filter */, 620 ETH_FILTERS_GFT_UPDATE_FAIL /* Fail update GFT filter. */, 621 MAX_ETH_ERROR_CODE 622 }; 623 624 625 /* 626 * opcodes for the event ring 627 */ 628 enum eth_event_opcode 629 { 630 ETH_EVENT_UNUSED, 631 ETH_EVENT_VPORT_START, 632 ETH_EVENT_VPORT_UPDATE, 633 ETH_EVENT_VPORT_STOP, 634 ETH_EVENT_TX_QUEUE_START, 635 ETH_EVENT_TX_QUEUE_STOP, 636 ETH_EVENT_RX_QUEUE_START, 637 ETH_EVENT_RX_QUEUE_UPDATE, 638 ETH_EVENT_RX_QUEUE_STOP, 639 ETH_EVENT_FILTERS_UPDATE, 640 ETH_EVENT_RX_ADD_OPENFLOW_FILTER, 641 ETH_EVENT_RX_DELETE_OPENFLOW_FILTER, 642 ETH_EVENT_RX_CREATE_OPENFLOW_ACTION, 643 ETH_EVENT_RX_ADD_UDP_FILTER, 644 ETH_EVENT_RX_DELETE_UDP_FILTER, 645 ETH_EVENT_RX_CREATE_GFT_ACTION, 646 ETH_EVENT_RX_GFT_UPDATE_FILTER, 647 MAX_ETH_EVENT_OPCODE 648 }; 649 650 651 /* 652 * Classify rule types in E2/E3 653 */ 654 enum eth_filter_action 655 { 656 ETH_FILTER_ACTION_UNUSED, 657 ETH_FILTER_ACTION_REMOVE, 658 ETH_FILTER_ACTION_ADD, 659 ETH_FILTER_ACTION_REMOVE_ALL /* Remove all filters of given type and vport ID. */, 660 MAX_ETH_FILTER_ACTION 661 }; 662 663 664 /* 665 * Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ 666 */ 667 struct eth_filter_cmd 668 { 669 u8 type /* Filter Type (MAC/VLAN/Pair/VNI) */; 670 u8 vport_id /* the vport id */; 671 u8 action /* filter command action: add/remove/replace */; 672 u8 reserved0; 673 __le32 vni; 674 __le16 mac_lsb; 675 __le16 mac_mid; 676 __le16 mac_msb; 677 __le16 vlan_id; 678 }; 679 680 681 /* 682 * $$KEEP_ENDIANNESS$$ 683 */ 684 struct eth_filter_cmd_header 685 { 686 u8 rx /* If set, apply these commands to the RX path */; 687 u8 tx /* If set, apply these commands to the TX path */; 688 u8 cmd_cnt /* Number of filter commands */; 689 u8 assert_on_error /* 0 - dont assert in case of filter configuration error. Just return an error code. 1 - assert in case of filter configuration error. */; 690 u8 reserved1[4]; 691 }; 692 693 694 /* 695 * Ethernet filter types: mac/vlan/pair 696 */ 697 enum eth_filter_type 698 { 699 ETH_FILTER_TYPE_UNUSED, 700 ETH_FILTER_TYPE_MAC /* Add/remove a MAC address */, 701 ETH_FILTER_TYPE_VLAN /* Add/remove a VLAN */, 702 ETH_FILTER_TYPE_PAIR /* Add/remove a MAC-VLAN pair */, 703 ETH_FILTER_TYPE_INNER_MAC /* Add/remove a inner MAC address */, 704 ETH_FILTER_TYPE_INNER_VLAN /* Add/remove a inner VLAN */, 705 ETH_FILTER_TYPE_INNER_PAIR /* Add/remove a inner MAC-VLAN pair */, 706 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR /* Add/remove a inner MAC-VNI pair */, 707 ETH_FILTER_TYPE_MAC_VNI_PAIR /* Add/remove a MAC-VNI pair */, 708 ETH_FILTER_TYPE_VNI /* Add/remove a VNI */, 709 MAX_ETH_FILTER_TYPE 710 }; 711 712 713 /* 714 * eth IPv4 Fragment Type 715 */ 716 enum eth_ipv4_frag_type 717 { 718 ETH_IPV4_NOT_FRAG /* IPV4 Packet Not Fragmented */, 719 ETH_IPV4_FIRST_FRAG /* First Fragment of IPv4 Packet (contains headers) */, 720 ETH_IPV4_NON_FIRST_FRAG /* Non-First Fragment of IPv4 Packet (does not contain headers) */, 721 MAX_ETH_IPV4_FRAG_TYPE 722 }; 723 724 725 /* 726 * eth IPv4 Fragment Type 727 */ 728 enum eth_ip_type 729 { 730 ETH_IPV4 /* IPv4 */, 731 ETH_IPV6 /* IPv6 */, 732 MAX_ETH_IP_TYPE 733 }; 734 735 736 /* 737 * Ethernet Ramrod Command IDs 738 */ 739 enum eth_ramrod_cmd_id 740 { 741 ETH_RAMROD_UNUSED, 742 ETH_RAMROD_VPORT_START /* VPort Start Ramrod */, 743 ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */, 744 ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */, 745 ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */, 746 ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */, 747 ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */, 748 ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */, 749 ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */, 750 ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */, 751 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION /* RX - Create an Openflow Action */, 752 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER /* RX - Add an Openflow Filter to the Searcher */, 753 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER /* RX - Delete an Openflow Filter to the Searcher */, 754 ETH_RAMROD_RX_ADD_UDP_FILTER /* RX - Add a UDP Filter to the Searcher */, 755 ETH_RAMROD_RX_DELETE_UDP_FILTER /* RX - Delete a UDP Filter to the Searcher */, 756 ETH_RAMROD_RX_CREATE_GFT_ACTION /* RX - Create a Gft Action */, 757 ETH_RAMROD_GFT_UPDATE_FILTER /* RX - Add/Delete a GFT Filter to the Searcher */, 758 MAX_ETH_RAMROD_CMD_ID 759 }; 760 761 762 /* 763 * return code from eth sp ramrods 764 */ 765 struct eth_return_code 766 { 767 u8 value; 768 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F /* error code (use enum eth_error_code) */ 769 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0 770 #define ETH_RETURN_CODE_RESERVED_MASK 0x3 771 #define ETH_RETURN_CODE_RESERVED_SHIFT 5 772 #define ETH_RETURN_CODE_RX_TX_MASK 0x1 /* rx path - 0, tx path - 1 */ 773 #define ETH_RETURN_CODE_RX_TX_SHIFT 7 774 }; 775 776 777 /* 778 * What to do in case an error occurs 779 */ 780 enum eth_tx_err 781 { 782 ETH_TX_ERR_DROP /* Drop erroneous packet. */, 783 ETH_TX_ERR_ASSERT_MALICIOUS /* Assert an interrupt for PF, declare as malicious for VF */, 784 MAX_ETH_TX_ERR 785 }; 786 787 788 /* 789 * Array of the different error type behaviors 790 */ 791 struct eth_tx_err_vals 792 { 793 __le16 values; 794 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1 /* Wrong VLAN insertion mode (use enum eth_tx_err) */ 795 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0 796 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1 /* Packet is below minimal size (use enum eth_tx_err) */ 797 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1 798 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1 /* Vport has sent spoofed packet (use enum eth_tx_err) */ 799 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2 800 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1 /* Packet with illegal type of inband tag (use enum eth_tx_err) */ 801 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3 802 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1 /* Packet marked for VLAN insertion when inband tag is present (use enum eth_tx_err) */ 803 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4 804 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1 /* Non LSO packet larger than MTU (use enum eth_tx_err) */ 805 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5 806 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1 /* VF/PF has sent LLDP/PFC or any other type of control packet which is not allowed to (use enum eth_tx_err) */ 807 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6 808 #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF 809 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7 810 }; 811 812 813 /* 814 * vport rss configuration data 815 */ 816 struct eth_vport_rss_config 817 { 818 __le16 capabilities; 819 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1 /* configuration of the IpV4 2-tuple capability */ 820 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0 821 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1 /* configuration of the IpV6 2-tuple capability */ 822 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1 823 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1 /* configuration of the IpV4 4-tuple capability for TCP */ 824 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2 825 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1 /* configuration of the IpV6 4-tuple capability for TCP */ 826 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3 827 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1 /* configuration of the IpV4 4-tuple capability for UDP */ 828 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4 829 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1 /* configuration of the IpV6 4-tuple capability for UDP */ 830 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5 831 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1 /* configuration of the 5-tuple capability */ 832 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6 833 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF /* if set update the rss keys */ 834 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7 835 u8 rss_id /* The RSS engine ID. Must be allocated to each vport with RSS enabled. Total number of RSS engines is ETH_RSS_ENGINE_NUM_ , according to chip type. */; 836 u8 rss_mode /* The RSS mode for this function */; 837 u8 update_rss_key /* if set update the rss key */; 838 u8 update_rss_ind_table /* if set update the indirection table values */; 839 u8 update_rss_capabilities /* if set update the capabilities and indirection table size. */; 840 u8 tbl_size /* rss mask (Tbl size) */; 841 __le32 reserved2[2]; 842 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM] /* RSS indirection table */; 843 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS] /* RSS key supplied to us by OS */; 844 __le32 reserved3[2]; 845 }; 846 847 848 /* 849 * eth vport RSS mode 850 */ 851 enum eth_vport_rss_mode 852 { 853 ETH_VPORT_RSS_MODE_DISABLED /* RSS Disabled */, 854 ETH_VPORT_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */, 855 MAX_ETH_VPORT_RSS_MODE 856 }; 857 858 859 /* 860 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ 861 */ 862 struct eth_vport_rx_mode 863 { 864 __le16 state; 865 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1 /* drop all unicast packets */ 866 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0 867 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 /* accept all unicast packets (subject to vlan) */ 868 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 869 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1 /* accept all unmatched unicast packets */ 870 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2 871 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1 /* drop all multicast packets */ 872 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3 873 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 /* accept all multicast packets (subject to vlan) */ 874 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4 875 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 /* accept all broadcast packets (subject to vlan) */ 876 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5 877 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF 878 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6 879 __le16 reserved2[3]; 880 }; 881 882 883 /* 884 * Command for setting tpa parameters 885 */ 886 struct eth_vport_tpa_param 887 { 888 u8 tpa_ipv4_en_flg /* Enable TPA for IPv4 packets */; 889 u8 tpa_ipv6_en_flg /* Enable TPA for IPv6 packets */; 890 u8 tpa_ipv4_tunn_en_flg /* Enable TPA for IPv4 over tunnel */; 891 u8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */; 892 u8 tpa_pkt_split_flg /* If set, start each tpa segment on new SGE (GRO mode). One SGE per segment allowed */; 893 u8 tpa_hdr_data_split_flg /* If set, put header of first TPA segment on bd and data on SGE */; 894 u8 tpa_gro_consistent_flg /* If set, GRO data consistent will checked for TPA continue */; 895 u8 tpa_max_aggs_num /* maximum number of opened aggregations per v-port */; 896 __le16 tpa_max_size /* maximal size for the aggregated TPA packets */; 897 __le16 tpa_min_size_to_start /* minimum TCP payload size for a packet to start aggregation */; 898 __le16 tpa_min_size_to_cont /* minimum TCP payload size for a packet to continue aggregation */; 899 u8 max_buff_num /* maximal number of buffers that can be used for one aggregation */; 900 u8 reserved; 901 }; 902 903 904 /* 905 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ 906 */ 907 struct eth_vport_tx_mode 908 { 909 __le16 state; 910 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1 /* drop all unicast packets */ 911 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0 912 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 /* accept all unicast packets (subject to vlan) */ 913 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 914 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1 /* drop all multicast packets */ 915 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2 916 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 /* accept all multicast packets (subject to vlan) */ 917 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3 918 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 /* accept all broadcast packets (subject to vlan) */ 919 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4 920 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF 921 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5 922 __le16 reserved2[3]; 923 }; 924 925 926 /* 927 * Ramrod data for rx create gft action 928 */ 929 enum gft_filter_update_action 930 { 931 GFT_ADD_FILTER, 932 GFT_DELETE_FILTER, 933 MAX_GFT_FILTER_UPDATE_ACTION 934 }; 935 936 937 /* 938 * Ramrod data for rx create gft action 939 */ 940 enum gft_logic_filter_type 941 { 942 GFT_FILTER_TYPE /* flow FW is GFT-logic as well */, 943 RFS_FILTER_TYPE /* flow FW is A-RFS-logic */, 944 MAX_GFT_LOGIC_FILTER_TYPE 945 }; 946 947 948 949 950 /* 951 * Ramrod data for rx add openflow filter 952 */ 953 struct rx_add_openflow_filter_data 954 { 955 __le16 action_icid /* CID of Action to run for this filter */; 956 u8 priority /* Searcher String - Packet priority */; 957 u8 reserved0; 958 __le32 tenant_id /* Searcher String - Tenant ID */; 959 __le16 dst_mac_hi /* Searcher String - Destination Mac Bytes 0 to 1 */; 960 __le16 dst_mac_mid /* Searcher String - Destination Mac Bytes 2 to 3 */; 961 __le16 dst_mac_lo /* Searcher String - Destination Mac Bytes 4 to 5 */; 962 __le16 src_mac_hi /* Searcher String - Source Mac 0 to 1 */; 963 __le16 src_mac_mid /* Searcher String - Source Mac 2 to 3 */; 964 __le16 src_mac_lo /* Searcher String - Source Mac 4 to 5 */; 965 __le16 vlan_id /* Searcher String - Vlan ID */; 966 __le16 l2_eth_type /* Searcher String - Last L2 Ethertype */; 967 u8 ipv4_dscp /* Searcher String - IPv4 6 MSBs of the TOS Field */; 968 u8 ipv4_frag_type /* Searcher String - IPv4 Fragmentation Type */; 969 u8 ipv4_over_ip /* Searcher String - IPv4 Over IP Type */; 970 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */; 971 __le32 ipv4_dst_addr /* Searcher String - IPv4 Destination Address */; 972 __le32 ipv4_src_addr /* Searcher String - IPv4 Source Address */; 973 __le16 l4_dst_port /* Searcher String - TCP/UDP Destination Port */; 974 __le16 l4_src_port /* Searcher String - TCP/UDP Source Port */; 975 }; 976 977 978 /* 979 * Ramrod data for rx create gft action 980 */ 981 struct rx_create_gft_action_data 982 { 983 u8 vport_id /* Vport Id of GFT Action */; 984 u8 reserved[7]; 985 }; 986 987 988 /* 989 * Ramrod data for rx create openflow action 990 */ 991 struct rx_create_openflow_action_data 992 { 993 u8 vport_id /* ID of RX queue */; 994 u8 reserved[7]; 995 }; 996 997 998 /* 999 * Ramrod data for rx queue start ramrod 1000 */ 1001 struct rx_queue_start_ramrod_data 1002 { 1003 __le16 rx_queue_id /* ID of RX queue */; 1004 __le16 num_of_pbl_pages /* Num of pages in CQE PBL */; 1005 __le16 bd_max_bytes /* maximal bytes that can be places on the bd */; 1006 __le16 sb_id /* Status block ID */; 1007 u8 sb_index /* index of the protocol index */; 1008 u8 vport_id /* ID of virtual port */; 1009 u8 default_rss_queue_flg /* set queue as default rss queue if set */; 1010 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 1011 u8 complete_event_flg /* post completion to the event ring if set */; 1012 u8 stats_counter_id /* Statistics counter ID */; 1013 u8 pin_context /* Pin context in CCFC to improve performance */; 1014 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD/SGE fetch */; 1015 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet placement */; 1016 u8 pxp_st_hint /* PXP command Steering tag hint. Use enum pxp_tph_st_hint */; 1017 __le16 pxp_st_index /* PXP command Steering tag index */; 1018 u8 pmd_mode /* Indicates that current queue belongs to poll-mode driver */; 1019 u8 notify_en /* Indicates that the current queue is using the TX notification queue mechanism - should be set only for PMD queue */; 1020 u8 toggle_val /* Initial value for the toggle valid bit - used in PMD mode */; 1021 u8 vf_rx_prod_index /* Index of RX producers in VF zone. Used for VF only. */; 1022 u8 vf_rx_prod_use_zone_a /* Backward compatibility mode. If set, unprotected mStorm queue zone will used for VF RX producers instead of VF zone. */; 1023 u8 reserved[5]; 1024 __le16 reserved1 /* FW reserved. */; 1025 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */; 1026 struct regpair bd_base /* bd address of the first bd page */; 1027 struct regpair reserved2 /* FW reserved. */; 1028 }; 1029 1030 1031 /* 1032 * Ramrod data for rx queue stop ramrod 1033 */ 1034 struct rx_queue_stop_ramrod_data 1035 { 1036 __le16 rx_queue_id /* ID of RX queue */; 1037 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 1038 u8 complete_event_flg /* post completion to the event ring if set */; 1039 u8 vport_id /* ID of virtual port */; 1040 u8 reserved[3]; 1041 }; 1042 1043 1044 /* 1045 * Ramrod data for rx queue update ramrod 1046 */ 1047 struct rx_queue_update_ramrod_data 1048 { 1049 __le16 rx_queue_id /* ID of RX queue */; 1050 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 1051 u8 complete_event_flg /* post completion to the event ring if set */; 1052 u8 vport_id /* ID of virtual port */; 1053 u8 reserved[4]; 1054 u8 reserved1 /* FW reserved. */; 1055 u8 reserved2 /* FW reserved. */; 1056 u8 reserved3 /* FW reserved. */; 1057 __le16 reserved4 /* FW reserved. */; 1058 __le16 reserved5 /* FW reserved. */; 1059 struct regpair reserved6 /* FW reserved. */; 1060 }; 1061 1062 1063 /* 1064 * Ramrod data for rx Add UDP Filter 1065 */ 1066 struct rx_udp_filter_data 1067 { 1068 __le16 action_icid /* CID of Action to run for this filter */; 1069 __le16 vlan_id /* Searcher String - Vlan ID */; 1070 u8 ip_type /* Searcher String - IP Type */; 1071 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */; 1072 __le16 reserved1; 1073 __le32 ip_dst_addr[4] /* Searcher String - IP Destination Address, for IPv4 use ip_dst_addr[0] only */; 1074 __le32 ip_src_addr[4] /* Searcher String - IP Source Address, for IPv4 use ip_dst_addr[0] only */; 1075 __le16 udp_dst_port /* Searcher String - UDP Destination Port */; 1076 __le16 udp_src_port /* Searcher String - UDP Source Port */; 1077 __le32 tenant_id /* Searcher String - Tenant ID */; 1078 }; 1079 1080 1081 /* 1082 * Ramrod to add filter - filter is packet headr of type of packet wished to pass certin FW flow 1083 */ 1084 struct rx_update_gft_filter_data 1085 { 1086 struct regpair pkt_hdr_addr /* Pointer to Packet Header That Defines GFT Filter */; 1087 __le16 pkt_hdr_length /* Packet Header Length */; 1088 __le16 rx_qid_or_action_icid /* If is_rfs flag is set: Queue Id to associate filter with else: action icid */; 1089 u8 vport_id /* Field is used if is_rfs flag is set: vport Id of which to associate filter with */; 1090 u8 filter_type /* Use enum to set type of flow using gft HW logic blocks */; 1091 u8 filter_action /* Use to set type of action on filter */; 1092 u8 assert_on_error /* 0 - dont assert in case of error. Just return an error code. 1 - assert in case of error. */; 1093 }; 1094 1095 1096 1097 /* 1098 * Ramrod data for tx queue start ramrod 1099 */ 1100 struct tx_queue_start_ramrod_data 1101 { 1102 __le16 sb_id /* Status block ID */; 1103 u8 sb_index /* Status block protocol index */; 1104 u8 vport_id /* VPort ID */; 1105 u8 reserved0 /* FW reserved. (qcn_rl_en) */; 1106 u8 stats_counter_id /* Statistics counter ID to use */; 1107 __le16 qm_pq_id /* QM PQ ID */; 1108 u8 flags; 1109 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1 /* 0: Enable QM opportunistic flow. 1: Disable QM opportunistic flow */ 1110 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0 1111 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1 /* If set, Test Mode - packets will be duplicated by Xstorm handler */ 1112 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1 1113 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1 /* If set, Test Mode - packets destination will be determined by dest_port_mode field from Tx BD */ 1114 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2 1115 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1 /* Indicates that current queue belongs to poll-mode driver */ 1116 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3 1117 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1 /* Indicates that the current queue is using the TX notification queue mechanism - should be set only for PMD queue */ 1118 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4 1119 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1 /* Pin context in CCFC to improve performance */ 1120 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5 1121 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3 1122 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6 1123 u8 pxp_st_hint /* PXP command Steering tag hint */; 1124 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD fetch */; 1125 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet fetch */; 1126 __le16 pxp_st_index /* PXP command Steering tag index */; 1127 __le16 comp_agg_size /* TX completion min agg size - for PMD queues */; 1128 __le16 queue_zone_id /* queue zone ID to use */; 1129 __le16 reserved2 /* FW reserved. (test_dup_count) */; 1130 __le16 pbl_size /* Number of BD pages pointed by PBL */; 1131 __le16 tx_queue_id /* unique Queue ID - currently used only by PMD flow */; 1132 __le16 same_as_last_id /* Unique Same-As-Last Resource ID - improves performance for same-as-last packets per connection (range 0..ETH_TX_NUM_SAME_AS_LAST_ENTRIES-1 IDs available) */; 1133 __le16 reserved[3]; 1134 struct regpair pbl_base_addr /* address of the pbl page */; 1135 struct regpair bd_cons_address /* BD consumer address in host - for PMD queues */; 1136 }; 1137 1138 1139 /* 1140 * Ramrod data for tx queue stop ramrod 1141 */ 1142 struct tx_queue_stop_ramrod_data 1143 { 1144 __le16 reserved[4]; 1145 }; 1146 1147 1148 1149 /* 1150 * Ramrod data for vport update ramrod 1151 */ 1152 struct vport_filter_update_ramrod_data 1153 { 1154 struct eth_filter_cmd_header filter_cmd_hdr /* Header for Filter Commands (RX/TX, Add/Remove/Replace, etc) */; 1155 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT] /* Filter Commands */; 1156 }; 1157 1158 1159 /* 1160 * Ramrod data for vport start ramrod 1161 */ 1162 struct vport_start_ramrod_data 1163 { 1164 u8 vport_id; 1165 u8 sw_fid; 1166 __le16 mtu; 1167 u8 drop_ttl0_en /* if set, drop packet with ttl=0 */; 1168 u8 inner_vlan_removal_en; 1169 struct eth_vport_rx_mode rx_mode /* Rx filter data */; 1170 struct eth_vport_tx_mode tx_mode /* Tx filter data */; 1171 struct eth_vport_tpa_param tpa_param /* TPA configuration parameters */; 1172 __le16 default_vlan /* Default Vlan value to be forced by FW */; 1173 u8 tx_switching_en /* Tx switching is enabled for current Vport */; 1174 u8 anti_spoofing_en /* Anti-spoofing verification is set for current Vport */; 1175 u8 default_vlan_en /* If set, the default Vlan value is forced by the FW */; 1176 u8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */; 1177 u8 silent_vlan_removal_en /* If enable then innerVlan will be striped and not written to cqe */; 1178 u8 untagged /* If set untagged filter (vlan0) is added to current Vport, otherwise port is marked as any-vlan */; 1179 struct eth_tx_err_vals tx_err_behav /* Desired behavior per TX error type */; 1180 u8 zero_placement_offset /* If set, ETH header padding will not inserted. placement_offset will be zero. */; 1181 u8 ctl_frame_mac_check_en /* If set, Contorl frames will be filtered according to MAC check. */; 1182 u8 ctl_frame_ethtype_check_en /* If set, Contorl frames will be filtered according to ethtype check. */; 1183 u8 reserved[5]; 1184 }; 1185 1186 1187 /* 1188 * Ramrod data for vport stop ramrod 1189 */ 1190 struct vport_stop_ramrod_data 1191 { 1192 u8 vport_id; 1193 u8 reserved[7]; 1194 }; 1195 1196 1197 /* 1198 * Ramrod data for vport update ramrod 1199 */ 1200 struct vport_update_ramrod_data_cmn 1201 { 1202 u8 vport_id; 1203 u8 update_rx_active_flg /* set if rx active flag should be handled */; 1204 u8 rx_active_flg /* rx active flag value */; 1205 u8 update_tx_active_flg /* set if tx active flag should be handled */; 1206 u8 tx_active_flg /* tx active flag value */; 1207 u8 update_rx_mode_flg /* set if rx state data should be handled */; 1208 u8 update_tx_mode_flg /* set if tx state data should be handled */; 1209 u8 update_approx_mcast_flg /* set if approx. mcast data should be handled */; 1210 u8 update_rss_flg /* set if rss data should be handled */; 1211 u8 update_inner_vlan_removal_en_flg /* set if inner_vlan_removal_en should be handled */; 1212 u8 inner_vlan_removal_en; 1213 u8 update_tpa_param_flg /* set if tpa parameters should be handled, TPA must be disable before */; 1214 u8 update_tpa_en_flg /* set if tpa enable changes */; 1215 u8 update_tx_switching_en_flg /* set if tx switching en flag should be handled */; 1216 u8 tx_switching_en /* tx switching en value */; 1217 u8 update_anti_spoofing_en_flg /* set if anti spoofing flag should be handled */; 1218 u8 anti_spoofing_en /* Anti-spoofing verification en value */; 1219 u8 update_handle_ptp_pkts /* set if handle_ptp_pkts should be handled. */; 1220 u8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */; 1221 u8 update_default_vlan_en_flg /* If set, the default Vlan enable flag is updated */; 1222 u8 default_vlan_en /* If set, the default Vlan value is forced by the FW */; 1223 u8 update_default_vlan_flg /* If set, the default Vlan value is updated */; 1224 __le16 default_vlan /* Default Vlan value to be forced by FW */; 1225 u8 update_accept_any_vlan_flg /* set if accept_any_vlan should be handled */; 1226 u8 accept_any_vlan /* accept_any_vlan updated value */; 1227 u8 silent_vlan_removal_en /* Set to remove vlan silently, update_inner_vlan_removal_en_flg must be enabled as well. If Rx is in noSgl mode send rx_queue_update_ramrod_data */; 1228 u8 update_mtu_flg /* If set, MTU will be updated. Vport must be not active. */; 1229 __le16 mtu /* New MTU value. Used if update_mtu_flg are set */; 1230 u8 update_ctl_frame_checks_en_flg /* If set, ctl_frame_mac_check_en and ctl_frame_ethtype_check_en will be updated */; 1231 u8 ctl_frame_mac_check_en /* If set, Contorl frames will be filtered according to MAC check. */; 1232 u8 ctl_frame_ethtype_check_en /* If set, Contorl frames will be filtered according to ethtype check. */; 1233 u8 reserved[15]; 1234 }; 1235 1236 struct vport_update_ramrod_mcast 1237 { 1238 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS] /* multicast bins */; 1239 }; 1240 1241 /* 1242 * Ramrod data for vport update ramrod 1243 */ 1244 struct vport_update_ramrod_data 1245 { 1246 struct vport_update_ramrod_data_cmn common /* Common data for all vport update ramrods */; 1247 struct eth_vport_rx_mode rx_mode /* vport rx mode bitmap */; 1248 struct eth_vport_tx_mode tx_mode /* vport tx mode bitmap */; 1249 struct eth_vport_tpa_param tpa_param /* TPA configuration parameters */; 1250 struct vport_update_ramrod_mcast approx_mcast; 1251 struct eth_vport_rss_config rss_config /* rss config data */; 1252 }; 1253 1254 1255 1256 1257 1258 1259 struct E4XstormEthConnAgCtxDqExtLdPart 1260 { 1261 u8 reserved0 /* cdu_validation */; 1262 u8 eth_state /* state */; 1263 u8 flags0; 1264 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1265 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 1266 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 1267 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 1268 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 1269 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 1270 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1271 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 1272 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 /* bit4 */ 1273 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 1274 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 /* cf_array_active */ 1275 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 1276 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 /* bit6 */ 1277 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 1278 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 /* bit7 */ 1279 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 1280 u8 flags1; 1281 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 /* bit8 */ 1282 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 1283 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 /* bit9 */ 1284 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 1285 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1 /* bit10 */ 1286 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2 1287 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */ 1288 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 1289 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 /* bit12 */ 1290 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 1291 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1 /* bit13 */ 1292 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5 1293 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 1294 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6 1295 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 1296 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7 1297 u8 flags2; 1298 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */ 1299 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0 1300 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */ 1301 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2 1302 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */ 1303 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4 1304 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */ 1305 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6 1306 u8 flags3; 1307 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3 /* cf4 */ 1308 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0 1309 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3 /* cf5 */ 1310 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2 1311 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3 /* cf6 */ 1312 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4 1313 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3 /* cf7 */ 1314 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6 1315 u8 flags4; 1316 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */ 1317 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0 1318 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */ 1319 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2 1320 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */ 1321 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4 1322 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */ 1323 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6 1324 u8 flags5; 1325 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */ 1326 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0 1327 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */ 1328 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2 1329 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3 /* cf14 */ 1330 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4 1331 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */ 1332 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6 1333 u8 flags6; 1334 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 1335 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0 1336 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 1337 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2 1338 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3 /* cf18 */ 1339 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4 1340 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3 /* cf19 */ 1341 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6 1342 u8 flags7; 1343 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3 /* cf20 */ 1344 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0 1345 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3 /* cf21 */ 1346 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2 1347 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */ 1348 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 1349 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */ 1350 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 1351 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */ 1352 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 1353 u8 flags8; 1354 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */ 1355 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 1356 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */ 1357 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 1358 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 /* cf4en */ 1359 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 1360 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 /* cf5en */ 1361 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 1362 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 /* cf6en */ 1363 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 1364 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1 /* cf7en */ 1365 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5 1366 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */ 1367 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 1368 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */ 1369 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 1370 u8 flags9; 1371 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */ 1372 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 1373 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */ 1374 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 1375 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */ 1376 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 1377 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */ 1378 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 1379 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 /* cf14en */ 1380 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 1381 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */ 1382 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 1383 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 1384 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6 1385 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 1386 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7 1387 u8 flags10; 1388 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1 /* cf18en */ 1389 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0 1390 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 1391 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1 1392 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 1393 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2 1394 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1 /* cf21en */ 1395 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3 1396 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1397 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 1398 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 1399 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5 1400 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1 /* rule0en */ 1401 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6 1402 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1 /* rule1en */ 1403 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7 1404 u8 flags11; 1405 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1 /* rule2en */ 1406 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0 1407 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1 /* rule3en */ 1408 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1 1409 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 1410 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2 1411 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */ 1412 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 1413 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */ 1414 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 1415 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 /* rule7en */ 1416 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 1417 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */ 1418 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 1419 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */ 1420 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 1421 u8 flags12; 1422 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 /* rule10en */ 1423 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 1424 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */ 1425 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 1426 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */ 1427 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 1428 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */ 1429 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 1430 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 /* rule14en */ 1431 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 1432 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */ 1433 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 1434 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 /* rule16en */ 1435 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 1436 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 /* rule17en */ 1437 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 1438 u8 flags13; 1439 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */ 1440 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 1441 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */ 1442 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 1443 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */ 1444 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 1445 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */ 1446 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 1447 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */ 1448 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 1449 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */ 1450 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 1451 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */ 1452 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 1453 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */ 1454 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 1455 u8 flags14; 1456 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 1457 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0 1458 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 1459 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1 1460 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 1461 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2 1462 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 1463 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3 1464 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 1465 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4 1466 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1467 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 1468 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3 /* cf23 */ 1469 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6 1470 u8 edpm_event_id /* byte2 */; 1471 __le16 physical_q0 /* physical_q0 */; 1472 __le16 e5_reserved1 /* physical_q1 */; 1473 __le16 edpm_num_bds /* physical_q2 */; 1474 __le16 tx_bd_cons /* word3 */; 1475 __le16 tx_bd_prod /* word4 */; 1476 __le16 tx_class /* word5 */; 1477 __le16 conn_dpi /* conn_dpi */; 1478 u8 byte3 /* byte3 */; 1479 u8 byte4 /* byte4 */; 1480 u8 byte5 /* byte5 */; 1481 u8 byte6 /* byte6 */; 1482 __le32 reg0 /* reg0 */; 1483 __le32 reg1 /* reg1 */; 1484 __le32 reg2 /* reg2 */; 1485 __le32 reg3 /* reg3 */; 1486 __le32 reg4 /* reg4 */; 1487 }; 1488 1489 1490 struct e4_mstorm_eth_conn_ag_ctx 1491 { 1492 u8 byte0 /* cdu_validation */; 1493 u8 byte1 /* state */; 1494 u8 flags0; 1495 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1496 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1497 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1498 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 1499 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1500 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2 1501 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1502 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4 1503 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1504 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 1505 u8 flags1; 1506 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1507 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0 1508 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1509 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1 1510 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1511 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 1512 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1513 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 1514 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1515 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 1516 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1517 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 1518 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1519 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 1520 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1521 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 1522 __le16 word0 /* word0 */; 1523 __le16 word1 /* word1 */; 1524 __le32 reg0 /* reg0 */; 1525 __le32 reg1 /* reg1 */; 1526 }; 1527 1528 1529 1530 1531 1532 struct e4_xstorm_eth_hw_conn_ag_ctx 1533 { 1534 u8 reserved0 /* cdu_validation */; 1535 u8 eth_state /* state */; 1536 u8 flags0; 1537 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1538 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1539 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 1540 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1 1541 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 1542 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2 1543 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1544 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 1545 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 1546 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4 1547 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 1548 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5 1549 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 1550 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6 1551 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 1552 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7 1553 u8 flags1; 1554 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 1555 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0 1556 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 1557 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1 1558 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 1559 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2 1560 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1561 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3 1562 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 1563 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4 1564 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 1565 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5 1566 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 1567 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 1568 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 1569 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 1570 u8 flags2; 1571 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1572 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0 1573 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1574 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2 1575 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1576 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4 1577 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1578 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6 1579 u8 flags3; 1580 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1581 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0 1582 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1583 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2 1584 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1585 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4 1586 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1587 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6 1588 u8 flags4; 1589 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1590 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0 1591 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1592 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2 1593 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1594 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4 1595 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1596 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6 1597 u8 flags5; 1598 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1599 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0 1600 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1601 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2 1602 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 1603 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4 1604 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1605 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6 1606 u8 flags6; 1607 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 1608 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 1609 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 1610 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 1611 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 1612 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4 1613 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 1614 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 1615 u8 flags7; 1616 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 1617 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 1618 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 1619 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2 1620 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1621 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1622 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1623 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6 1624 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1625 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7 1626 u8 flags8; 1627 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1628 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0 1629 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1630 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1 1631 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1632 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2 1633 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1634 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3 1635 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1636 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4 1637 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1638 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5 1639 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1640 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6 1641 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1642 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7 1643 u8 flags9; 1644 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1645 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0 1646 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1647 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1 1648 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1649 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2 1650 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1651 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3 1652 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 1653 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4 1654 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1655 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5 1656 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 1657 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 1658 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 1659 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 1660 u8 flags10; 1661 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 1662 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 1663 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 1664 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 1665 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 1666 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 1667 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 1668 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3 1669 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1670 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1671 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 1672 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 1673 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 1674 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6 1675 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 1676 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7 1677 u8 flags11; 1678 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 1679 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0 1680 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 1681 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1 1682 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 1683 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 1684 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1685 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3 1686 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1687 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4 1688 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1689 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5 1690 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1691 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1692 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1693 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7 1694 u8 flags12; 1695 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 1696 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0 1697 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1698 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1 1699 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1700 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1701 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1702 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1703 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 1704 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4 1705 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 1706 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5 1707 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 1708 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6 1709 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 1710 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7 1711 u8 flags13; 1712 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 1713 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0 1714 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 1715 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1 1716 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 1717 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 1718 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 1719 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 1720 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1721 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1722 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 1723 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 1724 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1725 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1726 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1727 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1728 u8 flags14; 1729 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 1730 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 1731 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 1732 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 1733 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 1734 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 1735 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 1736 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 1737 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 1738 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 1739 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1740 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 1741 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 1742 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 1743 u8 edpm_event_id /* byte2 */; 1744 __le16 physical_q0 /* physical_q0 */; 1745 __le16 e5_reserved1 /* physical_q1 */; 1746 __le16 edpm_num_bds /* physical_q2 */; 1747 __le16 tx_bd_cons /* word3 */; 1748 __le16 tx_bd_prod /* word4 */; 1749 __le16 tx_class /* word5 */; 1750 __le16 conn_dpi /* conn_dpi */; 1751 }; 1752 1753 1754 1755 struct E5XstormEthConnAgCtxDqExtLdPart 1756 { 1757 u8 reserved0 /* cdu_validation */; 1758 u8 state_and_core_id /* state_and_core_id */; 1759 u8 flags0; 1760 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1761 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 1762 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 1763 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 1764 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 1765 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 1766 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1767 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 1768 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 /* bit4 */ 1769 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 1770 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 /* cf_array_active */ 1771 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 1772 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 /* bit6 */ 1773 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 1774 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 /* bit7 */ 1775 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 1776 u8 flags1; 1777 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 /* bit8 */ 1778 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 1779 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 /* bit9 */ 1780 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 1781 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1 /* bit10 */ 1782 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2 1783 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */ 1784 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 1785 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 /* bit12 */ 1786 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 1787 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1 /* bit13 */ 1788 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5 1789 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 1790 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6 1791 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 1792 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7 1793 u8 flags2; 1794 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */ 1795 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0 1796 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */ 1797 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2 1798 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */ 1799 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4 1800 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */ 1801 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6 1802 u8 flags3; 1803 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3 /* cf4 */ 1804 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0 1805 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3 /* cf5 */ 1806 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2 1807 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3 /* cf6 */ 1808 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4 1809 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3 /* cf7 */ 1810 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6 1811 u8 flags4; 1812 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */ 1813 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0 1814 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */ 1815 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2 1816 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */ 1817 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4 1818 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */ 1819 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6 1820 u8 flags5; 1821 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */ 1822 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0 1823 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */ 1824 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2 1825 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3 /* cf14 */ 1826 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4 1827 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */ 1828 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6 1829 u8 flags6; 1830 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 1831 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0 1832 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 1833 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2 1834 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3 /* cf18 */ 1835 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4 1836 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3 /* cf19 */ 1837 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6 1838 u8 flags7; 1839 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3 /* cf20 */ 1840 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0 1841 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3 /* cf21 */ 1842 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2 1843 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */ 1844 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 1845 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */ 1846 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 1847 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */ 1848 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 1849 u8 flags8; 1850 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */ 1851 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 1852 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */ 1853 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 1854 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 /* cf4en */ 1855 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 1856 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 /* cf5en */ 1857 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 1858 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 /* cf6en */ 1859 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 1860 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1 /* cf7en */ 1861 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5 1862 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */ 1863 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 1864 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */ 1865 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 1866 u8 flags9; 1867 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */ 1868 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 1869 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */ 1870 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 1871 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */ 1872 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 1873 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */ 1874 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 1875 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 /* cf14en */ 1876 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 1877 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */ 1878 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 1879 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 1880 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6 1881 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 1882 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7 1883 u8 flags10; 1884 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1 /* cf18en */ 1885 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0 1886 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 1887 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1 1888 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 1889 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2 1890 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1 /* cf21en */ 1891 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3 1892 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1893 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 1894 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 1895 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5 1896 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1 /* rule0en */ 1897 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6 1898 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1 /* rule1en */ 1899 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7 1900 u8 flags11; 1901 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1 /* rule2en */ 1902 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0 1903 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1 /* rule3en */ 1904 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1 1905 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 1906 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2 1907 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */ 1908 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 1909 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */ 1910 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 1911 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 /* rule7en */ 1912 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 1913 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */ 1914 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 1915 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */ 1916 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 1917 u8 flags12; 1918 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 /* rule10en */ 1919 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 1920 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */ 1921 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 1922 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */ 1923 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 1924 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */ 1925 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 1926 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 /* rule14en */ 1927 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 1928 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */ 1929 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 1930 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 /* rule16en */ 1931 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 1932 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 /* rule17en */ 1933 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 1934 u8 flags13; 1935 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */ 1936 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 1937 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */ 1938 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 1939 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */ 1940 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 1941 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */ 1942 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 1943 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */ 1944 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 1945 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */ 1946 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 1947 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */ 1948 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 1949 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */ 1950 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 1951 u8 flags14; 1952 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 1953 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0 1954 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 1955 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1 1956 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 1957 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2 1958 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 1959 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3 1960 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 1961 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4 1962 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1963 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 1964 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3 /* cf23 */ 1965 #define E5XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6 1966 u8 byte2 /* byte2 */; 1967 __le16 physical_q0 /* physical_q0 */; 1968 __le16 tx_l2_edpm_usg_cnt /* physical_q1 */; 1969 __le16 edpm_num_bds /* physical_q2 */; 1970 __le16 tx_bd_cons /* word3 */; 1971 __le16 tx_bd_prod /* word4 */; 1972 __le16 tx_class /* word5 */; 1973 __le16 conn_dpi /* conn_dpi */; 1974 u8 byte3 /* byte3 */; 1975 u8 byte4 /* byte4 */; 1976 u8 byte5 /* byte5 */; 1977 u8 byte6 /* byte6 */; 1978 __le32 reg0 /* reg0 */; 1979 __le32 reg1 /* reg1 */; 1980 __le32 reg2 /* reg2 */; 1981 __le32 reg3 /* reg3 */; 1982 __le32 reg4 /* reg4 */; 1983 }; 1984 1985 1986 struct e5_mstorm_eth_conn_ag_ctx 1987 { 1988 u8 byte0 /* cdu_validation */; 1989 u8 byte1 /* state_and_core_id */; 1990 u8 flags0; 1991 #define E5_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1992 #define E5_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1993 #define E5_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1994 #define E5_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 1995 #define E5_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1996 #define E5_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2 1997 #define E5_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1998 #define E5_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4 1999 #define E5_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2000 #define E5_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 2001 u8 flags1; 2002 #define E5_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2003 #define E5_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0 2004 #define E5_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2005 #define E5_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1 2006 #define E5_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2007 #define E5_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 2008 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2009 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 2010 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2011 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 2012 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2013 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 2014 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2015 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 2016 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2017 #define E5_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 2018 __le16 word0 /* word0 */; 2019 __le16 word1 /* word1 */; 2020 __le32 reg0 /* reg0 */; 2021 __le32 reg1 /* reg1 */; 2022 }; 2023 2024 2025 struct e5_tstorm_eth_conn_ag_ctx 2026 { 2027 u8 byte0 /* cdu_validation */; 2028 u8 byte1 /* state_and_core_id */; 2029 u8 flags0; 2030 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2031 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 2032 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2033 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 2034 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 2035 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 2036 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 2037 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 2038 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 2039 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 2040 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 2041 #define E5_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 2042 #define E5_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2043 #define E5_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 2044 u8 flags1; 2045 #define E5_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2046 #define E5_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 2047 #define E5_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2048 #define E5_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 2049 #define E5_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2050 #define E5_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 2051 #define E5_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2052 #define E5_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 2053 u8 flags2; 2054 #define E5_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2055 #define E5_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 2056 #define E5_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2057 #define E5_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 2058 #define E5_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 2059 #define E5_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 2060 #define E5_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2061 #define E5_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 2062 u8 flags3; 2063 #define E5_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2064 #define E5_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 2065 #define E5_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2066 #define E5_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 2067 #define E5_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2068 #define E5_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 2069 #define E5_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2070 #define E5_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 2071 #define E5_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2072 #define E5_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 2073 #define E5_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2074 #define E5_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 2075 u8 flags4; 2076 #define E5_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2077 #define E5_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 2078 #define E5_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2079 #define E5_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 2080 #define E5_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2081 #define E5_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 2082 #define E5_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 2083 #define E5_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 2084 #define E5_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2085 #define E5_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 2086 #define E5_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2087 #define E5_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 2088 #define E5_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2089 #define E5_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 2090 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2091 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 2092 u8 flags5; 2093 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2094 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 2095 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2096 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 2097 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2098 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 2099 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2100 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 2101 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2102 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 2103 #define E5_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */ 2104 #define E5_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 2105 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2106 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 2107 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 2108 #define E5_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 2109 u8 flags6; 2110 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 2111 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2112 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 2113 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2114 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 2115 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2116 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 2117 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 2118 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 2119 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 2120 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 2121 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 2122 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 2123 #define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 2124 u8 byte2 /* byte2 */; 2125 __le16 rx_bd_cons /* word0 */; 2126 __le32 reg0 /* reg0 */; 2127 __le32 reg1 /* reg1 */; 2128 __le32 reg2 /* reg2 */; 2129 __le32 reg3 /* reg3 */; 2130 __le32 reg4 /* reg4 */; 2131 __le32 reg5 /* reg5 */; 2132 __le32 reg6 /* reg6 */; 2133 __le32 reg7 /* reg7 */; 2134 __le32 reg8 /* reg8 */; 2135 u8 byte3 /* byte3 */; 2136 u8 byte4 /* byte4 */; 2137 u8 byte5 /* byte5 */; 2138 u8 e4_reserved8 /* byte6 */; 2139 __le16 rx_bd_prod /* word1 */; 2140 __le16 word2 /* conn_dpi */; 2141 __le32 reg9 /* reg9 */; 2142 __le16 word3 /* word3 */; 2143 __le16 e4_reserved9 /* word4 */; 2144 }; 2145 2146 2147 struct e5_ustorm_eth_conn_ag_ctx 2148 { 2149 u8 byte0 /* cdu_validation */; 2150 u8 byte1 /* state_and_core_id */; 2151 u8 flags0; 2152 #define E5_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2153 #define E5_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 2154 #define E5_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2155 #define E5_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 2156 #define E5_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 /* timer0cf */ 2157 #define E5_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2 2158 #define E5_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 /* timer1cf */ 2159 #define E5_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4 2160 #define E5_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2161 #define E5_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 2162 u8 flags1; 2163 #define E5_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2164 #define E5_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 2165 #define E5_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 /* cf4 */ 2166 #define E5_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 2167 #define E5_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 /* cf5 */ 2168 #define E5_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 2169 #define E5_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf6 */ 2170 #define E5_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 2171 u8 flags2; 2172 #define E5_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf0en */ 2173 #define E5_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 2174 #define E5_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 2175 #define E5_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1 2176 #define E5_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2177 #define E5_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 2178 #define E5_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2179 #define E5_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3 2180 #define E5_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 /* cf4en */ 2181 #define E5_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4 2182 #define E5_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 /* cf5en */ 2183 #define E5_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5 2184 #define E5_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf6en */ 2185 #define E5_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6 2186 #define E5_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2187 #define E5_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 2188 u8 flags3; 2189 #define E5_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2190 #define E5_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 2191 #define E5_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2192 #define E5_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 2193 #define E5_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2194 #define E5_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 2195 #define E5_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2196 #define E5_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 2197 #define E5_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2198 #define E5_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 2199 #define E5_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2200 #define E5_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 2201 #define E5_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2202 #define E5_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 2203 #define E5_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 2204 #define E5_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 2205 u8 flags4; 2206 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 2207 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2208 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 2209 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2210 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 2211 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2212 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 2213 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 2214 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 2215 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 2216 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 2217 #define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 2218 u8 byte2 /* byte2 */; 2219 __le16 word0 /* conn_dpi */; 2220 __le16 tx_bd_cons /* word1 */; 2221 __le32 reg0 /* reg0 */; 2222 __le32 reg1 /* reg1 */; 2223 __le32 reg2 /* reg2 */; 2224 __le32 tx_int_coallecing_timeset /* reg3 */; 2225 __le16 tx_drv_bd_cons /* word2 */; 2226 __le16 rx_drv_cqe_cons /* word3 */; 2227 }; 2228 2229 2230 struct e5_xstorm_eth_conn_ag_ctx 2231 { 2232 u8 reserved0 /* cdu_validation */; 2233 u8 state_and_core_id /* state_and_core_id */; 2234 u8 flags0; 2235 #define E5_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2236 #define E5_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2237 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2238 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1 2239 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2240 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2 2241 #define E5_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2242 #define E5_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2243 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2244 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4 2245 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2246 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5 2247 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2248 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6 2249 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2250 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7 2251 u8 flags1; 2252 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2253 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0 2254 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2255 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1 2256 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 2257 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2 2258 #define E5_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2259 #define E5_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3 2260 #define E5_XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 2261 #define E5_XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4 2262 #define E5_XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 2263 #define E5_XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5 2264 #define E5_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 2265 #define E5_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 2266 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 2267 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 2268 u8 flags2; 2269 #define E5_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2270 #define E5_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 2271 #define E5_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2272 #define E5_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 2273 #define E5_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2274 #define E5_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 2275 #define E5_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2276 #define E5_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 2277 u8 flags3; 2278 #define E5_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2279 #define E5_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 2280 #define E5_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2281 #define E5_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 2282 #define E5_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2283 #define E5_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 2284 #define E5_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 2285 #define E5_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 2286 u8 flags4; 2287 #define E5_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2288 #define E5_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 2289 #define E5_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2290 #define E5_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 2291 #define E5_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2292 #define E5_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 2293 #define E5_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2294 #define E5_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 2295 u8 flags5; 2296 #define E5_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2297 #define E5_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 2298 #define E5_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2299 #define E5_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2 2300 #define E5_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 2301 #define E5_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4 2302 #define E5_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2303 #define E5_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6 2304 u8 flags6; 2305 #define E5_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 2306 #define E5_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 2307 #define E5_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 2308 #define E5_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 2309 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 2310 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4 2311 #define E5_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 2312 #define E5_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 2313 u8 flags7; 2314 #define E5_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 2315 #define E5_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 2316 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 2317 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2 2318 #define E5_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2319 #define E5_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2320 #define E5_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2321 #define E5_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6 2322 #define E5_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2323 #define E5_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7 2324 u8 flags8; 2325 #define E5_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2326 #define E5_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0 2327 #define E5_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2328 #define E5_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1 2329 #define E5_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2330 #define E5_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2 2331 #define E5_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2332 #define E5_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3 2333 #define E5_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2334 #define E5_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4 2335 #define E5_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 2336 #define E5_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5 2337 #define E5_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2338 #define E5_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6 2339 #define E5_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2340 #define E5_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 2341 u8 flags9; 2342 #define E5_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2343 #define E5_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 2344 #define E5_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2345 #define E5_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 2346 #define E5_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2347 #define E5_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 2348 #define E5_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2349 #define E5_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 2350 #define E5_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 2351 #define E5_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 2352 #define E5_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2353 #define E5_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 2354 #define E5_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 2355 #define E5_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 2356 #define E5_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 2357 #define E5_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 2358 u8 flags10; 2359 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 2360 #define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 2361 #define E5_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 2362 #define E5_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 2363 #define E5_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 2364 #define E5_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 2365 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 2366 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 2367 #define E5_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2368 #define E5_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2369 #define E5_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 2370 #define E5_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 2371 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 2372 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 2373 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 2374 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 2375 u8 flags11; 2376 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 2377 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 2378 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 2379 #define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1 2380 #define E5_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 2381 #define E5_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 2382 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2383 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3 2384 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2385 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4 2386 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2387 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5 2388 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2389 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2390 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2391 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7 2392 u8 flags12; 2393 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 2394 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0 2395 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2396 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1 2397 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2398 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2399 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2400 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2401 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2402 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4 2403 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2404 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5 2405 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2406 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6 2407 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2408 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7 2409 u8 flags13; 2410 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2411 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0 2412 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2413 #define E5_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1 2414 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2415 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2416 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2417 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2418 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2419 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2420 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2421 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2422 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2423 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2424 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2425 #define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2426 u8 flags14; 2427 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 2428 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 2429 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 2430 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 2431 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 2432 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 2433 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 2434 #define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 2435 #define E5_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 2436 #define E5_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 2437 #define E5_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2438 #define E5_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2439 #define E5_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 2440 #define E5_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 2441 u8 byte2 /* byte2 */; 2442 __le16 physical_q0 /* physical_q0 */; 2443 __le16 tx_l2_edpm_usg_cnt /* physical_q1 */; 2444 __le16 edpm_num_bds /* physical_q2 */; 2445 __le16 tx_bd_cons /* word3 */; 2446 __le16 tx_bd_prod /* word4 */; 2447 __le16 tx_class /* word5 */; 2448 __le16 conn_dpi /* conn_dpi */; 2449 u8 byte3 /* byte3 */; 2450 u8 byte4 /* byte4 */; 2451 u8 byte5 /* byte5 */; 2452 u8 byte6 /* byte6 */; 2453 __le32 reg0 /* reg0 */; 2454 __le32 reg1 /* reg1 */; 2455 __le32 reg2 /* reg2 */; 2456 __le32 reg3 /* reg3 */; 2457 __le32 reg4 /* reg4 */; 2458 __le32 reg5 /* cf_array0 */; 2459 __le32 reg6 /* cf_array1 */; 2460 u8 flags15; 2461 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit22 */ 2462 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2463 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit23 */ 2464 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2465 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit24 */ 2466 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2467 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf24 */ 2468 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 2469 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf24en */ 2470 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 2471 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule26en */ 2472 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 2473 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule27en */ 2474 #define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 2475 u8 byte7 /* byte7 */; 2476 __le16 word7 /* word7 */; 2477 __le16 word8 /* word8 */; 2478 __le16 word9 /* word9 */; 2479 __le16 word10 /* word10 */; 2480 __le16 word11 /* word11 */; 2481 __le32 reg7 /* reg7 */; 2482 __le32 reg8 /* reg8 */; 2483 __le32 reg9 /* reg9 */; 2484 u8 byte8 /* byte8 */; 2485 u8 byte9 /* byte9 */; 2486 u8 byte10 /* byte10 */; 2487 u8 byte11 /* byte11 */; 2488 u8 byte12 /* byte12 */; 2489 u8 byte13 /* byte13 */; 2490 u8 byte14 /* byte14 */; 2491 u8 byte15 /* byte15 */; 2492 __le32 reg10 /* reg10 */; 2493 __le32 reg11 /* reg11 */; 2494 __le32 reg12 /* reg12 */; 2495 __le32 reg13 /* reg13 */; 2496 __le32 reg14 /* reg14 */; 2497 __le32 reg15 /* reg15 */; 2498 __le32 reg16 /* reg16 */; 2499 __le32 reg17 /* reg17 */; 2500 __le32 reg18 /* reg18 */; 2501 __le32 reg19 /* reg19 */; 2502 __le16 word12 /* word12 */; 2503 __le16 word13 /* word13 */; 2504 __le16 word14 /* word14 */; 2505 __le16 word15 /* word15 */; 2506 }; 2507 2508 2509 struct e5_xstorm_eth_hw_conn_ag_ctx 2510 { 2511 u8 reserved0 /* cdu_validation */; 2512 u8 state_and_core_id /* state_and_core_id */; 2513 u8 flags0; 2514 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2515 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2516 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2517 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1 2518 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2519 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2 2520 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2521 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2522 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2523 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4 2524 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2525 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5 2526 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2527 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6 2528 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2529 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7 2530 u8 flags1; 2531 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2532 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0 2533 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2534 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1 2535 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 2536 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2 2537 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2538 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3 2539 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 2540 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4 2541 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 2542 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5 2543 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 2544 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 2545 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 2546 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 2547 u8 flags2; 2548 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2549 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0 2550 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2551 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2 2552 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2553 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4 2554 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2555 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6 2556 u8 flags3; 2557 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2558 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0 2559 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2560 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2 2561 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2562 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4 2563 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 2564 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6 2565 u8 flags4; 2566 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2567 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0 2568 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2569 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2 2570 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2571 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4 2572 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2573 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6 2574 u8 flags5; 2575 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2576 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0 2577 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2578 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2 2579 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 2580 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4 2581 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2582 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6 2583 u8 flags6; 2584 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 2585 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 2586 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 2587 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 2588 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 2589 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4 2590 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 2591 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 2592 u8 flags7; 2593 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 2594 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 2595 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 2596 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2 2597 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2598 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2599 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2600 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6 2601 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2602 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7 2603 u8 flags8; 2604 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2605 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0 2606 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2607 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1 2608 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2609 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2 2610 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2611 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3 2612 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2613 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4 2614 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 2615 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5 2616 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2617 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6 2618 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2619 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7 2620 u8 flags9; 2621 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2622 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0 2623 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2624 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1 2625 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2626 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2 2627 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2628 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3 2629 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 2630 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4 2631 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2632 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5 2633 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 2634 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 2635 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 2636 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 2637 u8 flags10; 2638 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 2639 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 2640 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 2641 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 2642 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 2643 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 2644 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 2645 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3 2646 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2647 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2648 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 2649 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 2650 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 2651 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6 2652 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 2653 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7 2654 u8 flags11; 2655 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 2656 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0 2657 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 2658 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1 2659 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 2660 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 2661 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2662 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3 2663 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2664 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4 2665 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2666 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5 2667 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2668 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2669 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2670 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7 2671 u8 flags12; 2672 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 2673 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0 2674 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2675 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1 2676 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2677 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2678 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2679 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2680 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2681 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4 2682 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2683 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5 2684 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2685 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6 2686 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2687 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7 2688 u8 flags13; 2689 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2690 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0 2691 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2692 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1 2693 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2694 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2695 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2696 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2697 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2698 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2699 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2700 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2701 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2702 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2703 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2704 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2705 u8 flags14; 2706 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 2707 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 2708 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 2709 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 2710 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 2711 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 2712 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 2713 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 2714 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 2715 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 2716 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2717 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2718 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 2719 #define E5_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 2720 u8 byte2 /* byte2 */; 2721 __le16 physical_q0 /* physical_q0 */; 2722 __le16 tx_l2_edpm_usg_cnt /* physical_q1 */; 2723 __le16 edpm_num_bds /* physical_q2 */; 2724 __le16 tx_bd_cons /* word3 */; 2725 __le16 tx_bd_prod /* word4 */; 2726 __le16 tx_class /* word5 */; 2727 __le16 conn_dpi /* conn_dpi */; 2728 }; 2729 2730 2731 struct e5_ystorm_eth_conn_ag_ctx 2732 { 2733 u8 byte0 /* cdu_validation */; 2734 u8 state_and_core_id /* state_and_core_id */; 2735 u8 flags0; 2736 #define E5_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2737 #define E5_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 2738 #define E5_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2739 #define E5_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 2740 #define E5_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */ 2741 #define E5_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2 2742 #define E5_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */ 2743 #define E5_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4 2744 #define E5_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2745 #define E5_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 2746 u8 flags1; 2747 #define E5_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf0en */ 2748 #define E5_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0 2749 #define E5_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 2750 #define E5_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1 2751 #define E5_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2752 #define E5_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 2753 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2754 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 2755 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2756 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 2757 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2758 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 2759 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2760 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 2761 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2762 #define E5_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 2763 u8 tx_q0_int_coallecing_timeset /* byte2 */; 2764 u8 byte3 /* byte3 */; 2765 __le16 word0 /* word0 */; 2766 __le32 terminate_spqe /* reg0 */; 2767 __le32 reg1 /* reg1 */; 2768 __le16 tx_bd_cons_upd /* word1 */; 2769 __le16 word2 /* word2 */; 2770 __le16 word3 /* word3 */; 2771 __le16 word4 /* word4 */; 2772 __le32 reg2 /* reg2 */; 2773 __le32 reg3 /* reg3 */; 2774 }; 2775 2776 2777 /* 2778 * GFT CAM line struct 2779 */ 2780 struct gft_cam_line 2781 { 2782 __le32 camline; 2783 #define GFT_CAM_LINE_VALID_MASK 0x1 /* Indication if the line is valid. */ 2784 #define GFT_CAM_LINE_VALID_SHIFT 0 2785 #define GFT_CAM_LINE_DATA_MASK 0x3FFF /* Data bits, the word that compared with the profile key */ 2786 #define GFT_CAM_LINE_DATA_SHIFT 1 2787 #define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF /* Mask bits, indicate the bits in the data that are Dont-Care */ 2788 #define GFT_CAM_LINE_MASK_BITS_SHIFT 15 2789 #define GFT_CAM_LINE_RESERVED1_MASK 0x7 2790 #define GFT_CAM_LINE_RESERVED1_SHIFT 29 2791 }; 2792 2793 2794 /* 2795 * GFT CAM line struct (for driversim use) 2796 */ 2797 struct gft_cam_line_mapped 2798 { 2799 __le32 camline; 2800 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1 /* Indication if the line is valid. */ 2801 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0 2802 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2803 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1 2804 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2805 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2 2806 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF /* use enum gft_profile_upper_protocol_type (use enum gft_profile_upper_protocol_type) */ 2807 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3 2808 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */ 2809 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7 2810 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF 2811 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11 2812 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2813 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15 2814 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2815 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16 2816 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF /* use enum gft_profile_upper_protocol_type (use enum gft_profile_upper_protocol_type) */ 2817 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17 2818 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */ 2819 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21 2820 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF 2821 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25 2822 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7 2823 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29 2824 }; 2825 2826 2827 union gft_cam_line_union 2828 { 2829 struct gft_cam_line cam_line; 2830 struct gft_cam_line_mapped cam_line_mapped; 2831 }; 2832 2833 2834 /* 2835 * Used in gft_profile_key: Indication for ip version 2836 */ 2837 enum gft_profile_ip_version 2838 { 2839 GFT_PROFILE_IPV4=0, 2840 GFT_PROFILE_IPV6=1, 2841 MAX_GFT_PROFILE_IP_VERSION 2842 }; 2843 2844 2845 /* 2846 * Profile key stucr fot GFT logic in Prs 2847 */ 2848 struct gft_profile_key 2849 { 2850 __le16 profile_key; 2851 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2852 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0 2853 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2854 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1 2855 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF /* use enum gft_profile_upper_protocol_type (use enum gft_profile_upper_protocol_type) */ 2856 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2 2857 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */ 2858 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6 2859 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF 2860 #define GFT_PROFILE_KEY_PF_ID_SHIFT 10 2861 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3 2862 #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14 2863 }; 2864 2865 2866 /* 2867 * Used in gft_profile_key: Indication for tunnel type 2868 */ 2869 enum gft_profile_tunnel_type 2870 { 2871 GFT_PROFILE_NO_TUNNEL=0, 2872 GFT_PROFILE_VXLAN_TUNNEL=1, 2873 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL=2, 2874 GFT_PROFILE_GRE_IP_TUNNEL=3, 2875 GFT_PROFILE_GENEVE_MAC_TUNNEL=4, 2876 GFT_PROFILE_GENEVE_IP_TUNNEL=5, 2877 MAX_GFT_PROFILE_TUNNEL_TYPE 2878 }; 2879 2880 2881 /* 2882 * Used in gft_profile_key: Indication for protocol type 2883 */ 2884 enum gft_profile_upper_protocol_type 2885 { 2886 GFT_PROFILE_ROCE_PROTOCOL=0, 2887 GFT_PROFILE_RROCE_PROTOCOL=1, 2888 GFT_PROFILE_FCOE_PROTOCOL=2, 2889 GFT_PROFILE_ICMP_PROTOCOL=3, 2890 GFT_PROFILE_ARP_PROTOCOL=4, 2891 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER=5, 2892 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER=6, 2893 GFT_PROFILE_TCP_PROTOCOL=7, 2894 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER=8, 2895 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER=9, 2896 GFT_PROFILE_UDP_PROTOCOL=10, 2897 GFT_PROFILE_USER_IP_1_INNER=11, 2898 GFT_PROFILE_USER_IP_2_OUTER=12, 2899 GFT_PROFILE_USER_ETH_1_INNER=13, 2900 GFT_PROFILE_USER_ETH_2_OUTER=14, 2901 GFT_PROFILE_RAW=15, 2902 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE 2903 }; 2904 2905 2906 /* 2907 * GFT RAM line struct 2908 */ 2909 struct gft_ram_line 2910 { 2911 __le32 lo; 2912 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3 /* (use enum gft_vlan_select) */ 2913 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0 2914 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1 2915 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2 2916 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1 2917 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3 2918 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1 2919 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4 2920 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1 2921 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5 2922 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1 2923 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6 2924 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1 2925 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7 2926 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1 2927 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8 2928 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1 2929 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9 2930 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1 2931 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10 2932 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1 2933 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11 2934 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1 2935 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12 2936 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1 2937 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13 2938 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1 2939 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14 2940 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1 2941 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15 2942 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1 2943 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16 2944 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1 2945 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17 2946 #define GFT_RAM_LINE_TTL_MASK 0x1 2947 #define GFT_RAM_LINE_TTL_SHIFT 18 2948 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1 2949 #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19 2950 #define GFT_RAM_LINE_RESERVED0_MASK 0x1 2951 #define GFT_RAM_LINE_RESERVED0_SHIFT 20 2952 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1 2953 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21 2954 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1 2955 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22 2956 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1 2957 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23 2958 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1 2959 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24 2960 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1 2961 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25 2962 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1 2963 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26 2964 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1 2965 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27 2966 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1 2967 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28 2968 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1 2969 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29 2970 #define GFT_RAM_LINE_DST_PORT_MASK 0x1 2971 #define GFT_RAM_LINE_DST_PORT_SHIFT 30 2972 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1 2973 #define GFT_RAM_LINE_SRC_PORT_SHIFT 31 2974 __le32 hi; 2975 #define GFT_RAM_LINE_DSCP_MASK 0x1 2976 #define GFT_RAM_LINE_DSCP_SHIFT 0 2977 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1 2978 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1 2979 #define GFT_RAM_LINE_DST_IP_MASK 0x1 2980 #define GFT_RAM_LINE_DST_IP_SHIFT 2 2981 #define GFT_RAM_LINE_SRC_IP_MASK 0x1 2982 #define GFT_RAM_LINE_SRC_IP_SHIFT 3 2983 #define GFT_RAM_LINE_PRIORITY_MASK 0x1 2984 #define GFT_RAM_LINE_PRIORITY_SHIFT 4 2985 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1 2986 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5 2987 #define GFT_RAM_LINE_VLAN_MASK 0x1 2988 #define GFT_RAM_LINE_VLAN_SHIFT 6 2989 #define GFT_RAM_LINE_DST_MAC_MASK 0x1 2990 #define GFT_RAM_LINE_DST_MAC_SHIFT 7 2991 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1 2992 #define GFT_RAM_LINE_SRC_MAC_SHIFT 8 2993 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1 2994 #define GFT_RAM_LINE_TENANT_ID_SHIFT 9 2995 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF 2996 #define GFT_RAM_LINE_RESERVED1_SHIFT 10 2997 }; 2998 2999 3000 /* 3001 * Used in the first 2 bits for gft_ram_line: Indication for vlan mask 3002 */ 3003 enum gft_vlan_select 3004 { 3005 INNER_PROVIDER_VLAN=0, 3006 INNER_VLAN=1, 3007 OUTER_PROVIDER_VLAN=2, 3008 OUTER_VLAN=3, 3009 MAX_GFT_VLAN_SELECT 3010 }; 3011 3012 #endif /* __ECORE_HSI_ETH__ */ 3013