1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * Definitions of T4/T5/T6 work request and CPL5 commands and status codes
14 *
15 * Copyright (C) 2008-2019 Chelsio Communications. All rights reserved.
16 *
17 * Written by Dimitris Michailidis (dm@chelsio.com)
18 *
19 * This program is distributed in the hope that it will be useful, but WITHOUT
20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
22 * release for licensing terms and conditions.
23 */
24
25 #ifndef T4_MSG_H
26 #define T4_MSG_H
27
28 #if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
29 # include <asm/byteorder.h>
30 #endif
31
32 enum {
33 CPL_PASS_OPEN_REQ = 0x1,
34 CPL_PASS_ACCEPT_RPL = 0x2,
35 CPL_ACT_OPEN_REQ = 0x3,
36 CPL_SET_TCB = 0x4,
37 CPL_SET_TCB_FIELD = 0x5,
38 CPL_GET_TCB = 0x6,
39 CPL_CLOSE_CON_REQ = 0x8,
40 CPL_CLOSE_LISTSRV_REQ = 0x9,
41 CPL_ABORT_REQ = 0xA,
42 CPL_ABORT_RPL = 0xB,
43 CPL_TX_DATA = 0xC,
44 CPL_RX_DATA_ACK = 0xD,
45 CPL_TX_PKT = 0xE,
46 CPL_RTE_DELETE_REQ = 0xF,
47 CPL_RTE_WRITE_REQ = 0x10,
48 CPL_RTE_READ_REQ = 0x11,
49 CPL_L2T_WRITE_REQ = 0x12,
50 CPL_L2T_READ_REQ = 0x13,
51 CPL_SMT_WRITE_REQ = 0x14,
52 CPL_SMT_READ_REQ = 0x15,
53 CPL_TAG_WRITE_REQ = 0x16,
54 CPL_BARRIER = 0x18,
55 CPL_TID_RELEASE = 0x1A,
56 CPL_TAG_READ_REQ = 0x1B,
57 CPL_SRQ_TABLE_REQ = 0x1C,
58 CPL_TX_PKT_FSO = 0x1E,
59 CPL_TX_DATA_ISO = 0x1F,
60
61 CPL_CLOSE_LISTSRV_RPL = 0x20,
62 CPL_ERROR = 0x21,
63 CPL_GET_TCB_RPL = 0x22,
64 CPL_L2T_WRITE_RPL = 0x23,
65 CPL_PASS_OPEN_RPL = 0x24,
66 CPL_ACT_OPEN_RPL = 0x25,
67 CPL_PEER_CLOSE = 0x26,
68 CPL_RTE_DELETE_RPL = 0x27,
69 CPL_RTE_WRITE_RPL = 0x28,
70 CPL_RX_URG_PKT = 0x29,
71 CPL_TAG_WRITE_RPL = 0x2A,
72 CPL_ABORT_REQ_RSS = 0x2B,
73 CPL_RX_URG_NOTIFY = 0x2C,
74 CPL_ABORT_RPL_RSS = 0x2D,
75 CPL_SMT_WRITE_RPL = 0x2E,
76 CPL_TX_DATA_ACK = 0x2F,
77
78 CPL_RX_PHYS_ADDR = 0x30,
79 CPL_PCMD_READ_RPL = 0x31,
80 CPL_CLOSE_CON_RPL = 0x32,
81 CPL_ISCSI_HDR = 0x33,
82 CPL_L2T_READ_RPL = 0x34,
83 CPL_RDMA_CQE = 0x35,
84 CPL_RDMA_CQE_READ_RSP = 0x36,
85 CPL_RDMA_CQE_ERR = 0x37,
86 CPL_RTE_READ_RPL = 0x38,
87 CPL_RX_DATA = 0x39,
88 CPL_SET_TCB_RPL = 0x3A,
89 CPL_RX_PKT = 0x3B,
90 CPL_TAG_READ_RPL = 0x3C,
91 CPL_HIT_NOTIFY = 0x3D,
92 CPL_PKT_NOTIFY = 0x3E,
93 CPL_RX_DDP_COMPLETE = 0x3F,
94
95 CPL_ACT_ESTABLISH = 0x40,
96 CPL_PASS_ESTABLISH = 0x41,
97 CPL_RX_DATA_DDP = 0x42,
98 CPL_SMT_READ_RPL = 0x43,
99 CPL_PASS_ACCEPT_REQ = 0x44,
100 CPL_RX_ISCSI_CMP = 0x45,
101 CPL_RX_FCOE_DDP = 0x46,
102 CPL_FCOE_HDR = 0x47,
103 CPL_T5_TRACE_PKT = 0x48,
104 CPL_RX_ISCSI_DDP = 0x49,
105 CPL_RX_FCOE_DIF = 0x4A,
106 CPL_RX_DATA_DIF = 0x4B,
107 CPL_ERR_NOTIFY = 0x4D,
108 CPL_RX_TLS_CMP = 0x4E,
109
110 CPL_RDMA_READ_REQ = 0x60,
111 CPL_RX_ISCSI_DIF = 0x60,
112
113 CPL_SET_LE_REQ = 0x80,
114 CPL_PASS_OPEN_REQ6 = 0x81,
115 CPL_ACT_OPEN_REQ6 = 0x83,
116 CPL_TX_TLS_PDU = 0x88,
117 CPL_TX_TLS_SFO = 0x89,
118
119 CPL_TX_SEC_PDU = 0x8A,
120 CPL_TX_TLS_ACK = 0x8B,
121
122 CPL_RDMA_TERMINATE = 0xA2,
123 CPL_RDMA_WRITE = 0xA4,
124 CPL_SGE_EGR_UPDATE = 0xA5,
125 CPL_SET_LE_RPL = 0xA6,
126 CPL_FW2_MSG = 0xA7,
127 CPL_FW2_PLD = 0xA8,
128 CPL_T5_RDMA_READ_REQ = 0xA9,
129 CPL_RDMA_ATOMIC_REQ = 0xAA,
130 CPL_RDMA_ATOMIC_RPL = 0xAB,
131 CPL_RDMA_IMM_DATA = 0xAC,
132 CPL_RDMA_IMM_DATA_SE = 0xAD,
133 CPL_RX_MPS_PKT = 0xAF,
134
135 CPL_TRACE_PKT = 0xB0,
136 CPL_RX2TX_DATA = 0xB1,
137 CPL_TLS_DATA = 0xB1,
138 CPL_ISCSI_DATA = 0xB2,
139 CPL_FCOE_DATA = 0xB3,
140
141 CPL_FW4_MSG = 0xC0,
142 CPL_FW4_PLD = 0xC1,
143 CPL_FW4_ACK = 0xC3,
144 CPL_SRQ_TABLE_RPL = 0xCC,
145 CPL_RX_PHYS_DSGL = 0xD0,
146
147 CPL_FW6_MSG = 0xE0,
148 CPL_FW6_PLD = 0xE1,
149 CPL_TX_TNL_LSO = 0xEC,
150 CPL_TX_PKT_LSO = 0xED,
151 CPL_TX_PKT_XT = 0xEE,
152
153 NUM_CPL_CMDS /* must be last and previous entries must be sorted */
154 };
155
156 enum CPL_error {
157 CPL_ERR_NONE = 0,
158 CPL_ERR_TCAM_PARITY = 1,
159 CPL_ERR_TCAM_MISS = 2,
160 CPL_ERR_TCAM_FULL = 3,
161 CPL_ERR_BAD_LENGTH = 15,
162 CPL_ERR_BAD_ROUTE = 18,
163 CPL_ERR_CONN_RESET = 20,
164 CPL_ERR_CONN_EXIST_SYNRECV = 21,
165 CPL_ERR_CONN_EXIST = 22,
166 CPL_ERR_ARP_MISS = 23,
167 CPL_ERR_BAD_SYN = 24,
168 CPL_ERR_CONN_TIMEDOUT = 30,
169 CPL_ERR_XMIT_TIMEDOUT = 31,
170 CPL_ERR_PERSIST_TIMEDOUT = 32,
171 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
172 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
173 CPL_ERR_RTX_NEG_ADVICE = 35,
174 CPL_ERR_PERSIST_NEG_ADVICE = 36,
175 CPL_ERR_KEEPALV_NEG_ADVICE = 37,
176 CPL_ERR_WAIT_ARP_RPL = 41,
177 CPL_ERR_ABORT_FAILED = 42,
178 CPL_ERR_IWARP_FLM = 50,
179 CPL_CONTAINS_READ_RPL = 60,
180 CPL_CONTAINS_WRITE_RPL = 61,
181 };
182
183 /*
184 * Some of the error codes above implicitly indicate that there is no TID
185 * allocated with the result of an ACT_OPEN. We use this predicate to make
186 * that explicit.
187 */
act_open_has_tid(int status)188 static inline int act_open_has_tid(int status)
189 {
190 return (status != CPL_ERR_TCAM_PARITY &&
191 status != CPL_ERR_TCAM_MISS &&
192 status != CPL_ERR_TCAM_FULL &&
193 status != CPL_ERR_CONN_EXIST_SYNRECV &&
194 status != CPL_ERR_CONN_EXIST);
195 }
196
197 enum {
198 CPL_CONN_POLICY_AUTO = 0,
199 CPL_CONN_POLICY_ASK = 1,
200 CPL_CONN_POLICY_FILTER = 2,
201 CPL_CONN_POLICY_DENY = 3
202 };
203
204 enum {
205 ULP_MODE_NONE = 0,
206 ULP_MODE_ISCSI = 2,
207 ULP_MODE_RDMA = 4,
208 ULP_MODE_TCPDDP = 5,
209 ULP_MODE_FCOE = 6,
210 ULP_MODE_TLS = 8,
211 };
212
213 enum {
214 ULP_CRC_HEADER = 1 << 0,
215 ULP_CRC_DATA = 1 << 1
216 };
217
218 enum {
219 CPL_PASS_OPEN_ACCEPT,
220 CPL_PASS_OPEN_REJECT,
221 CPL_PASS_OPEN_ACCEPT_TNL
222 };
223
224 enum {
225 CPL_ABORT_SEND_RST = 0,
226 CPL_ABORT_NO_RST,
227 };
228
229 enum { /* TX_PKT_XT checksum types */
230 TX_CSUM_TCP = 0,
231 TX_CSUM_UDP = 1,
232 TX_CSUM_CRC16 = 4,
233 TX_CSUM_CRC32 = 5,
234 TX_CSUM_CRC32C = 6,
235 TX_CSUM_FCOE = 7,
236 TX_CSUM_TCPIP = 8,
237 TX_CSUM_UDPIP = 9,
238 TX_CSUM_TCPIP6 = 10,
239 TX_CSUM_UDPIP6 = 11,
240 TX_CSUM_IP = 12,
241 };
242
243 enum { /* packet type in CPL_RX_PKT */
244 PKTYPE_XACT_UCAST = 0,
245 PKTYPE_HASH_UCAST = 1,
246 PKTYPE_XACT_MCAST = 2,
247 PKTYPE_HASH_MCAST = 3,
248 PKTYPE_PROMISC = 4,
249 PKTYPE_HPROMISC = 5,
250 PKTYPE_BCAST = 6
251 };
252
253 enum { /* DMAC type in CPL_RX_PKT */
254 DATYPE_UCAST,
255 DATYPE_MCAST,
256 DATYPE_BCAST
257 };
258
259 enum { /* TCP congestion control algorithms */
260 CONG_ALG_RENO,
261 CONG_ALG_TAHOE,
262 CONG_ALG_NEWRENO,
263 CONG_ALG_HIGHSPEED
264 };
265
266 enum { /* RSS hash type */
267 RSS_HASH_NONE = 0, /* no hash computed */
268 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */
269 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */
270 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */
271 };
272
273 enum { /* LE commands */
274 LE_CMD_READ = 0x4,
275 LE_CMD_WRITE = 0xb
276 };
277
278 enum { /* LE request size */
279 LE_SZ_NONE = 0,
280 LE_SZ_33 = 1,
281 LE_SZ_66 = 2,
282 LE_SZ_132 = 3,
283 LE_SZ_264 = 4,
284 LE_SZ_528 = 5
285 };
286
287 union opcode_tid {
288 __be32 opcode_tid;
289 __u8 opcode;
290 };
291
292 #define S_CPL_OPCODE 24
293 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
294 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF)
295 #define G_TID(x) ((x) & 0xFFFFFF)
296
297 /* tid is assumed to be 24-bits */
298 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid))
299
300 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
301
302 /* extract the TID from a CPL command */
303 #define GET_TID(cmd) (G_TID(be32_to_cpu(OPCODE_TID(cmd))))
304
305 /* partitioning of TID fields that also carry a queue id */
306 #define S_TID_TID 0
307 #define M_TID_TID 0x3fff
308 #define V_TID_TID(x) ((x) << S_TID_TID)
309 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID)
310
311 #define S_TID_QID 14
312 #define M_TID_QID 0x3ff
313 #define V_TID_QID(x) ((x) << S_TID_QID)
314 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID)
315
316 union opcode_info {
317 __be64 opcode_info;
318 __u8 opcode;
319 };
320
321 struct tcp_options {
322 __be16 mss;
323 __u8 wsf;
324 #if defined(__LITTLE_ENDIAN_BITFIELD)
325 __u8 :4;
326 __u8 unknown:1;
327 __u8 ecn:1;
328 __u8 sack:1;
329 __u8 tstamp:1;
330 #else
331 __u8 tstamp:1;
332 __u8 sack:1;
333 __u8 ecn:1;
334 __u8 unknown:1;
335 __u8 :4;
336 #endif
337 };
338
339 struct rss_header {
340 __u8 opcode;
341 #if defined(__LITTLE_ENDIAN_BITFIELD)
342 __u8 channel:2;
343 __u8 filter_hit:1;
344 __u8 filter_tid:1;
345 __u8 hash_type:2;
346 __u8 ipv6:1;
347 __u8 send2fw:1;
348 #else
349 __u8 send2fw:1;
350 __u8 ipv6:1;
351 __u8 hash_type:2;
352 __u8 filter_tid:1;
353 __u8 filter_hit:1;
354 __u8 channel:2;
355 #endif
356 __be16 qid;
357 __be32 hash_val;
358 };
359
360 #define S_HASHTYPE 20
361 #define M_HASHTYPE 0x3
362 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
363
364 #define S_QNUM 0
365 #define M_QNUM 0xFFFF
366 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM)
367
368 #if defined(RSS_HDR_VLD) || defined(CHELSIO_FW)
369 # define RSS_HDR struct rss_header rss_hdr;
370 #else
371 # define RSS_HDR
372 #endif
373
374 #ifndef CHELSIO_FW
375 struct work_request_hdr {
376 __be32 wr_hi;
377 __be32 wr_mid;
378 __be64 wr_lo;
379 };
380
381 /* wr_mid fields */
382 #define S_WR_LEN16 0
383 #define M_WR_LEN16 0xFF
384 #define V_WR_LEN16(x) ((x) << S_WR_LEN16)
385 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16)
386
387 /* wr_hi fields */
388 #define S_WR_OP 24
389 #define M_WR_OP 0xFF
390 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP)
391 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
392
393 # define WR_HDR struct work_request_hdr wr
394 # define WR_HDR_SIZE sizeof(struct work_request_hdr)
395 #else
396 # define WR_HDR
397 # define WR_HDR_SIZE 0
398 #endif
399
400 /* option 0 fields */
401 #define S_ACCEPT_MODE 0
402 #define M_ACCEPT_MODE 0x3
403 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE)
404 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE)
405
406 #define S_TX_CHAN 2
407 #define M_TX_CHAN 0x3
408 #define V_TX_CHAN(x) ((x) << S_TX_CHAN)
409 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN)
410
411 #define S_NO_CONG 4
412 #define V_NO_CONG(x) ((x) << S_NO_CONG)
413 #define F_NO_CONG V_NO_CONG(1U)
414
415 #define S_DELACK 5
416 #define V_DELACK(x) ((x) << S_DELACK)
417 #define F_DELACK V_DELACK(1U)
418
419 #define S_INJECT_TIMER 6
420 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
421 #define F_INJECT_TIMER V_INJECT_TIMER(1U)
422
423 #define S_NON_OFFLOAD 7
424 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD)
425 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U)
426
427 #define S_ULP_MODE 8
428 #define M_ULP_MODE 0xF
429 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
430 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
431
432 #define S_RCV_BUFSIZ 12
433 #define M_RCV_BUFSIZ 0x3FFU
434 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
435 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
436
437 #define S_DSCP 22
438 #define M_DSCP 0x3F
439 #define V_DSCP(x) ((x) << S_DSCP)
440 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP)
441
442 #define S_SMAC_SEL 28
443 #define M_SMAC_SEL 0xFF
444 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL)
445 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL)
446
447 #define S_L2T_IDX 36
448 #define M_L2T_IDX 0xFFF
449 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX)
450 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
451
452 #define S_TCAM_BYPASS 48
453 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS)
454 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL)
455
456 #define S_NAGLE 49
457 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE)
458 #define F_NAGLE V_NAGLE(1ULL)
459
460 #define S_WND_SCALE 50
461 #define M_WND_SCALE 0xF
462 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE)
463 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
464
465 #define S_KEEP_ALIVE 54
466 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE)
467 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL)
468
469 #define S_MAX_RT 55
470 #define M_MAX_RT 0xF
471 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT)
472 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT)
473
474 #define S_MAX_RT_OVERRIDE 59
475 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE)
476 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL)
477
478 #define S_MSS_IDX 60
479 #define M_MSS_IDX 0xF
480 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX)
481 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
482
483 /* option 1 fields */
484 #define S_SYN_RSS_ENABLE 0
485 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE)
486 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U)
487
488 #define S_SYN_RSS_USE_HASH 1
489 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH)
490 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U)
491
492 #define S_SYN_RSS_QUEUE 2
493 #define M_SYN_RSS_QUEUE 0x3FF
494 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE)
495 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE)
496
497 #define S_LISTEN_INTF 12
498 #define M_LISTEN_INTF 0xFF
499 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF)
500 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF)
501
502 #define S_LISTEN_FILTER 20
503 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER)
504 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U)
505
506 #define S_SYN_DEFENSE 21
507 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
508 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U)
509
510 #define S_CONN_POLICY 22
511 #define M_CONN_POLICY 0x3
512 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
513 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
514
515 #define S_T5_FILT_INFO 24
516 #define M_T5_FILT_INFO 0xffffffffffULL
517 #define V_T5_FILT_INFO(x) ((x) << S_T5_FILT_INFO)
518 #define G_T5_FILT_INFO(x) (((x) >> S_T5_FILT_INFO) & M_T5_FILT_INFO)
519
520 #define S_FILT_INFO 28
521 #define M_FILT_INFO 0xfffffffffULL
522 #define V_FILT_INFO(x) ((x) << S_FILT_INFO)
523 #define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO)
524
525 /* option 2 fields */
526 #define S_RSS_QUEUE 0
527 #define M_RSS_QUEUE 0x3FF
528 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
529 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE)
530
531 #define S_RSS_QUEUE_VALID 10
532 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID)
533 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U)
534
535 #define S_RX_COALESCE_VALID 11
536 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
537 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U)
538
539 #define S_RX_COALESCE 12
540 #define M_RX_COALESCE 0x3
541 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
542 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
543
544 #define S_CONG_CNTRL 14
545 #define M_CONG_CNTRL 0x3
546 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL)
547 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL)
548
549 #define S_PACE 16
550 #define M_PACE 0x3
551 #define V_PACE(x) ((x) << S_PACE)
552 #define G_PACE(x) (((x) >> S_PACE) & M_PACE)
553
554 #define S_CONG_CNTRL_VALID 18
555 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID)
556 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U)
557
558 #define S_T5_ISS 18
559 #define V_T5_ISS(x) ((x) << S_T5_ISS)
560 #define F_T5_ISS V_T5_ISS(1U)
561
562 #define S_PACE_VALID 19
563 #define V_PACE_VALID(x) ((x) << S_PACE_VALID)
564 #define F_PACE_VALID V_PACE_VALID(1U)
565
566 #define S_RX_FC_DISABLE 20
567 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
568 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U)
569
570 #define S_RX_FC_DDP 21
571 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP)
572 #define F_RX_FC_DDP V_RX_FC_DDP(1U)
573
574 #define S_RX_FC_VALID 22
575 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
576 #define F_RX_FC_VALID V_RX_FC_VALID(1U)
577
578 #define S_TX_QUEUE 23
579 #define M_TX_QUEUE 0x7
580 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE)
581 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE)
582
583 #define S_RX_CHANNEL 26
584 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL)
585 #define F_RX_CHANNEL V_RX_CHANNEL(1U)
586
587 #define S_CCTRL_ECN 27
588 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN)
589 #define F_CCTRL_ECN V_CCTRL_ECN(1U)
590
591 #define S_WND_SCALE_EN 28
592 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN)
593 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U)
594
595 #define S_TSTAMPS_EN 29
596 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN)
597 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U)
598
599 #define S_SACK_EN 30
600 #define V_SACK_EN(x) ((x) << S_SACK_EN)
601 #define F_SACK_EN V_SACK_EN(1U)
602
603 #define S_T5_OPT_2_VALID 31
604 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID)
605 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U)
606
607 struct cpl_pass_open_req {
608 WR_HDR;
609 union opcode_tid ot;
610 __be16 local_port;
611 __be16 peer_port;
612 __be32 local_ip;
613 __be32 peer_ip;
614 __be64 opt0;
615 __be64 opt1;
616 };
617
618 struct cpl_pass_open_req6 {
619 WR_HDR;
620 union opcode_tid ot;
621 __be16 local_port;
622 __be16 peer_port;
623 __be64 local_ip_hi;
624 __be64 local_ip_lo;
625 __be64 peer_ip_hi;
626 __be64 peer_ip_lo;
627 __be64 opt0;
628 __be64 opt1;
629 };
630
631 struct cpl_pass_open_rpl {
632 RSS_HDR
633 union opcode_tid ot;
634 __u8 rsvd[3];
635 __u8 status;
636 };
637
638 struct cpl_pass_establish {
639 RSS_HDR
640 union opcode_tid ot;
641 __be32 rsvd;
642 __be32 tos_stid;
643 __be16 mac_idx;
644 __be16 tcp_opt;
645 __be32 snd_isn;
646 __be32 rcv_isn;
647 };
648
649 /* cpl_pass_establish.tos_stid fields */
650 #define S_PASS_OPEN_TID 0
651 #define M_PASS_OPEN_TID 0xFFFFFF
652 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
653 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
654
655 #define S_PASS_OPEN_TOS 24
656 #define M_PASS_OPEN_TOS 0xFF
657 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
658 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
659
660 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
661 #define S_TCPOPT_WSCALE_OK 5
662 #define M_TCPOPT_WSCALE_OK 0x1
663 #define V_TCPOPT_WSCALE_OK(x) ((x) << S_TCPOPT_WSCALE_OK)
664 #define G_TCPOPT_WSCALE_OK(x) (((x) >> S_TCPOPT_WSCALE_OK) & M_TCPOPT_WSCALE_OK)
665
666 #define S_TCPOPT_SACK 6
667 #define M_TCPOPT_SACK 0x1
668 #define V_TCPOPT_SACK(x) ((x) << S_TCPOPT_SACK)
669 #define G_TCPOPT_SACK(x) (((x) >> S_TCPOPT_SACK) & M_TCPOPT_SACK)
670
671 #define S_TCPOPT_TSTAMP 7
672 #define M_TCPOPT_TSTAMP 0x1
673 #define V_TCPOPT_TSTAMP(x) ((x) << S_TCPOPT_TSTAMP)
674 #define G_TCPOPT_TSTAMP(x) (((x) >> S_TCPOPT_TSTAMP) & M_TCPOPT_TSTAMP)
675
676 #define S_TCPOPT_SND_WSCALE 8
677 #define M_TCPOPT_SND_WSCALE 0xF
678 #define V_TCPOPT_SND_WSCALE(x) ((x) << S_TCPOPT_SND_WSCALE)
679 #define G_TCPOPT_SND_WSCALE(x) (((x) >> S_TCPOPT_SND_WSCALE) & M_TCPOPT_SND_WSCALE)
680
681 #define S_TCPOPT_MSS 12
682 #define M_TCPOPT_MSS 0xF
683 #define V_TCPOPT_MSS(x) ((x) << S_TCPOPT_MSS)
684 #define G_TCPOPT_MSS(x) (((x) >> S_TCPOPT_MSS) & M_TCPOPT_MSS)
685
686 struct cpl_pass_accept_req {
687 RSS_HDR
688 union opcode_tid ot;
689 __be16 rsvd;
690 __be16 len;
691 __be32 hdr_len;
692 __be16 vlan;
693 __be16 l2info;
694 __be32 tos_stid;
695 struct tcp_options tcpopt;
696 };
697
698 /* cpl_pass_accept_req.hdr_len fields */
699 #define S_SYN_RX_CHAN 0
700 #define M_SYN_RX_CHAN 0xF
701 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN)
702 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN)
703
704 #define S_TCP_HDR_LEN 10
705 #define M_TCP_HDR_LEN 0x3F
706 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN)
707 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN)
708
709 #define S_T6_TCP_HDR_LEN 8
710 #define V_T6_TCP_HDR_LEN(x) ((x) << S_T6_TCP_HDR_LEN)
711 #define G_T6_TCP_HDR_LEN(x) (((x) >> S_T6_TCP_HDR_LEN) & M_TCP_HDR_LEN)
712
713 #define S_IP_HDR_LEN 16
714 #define M_IP_HDR_LEN 0x3FF
715 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN)
716 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN)
717
718 #define S_T6_IP_HDR_LEN 14
719 #define V_T6_IP_HDR_LEN(x) ((x) << S_T6_IP_HDR_LEN)
720 #define G_T6_IP_HDR_LEN(x) (((x) >> S_T6_IP_HDR_LEN) & M_IP_HDR_LEN)
721
722 #define S_ETH_HDR_LEN 26
723 #define M_ETH_HDR_LEN 0x3F
724 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN)
725 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN)
726
727 #define S_T6_ETH_HDR_LEN 24
728 #define M_T6_ETH_HDR_LEN 0xFF
729 #define V_T6_ETH_HDR_LEN(x) ((x) << S_T6_ETH_HDR_LEN)
730 #define G_T6_ETH_HDR_LEN(x) (((x) >> S_T6_ETH_HDR_LEN) & M_T6_ETH_HDR_LEN)
731
732 /* cpl_pass_accept_req.l2info fields */
733 #define S_SYN_MAC_IDX 0
734 #define M_SYN_MAC_IDX 0x1FF
735 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX)
736 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX)
737
738 #define S_SYN_XACT_MATCH 9
739 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH)
740 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U)
741
742 #define S_SYN_INTF 12
743 #define M_SYN_INTF 0xF
744 #define V_SYN_INTF(x) ((x) << S_SYN_INTF)
745 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF)
746
747 struct cpl_pass_accept_rpl {
748 WR_HDR;
749 union opcode_tid ot;
750 __be32 opt2;
751 __be64 opt0;
752 };
753
754 struct cpl_t5_pass_accept_rpl {
755 WR_HDR;
756 union opcode_tid ot;
757 __be32 opt2;
758 __be64 opt0;
759 __be32 iss;
760 union {
761 __be32 rsvd; /* T5 */
762 __be32 opt3; /* T6 */
763 };
764 };
765
766 struct cpl_act_open_req {
767 WR_HDR;
768 union opcode_tid ot;
769 __be16 local_port;
770 __be16 peer_port;
771 __be32 local_ip;
772 __be32 peer_ip;
773 __be64 opt0;
774 __be32 params;
775 __be32 opt2;
776 };
777
778 #define S_FILTER_TUPLE 24
779 #define M_FILTER_TUPLE 0xFFFFFFFFFF
780 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE)
781 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE)
782
783 struct cpl_t5_act_open_req {
784 WR_HDR;
785 union opcode_tid ot;
786 __be16 local_port;
787 __be16 peer_port;
788 __be32 local_ip;
789 __be32 peer_ip;
790 __be64 opt0;
791 __be32 rsvd;
792 __be32 opt2;
793 __be64 params;
794 };
795
796 struct cpl_t6_act_open_req {
797 WR_HDR;
798 union opcode_tid ot;
799 __be16 local_port;
800 __be16 peer_port;
801 __be32 local_ip;
802 __be32 peer_ip;
803 __be64 opt0;
804 __be32 rsvd;
805 __be32 opt2;
806 __be64 params;
807 __be32 rsvd2;
808 __be32 opt3;
809 };
810
811 /* cpl_{t5,t6}_act_open_req.params field */
812 #define S_AOPEN_FCOEMASK 0
813 #define V_AOPEN_FCOEMASK(x) ((x) << S_AOPEN_FCOEMASK)
814 #define F_AOPEN_FCOEMASK V_AOPEN_FCOEMASK(1U)
815
816 struct cpl_act_open_req6 {
817 WR_HDR;
818 union opcode_tid ot;
819 __be16 local_port;
820 __be16 peer_port;
821 __be64 local_ip_hi;
822 __be64 local_ip_lo;
823 __be64 peer_ip_hi;
824 __be64 peer_ip_lo;
825 __be64 opt0;
826 __be32 params;
827 __be32 opt2;
828 };
829
830 struct cpl_t5_act_open_req6 {
831 WR_HDR;
832 union opcode_tid ot;
833 __be16 local_port;
834 __be16 peer_port;
835 __be64 local_ip_hi;
836 __be64 local_ip_lo;
837 __be64 peer_ip_hi;
838 __be64 peer_ip_lo;
839 __be64 opt0;
840 __be32 rsvd;
841 __be32 opt2;
842 __be64 params;
843 };
844
845 struct cpl_t6_act_open_req6 {
846 WR_HDR;
847 union opcode_tid ot;
848 __be16 local_port;
849 __be16 peer_port;
850 __be64 local_ip_hi;
851 __be64 local_ip_lo;
852 __be64 peer_ip_hi;
853 __be64 peer_ip_lo;
854 __be64 opt0;
855 __be32 rsvd;
856 __be32 opt2;
857 __be64 params;
858 __be32 rsvd2;
859 __be32 opt3;
860 };
861
862 struct cpl_act_open_rpl {
863 RSS_HDR
864 union opcode_tid ot;
865 __be32 atid_status;
866 };
867
868 /* cpl_act_open_rpl.atid_status fields */
869 #define S_AOPEN_STATUS 0
870 #define M_AOPEN_STATUS 0xFF
871 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS)
872 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS)
873
874 #define S_AOPEN_ATID 8
875 #define M_AOPEN_ATID 0xFFFFFF
876 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID)
877 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID)
878
879 struct cpl_act_establish {
880 RSS_HDR
881 union opcode_tid ot;
882 __be32 rsvd;
883 __be32 tos_atid;
884 __be16 mac_idx;
885 __be16 tcp_opt;
886 __be32 snd_isn;
887 __be32 rcv_isn;
888 };
889
890 struct cpl_get_tcb {
891 WR_HDR;
892 union opcode_tid ot;
893 __be16 reply_ctrl;
894 __be16 cookie;
895 };
896
897 /* cpl_get_tcb.reply_ctrl fields */
898 #define S_QUEUENO 0
899 #define M_QUEUENO 0x3FF
900 #define V_QUEUENO(x) ((x) << S_QUEUENO)
901 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO)
902
903 #define S_REPLY_CHAN 14
904 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN)
905 #define F_REPLY_CHAN V_REPLY_CHAN(1U)
906
907 #define S_NO_REPLY 15
908 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
909 #define F_NO_REPLY V_NO_REPLY(1U)
910
911 struct cpl_get_tcb_rpl {
912 RSS_HDR
913 union opcode_tid ot;
914 __u8 cookie;
915 __u8 status;
916 __be16 len;
917 };
918
919 struct cpl_set_tcb {
920 WR_HDR;
921 union opcode_tid ot;
922 __be16 reply_ctrl;
923 __be16 cookie;
924 };
925
926 struct cpl_set_tcb_field {
927 WR_HDR;
928 union opcode_tid ot;
929 __be16 reply_ctrl;
930 __be16 word_cookie;
931 __be64 mask;
932 __be64 val;
933 };
934
935 /* cpl_set_tcb_field.word_cookie fields */
936 #define S_WORD 0
937 #define M_WORD 0x1F
938 #define V_WORD(x) ((x) << S_WORD)
939 #define G_WORD(x) (((x) >> S_WORD) & M_WORD)
940
941 #define S_COOKIE 5
942 #define M_COOKIE 0x7
943 #define V_COOKIE(x) ((x) << S_COOKIE)
944 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE)
945
946 struct cpl_set_tcb_rpl {
947 RSS_HDR
948 union opcode_tid ot;
949 __be16 rsvd;
950 __u8 cookie;
951 __u8 status;
952 __be64 oldval;
953 };
954
955 struct cpl_close_con_req {
956 WR_HDR;
957 union opcode_tid ot;
958 __be32 rsvd;
959 };
960
961 struct cpl_close_con_rpl {
962 RSS_HDR
963 union opcode_tid ot;
964 __u8 rsvd[3];
965 __u8 status;
966 __be32 snd_nxt;
967 __be32 rcv_nxt;
968 };
969
970 struct cpl_close_listsvr_req {
971 WR_HDR;
972 union opcode_tid ot;
973 __be16 reply_ctrl;
974 __be16 rsvd;
975 };
976
977 /* additional cpl_close_listsvr_req.reply_ctrl field */
978 #define S_LISTSVR_IPV6 14
979 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6)
980 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U)
981
982 struct cpl_close_listsvr_rpl {
983 RSS_HDR
984 union opcode_tid ot;
985 __u8 rsvd[3];
986 __u8 status;
987 };
988
989 struct cpl_abort_req_rss {
990 RSS_HDR
991 union opcode_tid ot;
992 __u8 rsvd[3];
993 __u8 status;
994 };
995
996 struct cpl_abort_req_rss6 {
997 RSS_HDR
998 union opcode_tid ot;
999 __u32 srqidx_status;
1000 };
1001
1002 #define S_ABORT_RSS_STATUS 0
1003 #define M_ABORT_RSS_STATUS 0xff
1004 #define V_ABORT_RSS_STATUS(x) ((x) << S_ABORT_RSS_STATUS)
1005 #define G_ABORT_RSS_STATUS(x) (((x) >> S_ABORT_RSS_STATUS) & M_ABORT_RSS_STATUS)
1006
1007 #define S_ABORT_RSS_SRQIDX 8
1008 #define M_ABORT_RSS_SRQIDX 0xffffff
1009 #define V_ABORT_RSS_SRQIDX(x) ((x) << S_ABORT_RSS_SRQIDX)
1010 #define G_ABORT_RSS_SRQIDX(x) (((x) >> S_ABORT_RSS_SRQIDX) & M_ABORT_RSS_SRQIDX)
1011
1012
1013 /* cpl_abort_req status command code in case of T6,
1014 * bit[0] specifies whether to send RST (0) to remote peer or suppress it (1)
1015 * bit[1] indicates ABORT_REQ was sent after a CLOSE_CON_REQ
1016 * bit[2] specifies whether to disable the mmgr (1) or not (0)
1017 */
1018 struct cpl_abort_req {
1019 WR_HDR;
1020 union opcode_tid ot;
1021 __be32 rsvd0;
1022 __u8 rsvd1;
1023 __u8 cmd;
1024 __u8 rsvd2[6];
1025 };
1026
1027 struct cpl_abort_rpl_rss {
1028 RSS_HDR
1029 union opcode_tid ot;
1030 __u8 rsvd[3];
1031 __u8 status;
1032 };
1033
1034 struct cpl_abort_rpl_rss6 {
1035 RSS_HDR
1036 union opcode_tid ot;
1037 __u32 srqidx_status;
1038 };
1039
1040 struct cpl_abort_rpl {
1041 WR_HDR;
1042 union opcode_tid ot;
1043 __be32 rsvd0;
1044 __u8 rsvd1;
1045 __u8 cmd;
1046 __u8 rsvd2[6];
1047 };
1048
1049 struct cpl_peer_close {
1050 RSS_HDR
1051 union opcode_tid ot;
1052 __be32 rcv_nxt;
1053 };
1054
1055 struct cpl_tid_release {
1056 WR_HDR;
1057 union opcode_tid ot;
1058 __be32 rsvd;
1059 };
1060
1061 struct tx_data_wr {
1062 __be32 wr_hi;
1063 __be32 wr_lo;
1064 __be32 len;
1065 __be32 flags;
1066 __be32 sndseq;
1067 __be32 param;
1068 };
1069
1070 /* tx_data_wr.flags fields */
1071 #define S_TX_ACK_PAGES 21
1072 #define M_TX_ACK_PAGES 0x7
1073 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES)
1074 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
1075
1076 /* tx_data_wr.param fields */
1077 #define S_TX_PORT 0
1078 #define M_TX_PORT 0x7
1079 #define V_TX_PORT(x) ((x) << S_TX_PORT)
1080 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
1081
1082 #define S_TX_MSS 4
1083 #define M_TX_MSS 0xF
1084 #define V_TX_MSS(x) ((x) << S_TX_MSS)
1085 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
1086
1087 #define S_TX_QOS 8
1088 #define M_TX_QOS 0xFF
1089 #define V_TX_QOS(x) ((x) << S_TX_QOS)
1090 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
1091
1092 #define S_TX_SNDBUF 16
1093 #define M_TX_SNDBUF 0xFFFF
1094 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
1095 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
1096
1097 struct cpl_tx_data {
1098 union opcode_tid ot;
1099 __be32 len;
1100 __be32 rsvd;
1101 __be32 flags;
1102 };
1103
1104 /* cpl_tx_data.flags fields */
1105 #define S_TX_PROXY 5
1106 #define V_TX_PROXY(x) ((x) << S_TX_PROXY)
1107 #define F_TX_PROXY V_TX_PROXY(1U)
1108
1109 #define S_TX_ULP_SUBMODE 6
1110 #define M_TX_ULP_SUBMODE 0xF
1111 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
1112 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
1113
1114 #define S_TX_ULP_MODE 10
1115 #define M_TX_ULP_MODE 0x7
1116 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
1117 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
1118
1119 #define S_TX_FORCE 13
1120 #define V_TX_FORCE(x) ((x) << S_TX_FORCE)
1121 #define F_TX_FORCE V_TX_FORCE(1U)
1122
1123 #define S_TX_SHOVE 14
1124 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
1125 #define F_TX_SHOVE V_TX_SHOVE(1U)
1126
1127 #define S_TX_MORE 15
1128 #define V_TX_MORE(x) ((x) << S_TX_MORE)
1129 #define F_TX_MORE V_TX_MORE(1U)
1130
1131 #define S_TX_URG 16
1132 #define V_TX_URG(x) ((x) << S_TX_URG)
1133 #define F_TX_URG V_TX_URG(1U)
1134
1135 #define S_TX_FLUSH 17
1136 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH)
1137 #define F_TX_FLUSH V_TX_FLUSH(1U)
1138
1139 #define S_TX_SAVE 18
1140 #define V_TX_SAVE(x) ((x) << S_TX_SAVE)
1141 #define F_TX_SAVE V_TX_SAVE(1U)
1142
1143 #define S_TX_TNL 19
1144 #define V_TX_TNL(x) ((x) << S_TX_TNL)
1145 #define F_TX_TNL V_TX_TNL(1U)
1146
1147 #define S_T6_TX_FORCE 20
1148 #define V_T6_TX_FORCE(x) ((x) << S_T6_TX_FORCE)
1149 #define F_T6_TX_FORCE V_T6_TX_FORCE(1U)
1150
1151 /* additional tx_data_wr.flags fields */
1152 #define S_TX_CPU_IDX 0
1153 #define M_TX_CPU_IDX 0x3F
1154 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
1155 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
1156
1157 #define S_TX_CLOSE 17
1158 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
1159 #define F_TX_CLOSE V_TX_CLOSE(1U)
1160
1161 #define S_TX_INIT 18
1162 #define V_TX_INIT(x) ((x) << S_TX_INIT)
1163 #define F_TX_INIT V_TX_INIT(1U)
1164
1165 #define S_TX_IMM_ACK 19
1166 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
1167 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U)
1168
1169 #define S_TX_IMM_DMA 20
1170 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
1171 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U)
1172
1173 struct cpl_tx_data_ack {
1174 RSS_HDR
1175 union opcode_tid ot;
1176 __be32 snd_una;
1177 };
1178
1179 struct cpl_wr_ack { /* XXX */
1180 RSS_HDR
1181 union opcode_tid ot;
1182 __be16 credits;
1183 __be16 rsvd;
1184 __be32 snd_nxt;
1185 __be32 snd_una;
1186 };
1187
1188 struct cpl_tx_pkt_core {
1189 __be32 ctrl0;
1190 __be16 pack;
1191 __be16 len;
1192 __be64 ctrl1;
1193 };
1194
1195 struct cpl_tx_pkt {
1196 WR_HDR;
1197 struct cpl_tx_pkt_core c;
1198 };
1199
1200 #define cpl_tx_pkt_xt cpl_tx_pkt
1201
1202 /* cpl_tx_pkt_core.ctrl0 fields */
1203 #define S_TXPKT_VF 0
1204 #define M_TXPKT_VF 0xFF
1205 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF)
1206 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF)
1207
1208 #define S_TXPKT_PF 8
1209 #define M_TXPKT_PF 0x7
1210 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF)
1211 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF)
1212
1213 #define S_TXPKT_VF_VLD 11
1214 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD)
1215 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U)
1216
1217 #define S_TXPKT_OVLAN_IDX 12
1218 #define M_TXPKT_OVLAN_IDX 0xF
1219 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX)
1220 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX)
1221
1222 #define S_TXPKT_T5_OVLAN_IDX 12
1223 #define M_TXPKT_T5_OVLAN_IDX 0x7
1224 #define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX)
1225 #define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \
1226 M_TXPKT_T5_OVLAN_IDX)
1227
1228 #define S_TXPKT_INTF 16
1229 #define M_TXPKT_INTF 0xF
1230 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1231 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1232
1233 #define S_TXPKT_SPECIAL_STAT 20
1234 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT)
1235 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U)
1236
1237 #define S_TXPKT_T5_FCS_DIS 21
1238 #define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS)
1239 #define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U)
1240
1241 #define S_TXPKT_INS_OVLAN 21
1242 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN)
1243 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U)
1244
1245 #define S_TXPKT_T5_INS_OVLAN 15
1246 #define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN)
1247 #define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U)
1248
1249 #define S_TXPKT_STAT_DIS 22
1250 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS)
1251 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U)
1252
1253 #define S_TXPKT_LOOPBACK 23
1254 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1255 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U)
1256
1257 #define S_TXPKT_TSTAMP 23
1258 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP)
1259 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U)
1260
1261 #define S_TXPKT_OPCODE 24
1262 #define M_TXPKT_OPCODE 0xFF
1263 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1264 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1265
1266 /* cpl_tx_pkt_core.ctrl1 fields */
1267 #define S_TXPKT_SA_IDX 0
1268 #define M_TXPKT_SA_IDX 0xFFF
1269 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX)
1270 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX)
1271
1272 #define S_TXPKT_CSUM_END 12
1273 #define M_TXPKT_CSUM_END 0xFF
1274 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END)
1275 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END)
1276
1277 #define S_TXPKT_CSUM_START 20
1278 #define M_TXPKT_CSUM_START 0x3FF
1279 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START)
1280 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START)
1281
1282 #define S_TXPKT_IPHDR_LEN 20
1283 #define M_TXPKT_IPHDR_LEN 0x3FFF
1284 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN)
1285 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN)
1286
1287 #define M_T6_TXPKT_IPHDR_LEN 0xFFF
1288 #define G_T6_TXPKT_IPHDR_LEN(x) \
1289 (((x) >> S_TXPKT_IPHDR_LEN) & M_T6_TXPKT_IPHDR_LEN)
1290
1291 #define S_TXPKT_CSUM_LOC 30
1292 #define M_TXPKT_CSUM_LOC 0x3FF
1293 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC)
1294 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC)
1295
1296 #define S_TXPKT_ETHHDR_LEN 34
1297 #define M_TXPKT_ETHHDR_LEN 0x3F
1298 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN)
1299 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN)
1300
1301 #define S_T6_TXPKT_ETHHDR_LEN 32
1302 #define M_T6_TXPKT_ETHHDR_LEN 0xFF
1303 #define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN)
1304 #define G_T6_TXPKT_ETHHDR_LEN(x) \
1305 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN)
1306
1307 #define S_TXPKT_CSUM_TYPE 40
1308 #define M_TXPKT_CSUM_TYPE 0xF
1309 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE)
1310 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE)
1311
1312 #define S_TXPKT_VLAN 44
1313 #define M_TXPKT_VLAN 0xFFFF
1314 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN)
1315 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1316
1317 #define S_TXPKT_VLAN_VLD 60
1318 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD)
1319 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL)
1320
1321 #define S_TXPKT_IPSEC 61
1322 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC)
1323 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL)
1324
1325 #define S_TXPKT_IPCSUM_DIS 62
1326 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS)
1327 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL)
1328
1329 #define S_TXPKT_L4CSUM_DIS 63
1330 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS)
1331 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL)
1332
1333 struct cpl_tx_pkt_lso_core {
1334 __be32 lso_ctrl;
1335 __be16 ipid_ofst;
1336 __be16 mss;
1337 __be32 seqno_offset;
1338 __be32 len;
1339 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1340 };
1341
1342 struct cpl_tx_pkt_lso {
1343 WR_HDR;
1344 struct cpl_tx_pkt_lso_core c;
1345 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1346 };
1347
1348 struct cpl_tx_pkt_ufo_core {
1349 __be16 ethlen;
1350 __be16 iplen;
1351 __be16 udplen;
1352 __be16 mss;
1353 __be32 len;
1354 __be32 r1;
1355 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1356 };
1357
1358 struct cpl_tx_pkt_ufo {
1359 WR_HDR;
1360 struct cpl_tx_pkt_ufo_core c;
1361 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1362 };
1363
1364 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
1365 #define S_LSO_TCPHDR_LEN 0
1366 #define M_LSO_TCPHDR_LEN 0xF
1367 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN)
1368 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN)
1369
1370 #define S_LSO_IPHDR_LEN 4
1371 #define M_LSO_IPHDR_LEN 0xFFF
1372 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN)
1373 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN)
1374
1375 #define S_LSO_ETHHDR_LEN 16
1376 #define M_LSO_ETHHDR_LEN 0xF
1377 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN)
1378 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN)
1379
1380 #define S_LSO_IPV6 20
1381 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
1382 #define F_LSO_IPV6 V_LSO_IPV6(1U)
1383
1384 #define S_LSO_OFLD_ENCAP 21
1385 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP)
1386 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U)
1387
1388 #define S_LSO_LAST_SLICE 22
1389 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE)
1390 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U)
1391
1392 #define S_LSO_FIRST_SLICE 23
1393 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)
1394 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U)
1395
1396 #define S_LSO_OPCODE 24
1397 #define M_LSO_OPCODE 0xFF
1398 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
1399 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)
1400
1401 #define S_LSO_T5_XFER_SIZE 0
1402 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF
1403 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE)
1404 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE)
1405
1406 /* cpl_tx_pkt_lso_core.mss fields */
1407 #define S_LSO_MSS 0
1408 #define M_LSO_MSS 0x3FFF
1409 #define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1410 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1411
1412 #define S_LSO_IPID_SPLIT 15
1413 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT)
1414 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U)
1415
1416 struct cpl_tx_pkt_fso {
1417 WR_HDR;
1418 __be32 fso_ctrl;
1419 __be16 seqcnt_ofst;
1420 __be16 mtu;
1421 __be32 param_offset;
1422 __be32 len;
1423 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */
1424 };
1425
1426 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */
1427 #define S_FSO_XCHG_CLASS 21
1428 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS)
1429 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U)
1430
1431 #define S_FSO_INITIATOR 20
1432 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR)
1433 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U)
1434
1435 #define S_FSO_FCHDR_LEN 12
1436 #define M_FSO_FCHDR_LEN 0xF
1437 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN)
1438 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN)
1439
1440 struct cpl_iscsi_hdr_no_rss {
1441 union opcode_tid ot;
1442 __be16 pdu_len_ddp;
1443 __be16 len;
1444 __be32 seq;
1445 __be16 urg;
1446 __u8 rsvd;
1447 __u8 status;
1448 };
1449
1450 struct cpl_tx_data_iso {
1451 __be32 op_to_scsi;
1452 __u8 reserved1;
1453 __u8 ahs_len;
1454 __be16 mpdu;
1455 __be32 burst_size;
1456 __be32 len;
1457 __be32 reserved2_seglen_offset;
1458 __be32 datasn_offset;
1459 __be32 buffer_offset;
1460 __be32 reserved3;
1461
1462 /* encapsulated CPL_TX_DATA follows here */
1463 };
1464
1465 /* cpl_tx_data_iso.op_to_scsi fields */
1466 #define S_CPL_TX_DATA_ISO_OP 24
1467 #define M_CPL_TX_DATA_ISO_OP 0xff
1468 #define V_CPL_TX_DATA_ISO_OP(x) ((x) << S_CPL_TX_DATA_ISO_OP)
1469 #define G_CPL_TX_DATA_ISO_OP(x) \
1470 (((x) >> S_CPL_TX_DATA_ISO_OP) & M_CPL_TX_DATA_ISO_OP)
1471
1472 #define S_CPL_TX_DATA_ISO_FIRST 23
1473 #define M_CPL_TX_DATA_ISO_FIRST 0x1
1474 #define V_CPL_TX_DATA_ISO_FIRST(x) ((x) << S_CPL_TX_DATA_ISO_FIRST)
1475 #define G_CPL_TX_DATA_ISO_FIRST(x) \
1476 (((x) >> S_CPL_TX_DATA_ISO_FIRST) & M_CPL_TX_DATA_ISO_FIRST)
1477 #define F_CPL_TX_DATA_ISO_FIRST V_CPL_TX_DATA_ISO_FIRST(1U)
1478
1479 #define S_CPL_TX_DATA_ISO_LAST 22
1480 #define M_CPL_TX_DATA_ISO_LAST 0x1
1481 #define V_CPL_TX_DATA_ISO_LAST(x) ((x) << S_CPL_TX_DATA_ISO_LAST)
1482 #define G_CPL_TX_DATA_ISO_LAST(x) \
1483 (((x) >> S_CPL_TX_DATA_ISO_LAST) & M_CPL_TX_DATA_ISO_LAST)
1484 #define F_CPL_TX_DATA_ISO_LAST V_CPL_TX_DATA_ISO_LAST(1U)
1485
1486 #define S_CPL_TX_DATA_ISO_CPLHDRLEN 21
1487 #define M_CPL_TX_DATA_ISO_CPLHDRLEN 0x1
1488 #define V_CPL_TX_DATA_ISO_CPLHDRLEN(x) ((x) << S_CPL_TX_DATA_ISO_CPLHDRLEN)
1489 #define G_CPL_TX_DATA_ISO_CPLHDRLEN(x) \
1490 (((x) >> S_CPL_TX_DATA_ISO_CPLHDRLEN) & M_CPL_TX_DATA_ISO_CPLHDRLEN)
1491 #define F_CPL_TX_DATA_ISO_CPLHDRLEN V_CPL_TX_DATA_ISO_CPLHDRLEN(1U)
1492
1493 #define S_CPL_TX_DATA_ISO_HDRCRC 20
1494 #define M_CPL_TX_DATA_ISO_HDRCRC 0x1
1495 #define V_CPL_TX_DATA_ISO_HDRCRC(x) ((x) << S_CPL_TX_DATA_ISO_HDRCRC)
1496 #define G_CPL_TX_DATA_ISO_HDRCRC(x) \
1497 (((x) >> S_CPL_TX_DATA_ISO_HDRCRC) & M_CPL_TX_DATA_ISO_HDRCRC)
1498 #define F_CPL_TX_DATA_ISO_HDRCRC V_CPL_TX_DATA_ISO_HDRCRC(1U)
1499
1500 #define S_CPL_TX_DATA_ISO_PLDCRC 19
1501 #define M_CPL_TX_DATA_ISO_PLDCRC 0x1
1502 #define V_CPL_TX_DATA_ISO_PLDCRC(x) ((x) << S_CPL_TX_DATA_ISO_PLDCRC)
1503 #define G_CPL_TX_DATA_ISO_PLDCRC(x) \
1504 (((x) >> S_CPL_TX_DATA_ISO_PLDCRC) & M_CPL_TX_DATA_ISO_PLDCRC)
1505 #define F_CPL_TX_DATA_ISO_PLDCRC V_CPL_TX_DATA_ISO_PLDCRC(1U)
1506
1507 #define S_CPL_TX_DATA_ISO_IMMEDIATE 18
1508 #define M_CPL_TX_DATA_ISO_IMMEDIATE 0x1
1509 #define V_CPL_TX_DATA_ISO_IMMEDIATE(x) ((x) << S_CPL_TX_DATA_ISO_IMMEDIATE)
1510 #define G_CPL_TX_DATA_ISO_IMMEDIATE(x) \
1511 (((x) >> S_CPL_TX_DATA_ISO_IMMEDIATE) & M_CPL_TX_DATA_ISO_IMMEDIATE)
1512 #define F_CPL_TX_DATA_ISO_IMMEDIATE V_CPL_TX_DATA_ISO_IMMEDIATE(1U)
1513
1514 #define S_CPL_TX_DATA_ISO_SCSI 16
1515 #define M_CPL_TX_DATA_ISO_SCSI 0x3
1516 #define V_CPL_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_TX_DATA_ISO_SCSI)
1517 #define G_CPL_TX_DATA_ISO_SCSI(x) \
1518 (((x) >> S_CPL_TX_DATA_ISO_SCSI) & M_CPL_TX_DATA_ISO_SCSI)
1519
1520 /* cpl_tx_data_iso.reserved2_seglen_offset fields */
1521 #define S_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0
1522 #define M_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0xffffff
1523 #define V_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \
1524 ((x) << S_CPL_TX_DATA_ISO_SEGLEN_OFFSET)
1525 #define G_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \
1526 (((x) >> S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) & \
1527 M_CPL_TX_DATA_ISO_SEGLEN_OFFSET)
1528
1529 struct cpl_iscsi_hdr {
1530 RSS_HDR
1531 union opcode_tid ot;
1532 __be16 pdu_len_ddp;
1533 __be16 len;
1534 __be32 seq;
1535 __be16 urg;
1536 __u8 rsvd;
1537 __u8 status;
1538 };
1539
1540 /* cpl_iscsi_hdr.pdu_len_ddp fields */
1541 #define S_ISCSI_PDU_LEN 0
1542 #define M_ISCSI_PDU_LEN 0x7FFF
1543 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
1544 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
1545
1546 #define S_ISCSI_DDP 15
1547 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
1548 #define F_ISCSI_DDP V_ISCSI_DDP(1U)
1549
1550 struct cpl_iscsi_data {
1551 RSS_HDR
1552 union opcode_tid ot;
1553 __u8 rsvd0[2];
1554 __be16 len;
1555 __be32 seq;
1556 __be16 urg;
1557 __u8 rsvd1;
1558 __u8 status;
1559 };
1560
1561 struct cpl_rx_data {
1562 RSS_HDR
1563 union opcode_tid ot;
1564 __be16 rsvd;
1565 __be16 len;
1566 __be32 seq;
1567 __be16 urg;
1568 #if defined(__LITTLE_ENDIAN_BITFIELD)
1569 __u8 dack_mode:2;
1570 __u8 psh:1;
1571 __u8 heartbeat:1;
1572 __u8 ddp_off:1;
1573 __u8 :3;
1574 #else
1575 __u8 :3;
1576 __u8 ddp_off:1;
1577 __u8 heartbeat:1;
1578 __u8 psh:1;
1579 __u8 dack_mode:2;
1580 #endif
1581 __u8 status;
1582 };
1583
1584 struct cpl_fcoe_hdr {
1585 RSS_HDR
1586 union opcode_tid ot;
1587 __be16 oxid;
1588 __be16 len;
1589 __be32 rctl_fctl;
1590 __u8 cs_ctl;
1591 __u8 df_ctl;
1592 __u8 sof;
1593 __u8 eof;
1594 __be16 seq_cnt;
1595 __u8 seq_id;
1596 __u8 type;
1597 __be32 param;
1598 };
1599
1600 /* cpl_fcoe_hdr.rctl_fctl fields */
1601 #define S_FCOE_FCHDR_RCTL 24
1602 #define M_FCOE_FCHDR_RCTL 0xff
1603 #define V_FCOE_FCHDR_RCTL(x) ((x) << S_FCOE_FCHDR_RCTL)
1604 #define G_FCOE_FCHDR_RCTL(x) \
1605 (((x) >> S_FCOE_FCHDR_RCTL) & M_FCOE_FCHDR_RCTL)
1606
1607 #define S_FCOE_FCHDR_FCTL 0
1608 #define M_FCOE_FCHDR_FCTL 0xffffff
1609 #define V_FCOE_FCHDR_FCTL(x) ((x) << S_FCOE_FCHDR_FCTL)
1610 #define G_FCOE_FCHDR_FCTL(x) \
1611 (((x) >> S_FCOE_FCHDR_FCTL) & M_FCOE_FCHDR_FCTL)
1612
1613 struct cpl_fcoe_data {
1614 RSS_HDR
1615 union opcode_tid ot;
1616 __u8 rsvd0[2];
1617 __be16 len;
1618 __be32 seq;
1619 __u8 rsvd1[3];
1620 __u8 status;
1621 };
1622
1623 struct cpl_rx_urg_notify {
1624 RSS_HDR
1625 union opcode_tid ot;
1626 __be32 seq;
1627 };
1628
1629 struct cpl_rx_urg_pkt {
1630 RSS_HDR
1631 union opcode_tid ot;
1632 __be16 rsvd;
1633 __be16 len;
1634 };
1635
1636 struct cpl_rx_data_ack {
1637 WR_HDR;
1638 union opcode_tid ot;
1639 __be32 credit_dack;
1640 };
1641
1642 /* cpl_rx_data_ack.ack_seq fields */
1643 #define S_RX_CREDITS 0
1644 #define M_RX_CREDITS 0x3FFFFFF
1645 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
1646 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
1647
1648 #define S_RX_MODULATE_TX 26
1649 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX)
1650 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U)
1651
1652 #define S_RX_MODULATE_RX 27
1653 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX)
1654 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U)
1655
1656 #define S_RX_FORCE_ACK 28
1657 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
1658 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U)
1659
1660 #define S_RX_DACK_MODE 29
1661 #define M_RX_DACK_MODE 0x3
1662 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
1663 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
1664
1665 #define S_RX_DACK_CHANGE 31
1666 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
1667 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U)
1668
1669 struct cpl_rx_ddp_complete {
1670 RSS_HDR
1671 union opcode_tid ot;
1672 __be32 ddp_report;
1673 __be32 rcv_nxt;
1674 __be32 rsvd;
1675 };
1676
1677 struct cpl_rx_data_ddp {
1678 RSS_HDR
1679 union opcode_tid ot;
1680 __be16 urg;
1681 __be16 len;
1682 __be32 seq;
1683 union {
1684 __be32 nxt_seq;
1685 __be32 ddp_report;
1686 };
1687 __be32 ulp_crc;
1688 __be32 ddpvld;
1689 };
1690
1691 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp
1692
1693 struct cpl_rx_fcoe_ddp {
1694 RSS_HDR
1695 union opcode_tid ot;
1696 __be16 rsvd;
1697 __be16 len;
1698 __be32 seq;
1699 __be32 ddp_report;
1700 __be32 ulp_crc;
1701 __be32 ddpvld;
1702 };
1703
1704 struct cpl_rx_data_dif {
1705 RSS_HDR
1706 union opcode_tid ot;
1707 __be16 ddp_len;
1708 __be16 msg_len;
1709 __be32 seq;
1710 union {
1711 __be32 nxt_seq;
1712 __be32 ddp_report;
1713 };
1714 __be32 err_vec;
1715 __be32 ddpvld;
1716 };
1717
1718 struct cpl_rx_iscsi_dif {
1719 RSS_HDR
1720 union opcode_tid ot;
1721 __be16 ddp_len;
1722 __be16 msg_len;
1723 __be32 seq;
1724 union {
1725 __be32 nxt_seq;
1726 __be32 ddp_report;
1727 };
1728 __be32 ulp_crc;
1729 __be32 ddpvld;
1730 __u8 rsvd0[8];
1731 __be32 err_vec;
1732 __u8 rsvd1[4];
1733 };
1734
1735 struct cpl_rx_iscsi_cmp {
1736 RSS_HDR
1737 union opcode_tid ot;
1738 __be16 pdu_len_ddp;
1739 __be16 len;
1740 __be32 seq;
1741 __be16 urg;
1742 __u8 rsvd;
1743 __u8 status;
1744 __be32 ulp_crc;
1745 __be32 ddpvld;
1746 };
1747
1748 struct cpl_rx_fcoe_dif {
1749 RSS_HDR
1750 union opcode_tid ot;
1751 __be16 ddp_len;
1752 __be16 msg_len;
1753 __be32 seq;
1754 __be32 ddp_report;
1755 __be32 err_vec;
1756 __be32 ddpvld;
1757 };
1758
1759 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */
1760 #define S_DDP_VALID 15
1761 #define M_DDP_VALID 0x1FFFF
1762 #define V_DDP_VALID(x) ((x) << S_DDP_VALID)
1763 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
1764
1765 #define S_DDP_PPOD_MISMATCH 15
1766 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
1767 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U)
1768
1769 #define S_DDP_PDU 16
1770 #define V_DDP_PDU(x) ((x) << S_DDP_PDU)
1771 #define F_DDP_PDU V_DDP_PDU(1U)
1772
1773 #define S_DDP_LLIMIT_ERR 17
1774 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
1775 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U)
1776
1777 #define S_DDP_PPOD_PARITY_ERR 18
1778 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
1779 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U)
1780
1781 #define S_DDP_PADDING_ERR 19
1782 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
1783 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U)
1784
1785 #define S_DDP_HDRCRC_ERR 20
1786 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
1787 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U)
1788
1789 #define S_DDP_DATACRC_ERR 21
1790 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
1791 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U)
1792
1793 #define S_DDP_INVALID_TAG 22
1794 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
1795 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U)
1796
1797 #define S_DDP_ULIMIT_ERR 23
1798 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
1799 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U)
1800
1801 #define S_DDP_OFFSET_ERR 24
1802 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
1803 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U)
1804
1805 #define S_DDP_COLOR_ERR 25
1806 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
1807 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U)
1808
1809 #define S_DDP_TID_MISMATCH 26
1810 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
1811 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U)
1812
1813 #define S_DDP_INVALID_PPOD 27
1814 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
1815 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U)
1816
1817 #define S_DDP_ULP_MODE 28
1818 #define M_DDP_ULP_MODE 0xF
1819 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
1820 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
1821
1822 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */
1823 #define S_DDP_OFFSET 0
1824 #define M_DDP_OFFSET 0xFFFFFF
1825 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
1826 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
1827
1828 #define S_DDP_DACK_MODE 24
1829 #define M_DDP_DACK_MODE 0x3
1830 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE)
1831 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE)
1832
1833 #define S_DDP_BUF_IDX 26
1834 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
1835 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U)
1836
1837 #define S_DDP_URG 27
1838 #define V_DDP_URG(x) ((x) << S_DDP_URG)
1839 #define F_DDP_URG V_DDP_URG(1U)
1840
1841 #define S_DDP_PSH 28
1842 #define V_DDP_PSH(x) ((x) << S_DDP_PSH)
1843 #define F_DDP_PSH V_DDP_PSH(1U)
1844
1845 #define S_DDP_BUF_COMPLETE 29
1846 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
1847 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U)
1848
1849 #define S_DDP_BUF_TIMED_OUT 30
1850 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
1851 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U)
1852
1853 #define S_DDP_INV 31
1854 #define V_DDP_INV(x) ((x) << S_DDP_INV)
1855 #define F_DDP_INV V_DDP_INV(1U)
1856
1857 struct cpl_rx_pkt {
1858 RSS_HDR
1859 __u8 opcode;
1860 #if defined(__LITTLE_ENDIAN_BITFIELD)
1861 __u8 iff:4;
1862 __u8 csum_calc:1;
1863 __u8 ipmi_pkt:1;
1864 __u8 vlan_ex:1;
1865 __u8 ip_frag:1;
1866 #else
1867 __u8 ip_frag:1;
1868 __u8 vlan_ex:1;
1869 __u8 ipmi_pkt:1;
1870 __u8 csum_calc:1;
1871 __u8 iff:4;
1872 #endif
1873 __be16 csum;
1874 __be16 vlan;
1875 __be16 len;
1876 __be32 l2info;
1877 __be16 hdr_len;
1878 __be16 err_vec;
1879 };
1880
1881 /* rx_pkt.l2info fields */
1882 #define S_RX_ETHHDR_LEN 0
1883 #define M_RX_ETHHDR_LEN 0x1F
1884 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN)
1885 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN)
1886
1887 #define S_RX_T5_ETHHDR_LEN 0
1888 #define M_RX_T5_ETHHDR_LEN 0x3F
1889 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN)
1890 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN)
1891
1892 #define M_RX_T6_ETHHDR_LEN 0xFF
1893 #define G_RX_T6_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_T6_ETHHDR_LEN)
1894
1895 #define S_RX_PKTYPE 5
1896 #define M_RX_PKTYPE 0x7
1897 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE)
1898 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE)
1899
1900 #define S_RX_T5_DATYPE 6
1901 #define M_RX_T5_DATYPE 0x3
1902 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE)
1903 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE)
1904
1905 #define S_RX_MACIDX 8
1906 #define M_RX_MACIDX 0x1FF
1907 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX)
1908 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX)
1909
1910 #define S_RX_T5_PKTYPE 17
1911 #define M_RX_T5_PKTYPE 0x7
1912 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE)
1913 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE)
1914
1915 #define S_RX_DATYPE 18
1916 #define M_RX_DATYPE 0x3
1917 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE)
1918 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE)
1919
1920 #define S_RXF_PSH 20
1921 #define V_RXF_PSH(x) ((x) << S_RXF_PSH)
1922 #define F_RXF_PSH V_RXF_PSH(1U)
1923
1924 #define S_RXF_SYN 21
1925 #define V_RXF_SYN(x) ((x) << S_RXF_SYN)
1926 #define F_RXF_SYN V_RXF_SYN(1U)
1927
1928 #define S_RXF_UDP 22
1929 #define V_RXF_UDP(x) ((x) << S_RXF_UDP)
1930 #define F_RXF_UDP V_RXF_UDP(1U)
1931
1932 #define S_RXF_TCP 23
1933 #define V_RXF_TCP(x) ((x) << S_RXF_TCP)
1934 #define F_RXF_TCP V_RXF_TCP(1U)
1935
1936 #define S_RXF_IP 24
1937 #define V_RXF_IP(x) ((x) << S_RXF_IP)
1938 #define F_RXF_IP V_RXF_IP(1U)
1939
1940 #define S_RXF_IP6 25
1941 #define V_RXF_IP6(x) ((x) << S_RXF_IP6)
1942 #define F_RXF_IP6 V_RXF_IP6(1U)
1943
1944 #define S_RXF_SYN_COOKIE 26
1945 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE)
1946 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U)
1947
1948 #define S_RXF_FCOE 26
1949 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE)
1950 #define F_RXF_FCOE V_RXF_FCOE(1U)
1951
1952 #define S_RXF_LRO 27
1953 #define V_RXF_LRO(x) ((x) << S_RXF_LRO)
1954 #define F_RXF_LRO V_RXF_LRO(1U)
1955
1956 #define S_RX_CHAN 28
1957 #define M_RX_CHAN 0xF
1958 #define V_RX_CHAN(x) ((x) << S_RX_CHAN)
1959 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN)
1960
1961 /* rx_pkt.hdr_len fields */
1962 #define S_RX_TCPHDR_LEN 0
1963 #define M_RX_TCPHDR_LEN 0x3F
1964 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN)
1965 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN)
1966
1967 #define S_RX_IPHDR_LEN 6
1968 #define M_RX_IPHDR_LEN 0x3FF
1969 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN)
1970 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN)
1971
1972 /* rx_pkt.err_vec fields */
1973 #define S_RXERR_OR 0
1974 #define V_RXERR_OR(x) ((x) << S_RXERR_OR)
1975 #define F_RXERR_OR V_RXERR_OR(1U)
1976
1977 #define S_RXERR_MAC 1
1978 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC)
1979 #define F_RXERR_MAC V_RXERR_MAC(1U)
1980
1981 #define S_RXERR_IPVERS 2
1982 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS)
1983 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U)
1984
1985 #define S_RXERR_FRAG 3
1986 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG)
1987 #define F_RXERR_FRAG V_RXERR_FRAG(1U)
1988
1989 #define S_RXERR_ATTACK 4
1990 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK)
1991 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U)
1992
1993 #define S_RXERR_ETHHDR_LEN 5
1994 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN)
1995 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U)
1996
1997 #define S_RXERR_IPHDR_LEN 6
1998 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN)
1999 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U)
2000
2001 #define S_RXERR_TCPHDR_LEN 7
2002 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN)
2003 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U)
2004
2005 #define S_RXERR_PKT_LEN 8
2006 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN)
2007 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U)
2008
2009 #define S_RXERR_TCP_OPT 9
2010 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT)
2011 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U)
2012
2013 #define S_RXERR_IPCSUM 12
2014 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM)
2015 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U)
2016
2017 #define S_RXERR_CSUM 13
2018 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM)
2019 #define F_RXERR_CSUM V_RXERR_CSUM(1U)
2020
2021 #define S_RXERR_PING 14
2022 #define V_RXERR_PING(x) ((x) << S_RXERR_PING)
2023 #define F_RXERR_PING V_RXERR_PING(1U)
2024
2025 /* In T6, rx_pkt.err_vec indicates
2026 * RxError Error vector (16b) or
2027 * Encapsulating header length (8b),
2028 * Outer encapsulation type (2b) and
2029 * compressed error vector (6b) if CRxPktEnc is
2030 * enabled in TP_OUT_CONFIG
2031 */
2032
2033 #define S_T6_COMPR_RXERR_VEC 0
2034 #define M_T6_COMPR_RXERR_VEC 0x3F
2035 #define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC)
2036 #define G_T6_COMPR_RXERR_VEC(x) \
2037 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC)
2038
2039 #define S_T6_COMPR_RXERR_MAC 0
2040 #define V_T6_COMPR_RXERR_MAC(x) ((x) << S_T6_COMPR_RXERR_MAC)
2041 #define F_T6_COMPR_RXERR_MAC V_T6_COMPR_RXERR_MAC(1U)
2042
2043 /* Logical OR of RX_ERROR_PKT_LEN, RX_ERROR_TCP_HDR_LEN
2044 * RX_ERROR_IP_HDR_LEN, RX_ERROR_ETH_HDR_LEN
2045 */
2046 #define S_T6_COMPR_RXERR_LEN 1
2047 #define V_T6_COMPR_RXERR_LEN(x) ((x) << S_T6_COMPR_RXERR_LEN)
2048 #define F_T6_COMPR_RXERR_LEN V_COMPR_T6_RXERR_LEN(1U)
2049
2050 #define S_T6_COMPR_RXERR_TCP_OPT 2
2051 #define V_T6_COMPR_RXERR_TCP_OPT(x) ((x) << S_T6_COMPR_RXERR_TCP_OPT)
2052 #define F_T6_COMPR_RXERR_TCP_OPT V_T6_COMPR_RXERR_TCP_OPT(1U)
2053
2054 #define S_T6_COMPR_RXERR_IPV6_EXT 3
2055 #define V_T6_COMPR_RXERR_IPV6_EXT(x) ((x) << S_T6_COMPR_RXERR_IPV6_EXT)
2056 #define F_T6_COMPR_RXERR_IPV6_EXT V_T6_COMPR_RXERR_IPV6_EXT(1U)
2057
2058 /* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */
2059 #define S_T6_COMPR_RXERR_SUM 4
2060 #define V_T6_COMPR_RXERR_SUM(x) ((x) << S_T6_COMPR_RXERR_SUM)
2061 #define F_T6_COMPR_RXERR_SUM V_T6_COMPR_RXERR_SUM(1U)
2062
2063 /* Logical OR of RX_ERROR_FPMA, RX_ERROR_PING_DROP,
2064 * RX_ERROR_ATTACK, RX_ERROR_FRAG,RX_ERROR_IPVERSION
2065 */
2066 #define S_T6_COMPR_RXERR_MISC 5
2067 #define V_T6_COMPR_RXERR_MISC(x) ((x) << S_T6_COMPR_RXERR_MISC)
2068 #define F_T6_COMPR_RXERR_MISC V_T6_COMPR_RXERR_MISC(1U)
2069
2070 #define S_T6_RX_TNL_TYPE 6
2071 #define M_T6_RX_TNL_TYPE 0x3
2072 #define V_T6_RX_TNL_TYPE(x) ((x) << S_T6_RX_TNL_TYPE)
2073 #define G_T6_RX_TNL_TYPE(x) (((x) >> S_T6_RX_TNL_TYPE) & M_T6_RX_TNL_TYPE)
2074
2075 #define RX_PKT_TNL_TYPE_NVGRE 1
2076 #define RX_PKT_TNL_TYPE_VXLAN 2
2077 #define RX_PKT_TNL_TYPE_GENEVE 3
2078
2079 #define S_T6_RX_TNLHDR_LEN 8
2080 #define M_T6_RX_TNLHDR_LEN 0xFF
2081 #define V_T6_RX_TNLHDR_LEN(x) ((x) << S_T6_RX_TNLHDR_LEN)
2082 #define G_T6_RX_TNLHDR_LEN(x) (((x) >> S_T6_RX_TNLHDR_LEN) & M_T6_RX_TNLHDR_LEN)
2083
2084 struct cpl_trace_pkt {
2085 RSS_HDR
2086 __u8 opcode;
2087 __u8 intf;
2088 #if defined(__LITTLE_ENDIAN_BITFIELD)
2089 __u8 runt:4;
2090 __u8 filter_hit:4;
2091 __u8 :6;
2092 __u8 err:1;
2093 __u8 trunc:1;
2094 #else
2095 __u8 filter_hit:4;
2096 __u8 runt:4;
2097 __u8 trunc:1;
2098 __u8 err:1;
2099 __u8 :6;
2100 #endif
2101 __be16 rsvd;
2102 __be16 len;
2103 __be64 tstamp;
2104 };
2105
2106 struct cpl_t5_trace_pkt {
2107 RSS_HDR
2108 __u8 opcode;
2109 __u8 intf;
2110 #if defined(__LITTLE_ENDIAN_BITFIELD)
2111 __u8 runt:4;
2112 __u8 filter_hit:4;
2113 __u8 :6;
2114 __u8 err:1;
2115 __u8 trunc:1;
2116 #else
2117 __u8 filter_hit:4;
2118 __u8 runt:4;
2119 __u8 trunc:1;
2120 __u8 err:1;
2121 __u8 :6;
2122 #endif
2123 __be16 rsvd;
2124 __be16 len;
2125 __be64 tstamp;
2126 __be64 rsvd1;
2127 };
2128
2129 struct cpl_rte_delete_req {
2130 WR_HDR;
2131 union opcode_tid ot;
2132 __be32 params;
2133 };
2134
2135 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */
2136 #define S_RTE_REQ_LUT_IX 8
2137 #define M_RTE_REQ_LUT_IX 0x7FF
2138 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
2139 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
2140
2141 #define S_RTE_REQ_LUT_BASE 19
2142 #define M_RTE_REQ_LUT_BASE 0x7FF
2143 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
2144 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
2145
2146 #define S_RTE_READ_REQ_SELECT 31
2147 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
2148 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U)
2149
2150 struct cpl_rte_delete_rpl {
2151 RSS_HDR
2152 union opcode_tid ot;
2153 __u8 status;
2154 __u8 rsvd[3];
2155 };
2156
2157 struct cpl_rte_write_req {
2158 WR_HDR;
2159 union opcode_tid ot;
2160 __u32 write_sel;
2161 __be32 lut_params;
2162 __be32 l2t_idx;
2163 __be32 netmask;
2164 __be32 faddr;
2165 };
2166
2167 /* cpl_rte_write_req.write_sel fields */
2168 #define S_RTE_WR_L2TIDX 31
2169 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX)
2170 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U)
2171
2172 #define S_RTE_WR_FADDR 30
2173 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR)
2174 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U)
2175
2176 /* cpl_rte_write_req.lut_params fields */
2177 #define S_RTE_WR_LUT_IX 10
2178 #define M_RTE_WR_LUT_IX 0x7FF
2179 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX)
2180 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX)
2181
2182 #define S_RTE_WR_LUT_BASE 21
2183 #define M_RTE_WR_LUT_BASE 0x7FF
2184 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE)
2185 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE)
2186
2187 struct cpl_rte_write_rpl {
2188 RSS_HDR
2189 union opcode_tid ot;
2190 __u8 status;
2191 __u8 rsvd[3];
2192 };
2193
2194 struct cpl_rte_read_req {
2195 WR_HDR;
2196 union opcode_tid ot;
2197 __be32 params;
2198 };
2199
2200 struct cpl_rte_read_rpl {
2201 RSS_HDR
2202 union opcode_tid ot;
2203 __u8 status;
2204 __u8 rsvd;
2205 __be16 l2t_idx;
2206 #if defined(__LITTLE_ENDIAN_BITFIELD)
2207 __u32 :30;
2208 __u32 select:1;
2209 #else
2210 __u32 select:1;
2211 __u32 :30;
2212 #endif
2213 __be32 addr;
2214 };
2215
2216 struct cpl_l2t_write_req {
2217 WR_HDR;
2218 union opcode_tid ot;
2219 __be16 params;
2220 __be16 l2t_idx;
2221 __be16 vlan;
2222 __u8 dst_mac[6];
2223 };
2224
2225 /* cpl_l2t_write_req.params fields */
2226 #define S_L2T_W_INFO 2
2227 #define M_L2T_W_INFO 0x3F
2228 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO)
2229 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO)
2230
2231 #define S_L2T_W_PORT 8
2232 #define M_L2T_W_PORT 0x3
2233 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT)
2234 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT)
2235
2236 #define S_L2T_W_LPBK 10
2237 #define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK)
2238 #define F_L2T_W_PKBK V_L2T_W_LPBK(1U)
2239
2240 #define S_L2T_W_ARPMISS 11
2241 #define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS)
2242 #define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U)
2243
2244 #define S_L2T_W_NOREPLY 15
2245 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY)
2246 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U)
2247
2248
2249 /* cpl_l2t_write_req.vlan fields */
2250 #define S_L2T_VLANTAG 0
2251 #define M_L2T_VLANTAG 0xFFF
2252 #define V_L2T_VLANTAG(x) ((x) << S_L2T_VLANTAG)
2253 #define G_L2T_VLANTAG(x) (((x) >> S_L2T_VLANTAG) & M_L2T_VLANTAG)
2254
2255 #define S_L2T_VLANPRIO 13
2256 #define M_L2T_VLANPRIO 0x7
2257 #define V_L2T_VLANPRIO(x) ((x) << S_L2T_VLANPRIO)
2258 #define G_L2T_VLANPRIO(x) (((x) >> S_L2T_VLANPRIO) & M_L2T_VLANPRIO)
2259
2260 #define CPL_L2T_VLAN_NONE 0xfff
2261
2262 struct cpl_l2t_write_rpl {
2263 RSS_HDR
2264 union opcode_tid ot;
2265 __u8 status;
2266 __u8 rsvd[3];
2267 };
2268
2269 struct cpl_l2t_read_req {
2270 WR_HDR;
2271 union opcode_tid ot;
2272 __be32 l2t_idx;
2273 };
2274
2275 struct cpl_l2t_read_rpl {
2276 RSS_HDR
2277 union opcode_tid ot;
2278 __u8 status;
2279 #if defined(__LITTLE_ENDIAN_BITFIELD)
2280 __u8 :4;
2281 __u8 iff:4;
2282 #else
2283 __u8 iff:4;
2284 __u8 :4;
2285 #endif
2286 __be16 vlan;
2287 __be16 info;
2288 __u8 dst_mac[6];
2289 };
2290
2291 struct cpl_srq_table_req {
2292 WR_HDR;
2293 union opcode_tid ot;
2294 __u8 status;
2295 __u8 rsvd[2];
2296 __u8 idx;
2297 __be64 rsvd_pdid;
2298 __be32 qlen_qbase;
2299 __be16 cur_msn;
2300 __be16 max_msn;
2301 };
2302
2303 struct cpl_srq_table_rpl {
2304 RSS_HDR
2305 union opcode_tid ot;
2306 __u8 status;
2307 __u8 rsvd[2];
2308 __u8 idx;
2309 __be64 rsvd_pdid;
2310 __be32 qlen_qbase;
2311 __be16 cur_msn;
2312 __be16 max_msn;
2313 };
2314
2315 /* cpl_srq_table_{req,rpl}.params fields */
2316 #define S_SRQT_QLEN 28
2317 #define M_SRQT_QLEN 0xF
2318 #define V_SRQT_QLEN(x) ((x) << S_SRQT_QLEN)
2319 #define G_SRQT_QLEN(x) (((x) >> S_SRQT_QLEN) & M_SRQT_QLEN)
2320
2321 #define S_SRQT_QBASE 0
2322 #define M_SRQT_QBASE 0x3FFFFFF
2323 #define V_SRQT_QBASE(x) ((x) << S_SRQT_QBASE)
2324 #define G_SRQT_QBASE(x) (((x) >> S_SRQT_QBASE) & M_SRQT_QBASE)
2325
2326 #define S_SRQT_PDID 0
2327 #define M_SRQT_PDID 0xFF
2328 #define V_SRQT_PDID(x) ((x) << S_SRQT_PDID)
2329 #define G_SRQT_PDID(x) (((x) >> S_SRQT_PDID) & M_SRQT_PDID)
2330
2331 #define S_SRQT_IDX 0
2332 #define M_SRQT_IDX 0xF
2333 #define V_SRQT_IDX(x) ((x) << S_SRQT_IDX)
2334 #define G_SRQT_IDX(x) (((x) >> S_SRQT_IDX) & M_SRQT_IDX)
2335
2336 struct cpl_smt_write_req {
2337 WR_HDR;
2338 union opcode_tid ot;
2339 __be32 params;
2340 __be16 pfvf1;
2341 __u8 src_mac1[6];
2342 __be16 pfvf0;
2343 __u8 src_mac0[6];
2344 };
2345
2346 struct cpl_t6_smt_write_req {
2347 WR_HDR;
2348 union opcode_tid ot;
2349 __be32 params;
2350 __be64 tag;
2351 __be16 pfvf0;
2352 __u8 src_mac0[6];
2353 __be32 local_ip;
2354 __be32 rsvd;
2355 };
2356
2357 struct cpl_smt_write_rpl {
2358 RSS_HDR
2359 union opcode_tid ot;
2360 __u8 status;
2361 __u8 rsvd[3];
2362 };
2363
2364 struct cpl_smt_read_req {
2365 WR_HDR;
2366 union opcode_tid ot;
2367 __be32 params;
2368 };
2369
2370 struct cpl_smt_read_rpl {
2371 RSS_HDR
2372 union opcode_tid ot;
2373 __u8 status;
2374 __u8 ovlan_idx;
2375 __be16 rsvd;
2376 __be16 pfvf1;
2377 __u8 src_mac1[6];
2378 __be16 pfvf0;
2379 __u8 src_mac0[6];
2380 };
2381
2382 /* cpl_smt_{read,write}_req.params fields */
2383 #define S_SMTW_OVLAN_IDX 16
2384 #define M_SMTW_OVLAN_IDX 0xF
2385 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX)
2386 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX)
2387
2388 #define S_SMTW_IDX 20
2389 #define M_SMTW_IDX 0x7F
2390 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX)
2391 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX)
2392
2393 #define M_T6_SMTW_IDX 0xFF
2394 #define G_T6_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_T6_SMTW_IDX)
2395
2396 #define S_SMTW_NORPL 31
2397 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL)
2398 #define F_SMTW_NORPL V_SMTW_NORPL(1U)
2399
2400 /* cpl_smt_{read,write}_req.pfvf? fields */
2401 #define S_SMTW_VF 0
2402 #define M_SMTW_VF 0xFF
2403 #define V_SMTW_VF(x) ((x) << S_SMTW_VF)
2404 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF)
2405
2406 #define S_SMTW_PF 8
2407 #define M_SMTW_PF 0x7
2408 #define V_SMTW_PF(x) ((x) << S_SMTW_PF)
2409 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF)
2410
2411 #define S_SMTW_VF_VLD 11
2412 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD)
2413 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U)
2414
2415 struct cpl_tag_write_req {
2416 WR_HDR;
2417 union opcode_tid ot;
2418 __be32 params;
2419 __be64 tag_val;
2420 };
2421
2422 struct cpl_tag_write_rpl {
2423 RSS_HDR
2424 union opcode_tid ot;
2425 __u8 status;
2426 __u8 rsvd[2];
2427 __u8 idx;
2428 };
2429
2430 struct cpl_tag_read_req {
2431 WR_HDR;
2432 union opcode_tid ot;
2433 __be32 params;
2434 };
2435
2436 struct cpl_tag_read_rpl {
2437 RSS_HDR
2438 union opcode_tid ot;
2439 __u8 status;
2440 #if defined(__LITTLE_ENDIAN_BITFIELD)
2441 __u8 :4;
2442 __u8 tag_len:1;
2443 __u8 :2;
2444 __u8 ins_enable:1;
2445 #else
2446 __u8 ins_enable:1;
2447 __u8 :2;
2448 __u8 tag_len:1;
2449 __u8 :4;
2450 #endif
2451 __u8 rsvd;
2452 __u8 tag_idx;
2453 __be64 tag_val;
2454 };
2455
2456 /* cpl_tag{read,write}_req.params fields */
2457 #define S_TAGW_IDX 0
2458 #define M_TAGW_IDX 0x7F
2459 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX)
2460 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX)
2461
2462 #define S_TAGW_LEN 20
2463 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN)
2464 #define F_TAGW_LEN V_TAGW_LEN(1U)
2465
2466 #define S_TAGW_INS_ENABLE 23
2467 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE)
2468 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U)
2469
2470 #define S_TAGW_NORPL 31
2471 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL)
2472 #define F_TAGW_NORPL V_TAGW_NORPL(1U)
2473
2474 struct cpl_barrier {
2475 WR_HDR;
2476 __u8 opcode;
2477 __u8 chan_map;
2478 __be16 rsvd0;
2479 __be32 rsvd1;
2480 };
2481
2482 /* cpl_barrier.chan_map fields */
2483 #define S_CHAN_MAP 4
2484 #define M_CHAN_MAP 0xF
2485 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP)
2486 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP)
2487
2488 struct cpl_error {
2489 RSS_HDR
2490 union opcode_tid ot;
2491 __be32 error;
2492 };
2493
2494 struct cpl_hit_notify {
2495 RSS_HDR
2496 union opcode_tid ot;
2497 __be32 rsvd;
2498 __be32 info;
2499 __be32 reason;
2500 };
2501
2502 struct cpl_pkt_notify {
2503 RSS_HDR
2504 union opcode_tid ot;
2505 __be16 rsvd;
2506 __be16 len;
2507 __be32 info;
2508 __be32 reason;
2509 };
2510
2511 /* cpl_{hit,pkt}_notify.info fields */
2512 #define S_NTFY_MAC_IDX 0
2513 #define M_NTFY_MAC_IDX 0x1FF
2514 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX)
2515 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX)
2516
2517 #define S_NTFY_INTF 10
2518 #define M_NTFY_INTF 0xF
2519 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF)
2520 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF)
2521
2522 #define S_NTFY_TCPHDR_LEN 14
2523 #define M_NTFY_TCPHDR_LEN 0xF
2524 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN)
2525 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN)
2526
2527 #define S_NTFY_IPHDR_LEN 18
2528 #define M_NTFY_IPHDR_LEN 0x1FF
2529 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN)
2530 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN)
2531
2532 #define S_NTFY_ETHHDR_LEN 27
2533 #define M_NTFY_ETHHDR_LEN 0x1F
2534 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN)
2535 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN)
2536
2537 #define S_NTFY_T5_IPHDR_LEN 18
2538 #define M_NTFY_T5_IPHDR_LEN 0xFF
2539 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN)
2540 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN)
2541
2542 #define S_NTFY_T5_ETHHDR_LEN 26
2543 #define M_NTFY_T5_ETHHDR_LEN 0x3F
2544 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN)
2545 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN)
2546
2547 struct cpl_rdma_terminate {
2548 RSS_HDR
2549 union opcode_tid ot;
2550 __be16 rsvd;
2551 __be16 len;
2552 };
2553
2554 struct cpl_set_le_req {
2555 WR_HDR;
2556 union opcode_tid ot;
2557 __be16 reply_ctrl;
2558 __be16 params;
2559 __be64 mask_hi;
2560 __be64 mask_lo;
2561 __be64 val_hi;
2562 __be64 val_lo;
2563 };
2564
2565 /* cpl_set_le_req.reply_ctrl additional fields */
2566 #define S_LE_REQ_IP6 13
2567 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6)
2568 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U)
2569
2570 /* cpl_set_le_req.params fields */
2571 #define S_LE_CHAN 0
2572 #define M_LE_CHAN 0x3
2573 #define V_LE_CHAN(x) ((x) << S_LE_CHAN)
2574 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN)
2575
2576 #define S_LE_OFFSET 5
2577 #define M_LE_OFFSET 0x7
2578 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET)
2579 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET)
2580
2581 #define S_LE_MORE 8
2582 #define V_LE_MORE(x) ((x) << S_LE_MORE)
2583 #define F_LE_MORE V_LE_MORE(1U)
2584
2585 #define S_LE_REQSIZE 9
2586 #define M_LE_REQSIZE 0x7
2587 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE)
2588 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE)
2589
2590 #define S_LE_REQCMD 12
2591 #define M_LE_REQCMD 0xF
2592 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD)
2593 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD)
2594
2595 struct cpl_set_le_rpl {
2596 RSS_HDR
2597 union opcode_tid ot;
2598 __u8 chan;
2599 __u8 info;
2600 __be16 len;
2601 };
2602
2603 /* cpl_set_le_rpl.info fields */
2604 #define S_LE_RSPCMD 0
2605 #define M_LE_RSPCMD 0xF
2606 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD)
2607 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD)
2608
2609 #define S_LE_RSPSIZE 4
2610 #define M_LE_RSPSIZE 0x7
2611 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE)
2612 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE)
2613
2614 #define S_LE_RSPTYPE 7
2615 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE)
2616 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U)
2617
2618 struct cpl_sge_egr_update {
2619 RSS_HDR
2620 __be32 opcode_qid;
2621 __be16 cidx;
2622 __be16 pidx;
2623 };
2624
2625 /* cpl_sge_egr_update.ot fields */
2626 #define S_AUTOEQU 22
2627 #define M_AUTOEQU 0x1
2628 #define V_AUTOEQU(x) ((x) << S_AUTOEQU)
2629 #define G_AUTOEQU(x) (((x) >> S_AUTOEQU) & M_AUTOEQU)
2630
2631 #define S_EGR_QID 0
2632 #define M_EGR_QID 0x1FFFF
2633 #define V_EGR_QID(x) ((x) << S_EGR_QID)
2634 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID)
2635
2636 /* cpl_fw*.type values */
2637 enum {
2638 FW_TYPE_CMD_RPL = 0,
2639 FW_TYPE_WR_RPL = 1,
2640 FW_TYPE_CQE = 2,
2641 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
2642 FW_TYPE_RSSCPL = 4,
2643 FW_TYPE_WRERR_RPL = 5,
2644 FW_TYPE_PI_ERR = 6,
2645 FW_TYPE_TLS_KEY = 7,
2646 };
2647
2648 struct cpl_fw2_pld {
2649 RSS_HDR
2650 u8 opcode;
2651 u8 rsvd[5];
2652 __be16 len;
2653 };
2654
2655 struct cpl_fw4_pld {
2656 RSS_HDR
2657 u8 opcode;
2658 u8 rsvd0[3];
2659 u8 type;
2660 u8 rsvd1;
2661 __be16 len;
2662 __be64 data;
2663 __be64 rsvd2;
2664 };
2665
2666 struct cpl_fw6_pld {
2667 RSS_HDR
2668 u8 opcode;
2669 u8 rsvd[5];
2670 __be16 len;
2671 __be64 data[4];
2672 };
2673
2674 struct cpl_fw2_msg {
2675 RSS_HDR
2676 union opcode_info oi;
2677 };
2678
2679 struct cpl_fw4_msg {
2680 RSS_HDR
2681 u8 opcode;
2682 u8 type;
2683 __be16 rsvd0;
2684 __be32 rsvd1;
2685 __be64 data[2];
2686 };
2687
2688 struct cpl_fw4_ack {
2689 RSS_HDR
2690 union opcode_tid ot;
2691 u8 credits;
2692 u8 rsvd0[2];
2693 u8 flags;
2694 __be32 snd_nxt;
2695 __be32 snd_una;
2696 __be64 rsvd1;
2697 };
2698
2699 enum {
2700 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */
2701 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */
2702 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */
2703 };
2704
2705 struct cpl_fw6_msg {
2706 RSS_HDR
2707 u8 opcode;
2708 u8 type;
2709 __be16 rsvd0;
2710 __be32 rsvd1;
2711 __be64 data[4];
2712 };
2713
2714 /* cpl_fw6_msg.type values */
2715 enum {
2716 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL,
2717 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL,
2718 FW6_TYPE_CQE = FW_TYPE_CQE,
2719 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL,
2720 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
2721 FW6_TYPE_WRERR_RPL = FW_TYPE_WRERR_RPL,
2722 FW6_TYPE_PI_ERR = FW_TYPE_PI_ERR,
2723 };
2724
2725 struct cpl_fw6_msg_ofld_connection_wr_rpl {
2726 __u64 cookie;
2727 __be32 tid; /* or atid in case of active failure */
2728 __u8 t_state;
2729 __u8 retval;
2730 __u8 rsvd[2];
2731 };
2732
2733 /* ULP_TX opcodes */
2734 enum {
2735 ULP_TX_MEM_READ = 2,
2736 ULP_TX_MEM_WRITE = 3,
2737 ULP_TX_PKT = 4
2738 };
2739
2740 enum {
2741 ULP_TX_SC_NOOP = 0x80,
2742 ULP_TX_SC_IMM = 0x81,
2743 ULP_TX_SC_DSGL = 0x82,
2744 ULP_TX_SC_ISGL = 0x83,
2745 ULP_TX_SC_PICTRL = 0x84,
2746 ULP_TX_SC_MEMRD = 0x86
2747 };
2748
2749 #define S_ULPTX_CMD 24
2750 #define M_ULPTX_CMD 0xFF
2751 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
2752
2753 #define S_ULPTX_LEN16 0
2754 #define M_ULPTX_LEN16 0xFF
2755 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16)
2756
2757 #define S_ULP_TX_SC_MORE 23
2758 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE)
2759 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U)
2760
2761 struct ulptx_sge_pair {
2762 __be32 len[2];
2763 __be64 addr[2];
2764 };
2765
2766 struct ulptx_sgl {
2767 __be32 cmd_nsge;
2768 __be32 len0;
2769 __be64 addr0;
2770
2771 #if !(defined C99_NOT_SUPPORTED)
2772 struct ulptx_sge_pair sge[];
2773 #endif
2774
2775 };
2776
2777 struct ulptx_isge {
2778 __be32 stag;
2779 __be32 len;
2780 __be64 target_ofst;
2781 };
2782
2783 struct ulptx_isgl {
2784 __be32 cmd_nisge;
2785 __be32 rsvd;
2786
2787 #if !(defined C99_NOT_SUPPORTED)
2788 struct ulptx_isge sge[];
2789 #endif
2790
2791 };
2792
2793 struct ulptx_idata {
2794 __be32 cmd_more;
2795 __be32 len;
2796 };
2797
2798 #define S_ULPTX_NSGE 0
2799 #define M_ULPTX_NSGE 0xFFFF
2800 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)
2801 #define G_ULPTX_NSGE(x) (((x) >> S_ULPTX_NSGE) & M_ULPTX_NSGE)
2802
2803 struct ulptx_sc_memrd {
2804 __be32 cmd_to_len;
2805 __be32 addr;
2806 };
2807
2808 struct ulp_mem_io {
2809 WR_HDR;
2810 __be32 cmd;
2811 __be32 len16; /* command length */
2812 __be32 dlen; /* data length in 32-byte units */
2813 __be32 lock_addr;
2814 };
2815
2816 /* additional ulp_mem_io.cmd fields */
2817 #define S_ULP_MEMIO_ORDER 23
2818 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER)
2819 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U)
2820
2821 #define S_T5_ULP_MEMIO_IMM 23
2822 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM)
2823 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U)
2824
2825 #define S_T5_ULP_MEMIO_ORDER 22
2826 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER)
2827 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U)
2828
2829 #define S_T5_ULP_MEMIO_FID 4
2830 #define M_T5_ULP_MEMIO_FID 0x7ff
2831 #define V_T5_ULP_MEMIO_FID(x) ((x) << S_T5_ULP_MEMIO_FID)
2832
2833 /* ulp_mem_io.lock_addr fields */
2834 #define S_ULP_MEMIO_ADDR 0
2835 #define M_ULP_MEMIO_ADDR 0x7FFFFFF
2836 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
2837
2838 #define S_ULP_MEMIO_LOCK 31
2839 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
2840 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
2841
2842 /* ulp_mem_io.dlen fields */
2843 #define S_ULP_MEMIO_DATA_LEN 0
2844 #define M_ULP_MEMIO_DATA_LEN 0x1F
2845 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
2846
2847 /* ULP_TXPKT field values */
2848 enum {
2849 ULP_TXPKT_DEST_TP = 0,
2850 ULP_TXPKT_DEST_SGE,
2851 ULP_TXPKT_DEST_UP,
2852 ULP_TXPKT_DEST_DEVNULL,
2853 };
2854
2855 struct ulp_txpkt {
2856 __be32 cmd_dest;
2857 __be32 len;
2858 };
2859
2860 /* ulp_txpkt.cmd_dest fields */
2861 #define S_ULP_TXPKT_DATAMODIFY 23
2862 #define M_ULP_TXPKT_DATAMODIFY 0x1
2863 #define V_ULP_TXPKT_DATAMODIFY(x) ((x) << S_ULP_TXPKT_DATAMODIFY)
2864 #define G_ULP_TXPKT_DATAMODIFY(x) \
2865 (((x) >> S_ULP_TXPKT_DATAMODIFY) & M_ULP_TXPKT_DATAMODIFY_)
2866 #define F_ULP_TXPKT_DATAMODIFY V_ULP_TXPKT_DATAMODIFY(1U)
2867
2868 #define S_ULP_TXPKT_CHANNELID 22
2869 #define M_ULP_TXPKT_CHANNELID 0x1
2870 #define V_ULP_TXPKT_CHANNELID(x) ((x) << S_ULP_TXPKT_CHANNELID)
2871 #define G_ULP_TXPKT_CHANNELID(x) \
2872 (((x) >> S_ULP_TXPKT_CHANNELID) & M_ULP_TXPKT_CHANNELID)
2873 #define F_ULP_TXPKT_CHANNELID V_ULP_TXPKT_CHANNELID(1U)
2874
2875 /* ulp_txpkt.cmd_dest fields */
2876 #define S_ULP_TXPKT_DEST 16
2877 #define M_ULP_TXPKT_DEST 0x3
2878 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
2879
2880 #define S_ULP_TXPKT_FID 4
2881 #define M_ULP_TXPKT_FID 0x7ff
2882 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)
2883
2884 #define S_ULP_TXPKT_RO 3
2885 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO)
2886 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U)
2887
2888 enum cpl_tx_tnl_lso_type {
2889 TX_TNL_TYPE_OPAQUE,
2890 TX_TNL_TYPE_NVGRE,
2891 TX_TNL_TYPE_VXLAN,
2892 TX_TNL_TYPE_GENEVE,
2893 };
2894
2895 struct cpl_tx_tnl_lso {
2896 __be32 op_to_IpIdSplitOut;
2897 __be16 IpIdOffsetOut;
2898 __be16 UdpLenSetOut_to_TnlHdrLen;
2899 __be64 r1;
2900 __be32 Flow_to_TcpHdrLen;
2901 __be16 IpIdOffset;
2902 __be16 IpIdSplit_to_Mss;
2903 __be32 TCPSeqOffset;
2904 __be32 EthLenOffset_Size;
2905 /* encapsulated CPL (TX_PKT_XT) follows here */
2906 };
2907
2908 #define S_CPL_TX_TNL_LSO_OPCODE 24
2909 #define M_CPL_TX_TNL_LSO_OPCODE 0xff
2910 #define V_CPL_TX_TNL_LSO_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_OPCODE)
2911 #define G_CPL_TX_TNL_LSO_OPCODE(x) \
2912 (((x) >> S_CPL_TX_TNL_LSO_OPCODE) & M_CPL_TX_TNL_LSO_OPCODE)
2913
2914 #define S_CPL_TX_TNL_LSO_FIRST 23
2915 #define M_CPL_TX_TNL_LSO_FIRST 0x1
2916 #define V_CPL_TX_TNL_LSO_FIRST(x) ((x) << S_CPL_TX_TNL_LSO_FIRST)
2917 #define G_CPL_TX_TNL_LSO_FIRST(x) \
2918 (((x) >> S_CPL_TX_TNL_LSO_FIRST) & M_CPL_TX_TNL_LSO_FIRST)
2919 #define F_CPL_TX_TNL_LSO_FIRST V_CPL_TX_TNL_LSO_FIRST(1U)
2920
2921 #define S_CPL_TX_TNL_LSO_LAST 22
2922 #define M_CPL_TX_TNL_LSO_LAST 0x1
2923 #define V_CPL_TX_TNL_LSO_LAST(x) ((x) << S_CPL_TX_TNL_LSO_LAST)
2924 #define G_CPL_TX_TNL_LSO_LAST(x) \
2925 (((x) >> S_CPL_TX_TNL_LSO_LAST) & M_CPL_TX_TNL_LSO_LAST)
2926 #define F_CPL_TX_TNL_LSO_LAST V_CPL_TX_TNL_LSO_LAST(1U)
2927
2928 #define S_CPL_TX_TNL_LSO_ETHHDRLENXOUT 21
2929 #define M_CPL_TX_TNL_LSO_ETHHDRLENXOUT 0x1
2930 #define V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \
2931 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENXOUT)
2932 #define G_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \
2933 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENXOUT)
2934 #define F_CPL_TX_TNL_LSO_ETHHDRLENXOUT V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(1U)
2935
2936 #define S_CPL_TX_TNL_LSO_IPV6OUT 20
2937 #define M_CPL_TX_TNL_LSO_IPV6OUT 0x1
2938 #define V_CPL_TX_TNL_LSO_IPV6OUT(x) ((x) << S_CPL_TX_TNL_LSO_IPV6OUT)
2939 #define G_CPL_TX_TNL_LSO_IPV6OUT(x) \
2940 (((x) >> S_CPL_TX_TNL_LSO_IPV6OUT) & M_CPL_TX_TNL_LSO_IPV6OUT)
2941 #define F_CPL_TX_TNL_LSO_IPV6OUT V_CPL_TX_TNL_LSO_IPV6OUT(1U)
2942
2943 #define S_CPL_TX_TNL_LSO_ETHHDRLENOUT 16
2944 #define M_CPL_TX_TNL_LSO_ETHHDRLENOUT 0xf
2945 #define V_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \
2946 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENOUT)
2947 #define G_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \
2948 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENOUT)
2949
2950 #define S_CPL_TX_TNL_LSO_IPHDRLENOUT 4
2951 #define M_CPL_TX_TNL_LSO_IPHDRLENOUT 0xfff
2952 #define V_CPL_TX_TNL_LSO_IPHDRLENOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLENOUT)
2953 #define G_CPL_TX_TNL_LSO_IPHDRLENOUT(x) \
2954 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLENOUT) & M_CPL_TX_TNL_LSO_IPHDRLENOUT)
2955
2956 #define S_CPL_TX_TNL_LSO_IPHDRCHKOUT 3
2957 #define M_CPL_TX_TNL_LSO_IPHDRCHKOUT 0x1
2958 #define V_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRCHKOUT)
2959 #define G_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) \
2960 (((x) >> S_CPL_TX_TNL_LSO_IPHDRCHKOUT) & M_CPL_TX_TNL_LSO_IPHDRCHKOUT)
2961 #define F_CPL_TX_TNL_LSO_IPHDRCHKOUT V_CPL_TX_TNL_LSO_IPHDRCHKOUT(1U)
2962
2963 #define S_CPL_TX_TNL_LSO_IPLENSETOUT 2
2964 #define M_CPL_TX_TNL_LSO_IPLENSETOUT 0x1
2965 #define V_CPL_TX_TNL_LSO_IPLENSETOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPLENSETOUT)
2966 #define G_CPL_TX_TNL_LSO_IPLENSETOUT(x) \
2967 (((x) >> S_CPL_TX_TNL_LSO_IPLENSETOUT) & M_CPL_TX_TNL_LSO_IPLENSETOUT)
2968 #define F_CPL_TX_TNL_LSO_IPLENSETOUT V_CPL_TX_TNL_LSO_IPLENSETOUT(1U)
2969
2970 #define S_CPL_TX_TNL_LSO_IPIDINCOUT 1
2971 #define M_CPL_TX_TNL_LSO_IPIDINCOUT 0x1
2972 #define V_CPL_TX_TNL_LSO_IPIDINCOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDINCOUT)
2973 #define G_CPL_TX_TNL_LSO_IPIDINCOUT(x) \
2974 (((x) >> S_CPL_TX_TNL_LSO_IPIDINCOUT) & M_CPL_TX_TNL_LSO_IPIDINCOUT)
2975 #define F_CPL_TX_TNL_LSO_IPIDINCOUT V_CPL_TX_TNL_LSO_IPIDINCOUT(1U)
2976
2977 #define S_CPL_TX_TNL_LSO_IPIDSPLITOUT 0
2978 #define M_CPL_TX_TNL_LSO_IPIDSPLITOUT 0x1
2979 #define V_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \
2980 ((x) << S_CPL_TX_TNL_LSO_IPIDSPLITOUT)
2981 #define G_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \
2982 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLITOUT) & M_CPL_TX_TNL_LSO_IPIDSPLITOUT)
2983 #define F_CPL_TX_TNL_LSO_IPIDSPLITOUT V_CPL_TX_TNL_LSO_IPIDSPLITOUT(1U)
2984
2985 #define S_CPL_TX_TNL_LSO_UDPLENSETOUT 15
2986 #define M_CPL_TX_TNL_LSO_UDPLENSETOUT 0x1
2987 #define V_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \
2988 ((x) << S_CPL_TX_TNL_LSO_UDPLENSETOUT)
2989 #define G_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \
2990 (((x) >> S_CPL_TX_TNL_LSO_UDPLENSETOUT) & M_CPL_TX_TNL_LSO_UDPLENSETOUT)
2991 #define F_CPL_TX_TNL_LSO_UDPLENSETOUT V_CPL_TX_TNL_LSO_UDPLENSETOUT(1U)
2992
2993 #define S_CPL_TX_TNL_LSO_UDPCHKCLROUT 14
2994 #define M_CPL_TX_TNL_LSO_UDPCHKCLROUT 0x1
2995 #define V_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \
2996 ((x) << S_CPL_TX_TNL_LSO_UDPCHKCLROUT)
2997 #define G_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \
2998 (((x) >> S_CPL_TX_TNL_LSO_UDPCHKCLROUT) & M_CPL_TX_TNL_LSO_UDPCHKCLROUT)
2999 #define F_CPL_TX_TNL_LSO_UDPCHKCLROUT V_CPL_TX_TNL_LSO_UDPCHKCLROUT(1U)
3000
3001 #define S_CPL_TX_TNL_LSO_TNLTYPE 12
3002 #define M_CPL_TX_TNL_LSO_TNLTYPE 0x3
3003 #define V_CPL_TX_TNL_LSO_TNLTYPE(x) ((x) << S_CPL_TX_TNL_LSO_TNLTYPE)
3004 #define G_CPL_TX_TNL_LSO_TNLTYPE(x) \
3005 (((x) >> S_CPL_TX_TNL_LSO_TNLTYPE) & M_CPL_TX_TNL_LSO_TNLTYPE)
3006
3007 #define S_CPL_TX_TNL_LSO_TNLHDRLEN 0
3008 #define M_CPL_TX_TNL_LSO_TNLHDRLEN 0xfff
3009 #define V_CPL_TX_TNL_LSO_TNLHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TNLHDRLEN)
3010 #define G_CPL_TX_TNL_LSO_TNLHDRLEN(x) \
3011 (((x) >> S_CPL_TX_TNL_LSO_TNLHDRLEN) & M_CPL_TX_TNL_LSO_TNLHDRLEN)
3012
3013 #define S_CPL_TX_TNL_LSO_FLOW 21
3014 #define M_CPL_TX_TNL_LSO_FLOW 0x1
3015 #define V_CPL_TX_TNL_LSO_FLOW(x) ((x) << S_CPL_TX_TNL_LSO_FLOW)
3016 #define G_CPL_TX_TNL_LSO_FLOW(x) \
3017 (((x) >> S_CPL_TX_TNL_LSO_FLOW) & M_CPL_TX_TNL_LSO_FLOW)
3018 #define F_CPL_TX_TNL_LSO_FLOW V_CPL_TX_TNL_LSO_FLOW(1U)
3019
3020 #define S_CPL_TX_TNL_LSO_IPV6 20
3021 #define M_CPL_TX_TNL_LSO_IPV6 0x1
3022 #define V_CPL_TX_TNL_LSO_IPV6(x) ((x) << S_CPL_TX_TNL_LSO_IPV6)
3023 #define G_CPL_TX_TNL_LSO_IPV6(x) \
3024 (((x) >> S_CPL_TX_TNL_LSO_IPV6) & M_CPL_TX_TNL_LSO_IPV6)
3025 #define F_CPL_TX_TNL_LSO_IPV6 V_CPL_TX_TNL_LSO_IPV6(1U)
3026
3027 #define S_CPL_TX_TNL_LSO_ETHHDRLEN 16
3028 #define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf
3029 #define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN)
3030 #define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \
3031 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN)
3032
3033 #define S_CPL_TX_TNL_LSO_IPHDRLEN 4
3034 #define M_CPL_TX_TNL_LSO_IPHDRLEN 0xfff
3035 #define V_CPL_TX_TNL_LSO_IPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLEN)
3036 #define G_CPL_TX_TNL_LSO_IPHDRLEN(x) \
3037 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLEN) & M_CPL_TX_TNL_LSO_IPHDRLEN)
3038
3039 #define S_CPL_TX_TNL_LSO_TCPHDRLEN 0
3040 #define M_CPL_TX_TNL_LSO_TCPHDRLEN 0xf
3041 #define V_CPL_TX_TNL_LSO_TCPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TCPHDRLEN)
3042 #define G_CPL_TX_TNL_LSO_TCPHDRLEN(x) \
3043 (((x) >> S_CPL_TX_TNL_LSO_TCPHDRLEN) & M_CPL_TX_TNL_LSO_TCPHDRLEN)
3044
3045 #define S_CPL_TX_TNL_LSO_IPIDSPLIT 15
3046 #define M_CPL_TX_TNL_LSO_IPIDSPLIT 0x1
3047 #define V_CPL_TX_TNL_LSO_IPIDSPLIT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDSPLIT)
3048 #define G_CPL_TX_TNL_LSO_IPIDSPLIT(x) \
3049 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLIT) & M_CPL_TX_TNL_LSO_IPIDSPLIT)
3050 #define F_CPL_TX_TNL_LSO_IPIDSPLIT V_CPL_TX_TNL_LSO_IPIDSPLIT(1U)
3051
3052 #define S_CPL_TX_TNL_LSO_ETHHDRLENX 14
3053 #define M_CPL_TX_TNL_LSO_ETHHDRLENX 0x1
3054 #define V_CPL_TX_TNL_LSO_ETHHDRLENX(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENX)
3055 #define G_CPL_TX_TNL_LSO_ETHHDRLENX(x) \
3056 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENX) & M_CPL_TX_TNL_LSO_ETHHDRLENX)
3057 #define F_CPL_TX_TNL_LSO_ETHHDRLENX V_CPL_TX_TNL_LSO_ETHHDRLENX(1U)
3058
3059 #define S_CPL_TX_TNL_LSO_MSS 0
3060 #define M_CPL_TX_TNL_LSO_MSS 0x3fff
3061 #define V_CPL_TX_TNL_LSO_MSS(x) ((x) << S_CPL_TX_TNL_LSO_MSS)
3062 #define G_CPL_TX_TNL_LSO_MSS(x) \
3063 (((x) >> S_CPL_TX_TNL_LSO_MSS) & M_CPL_TX_TNL_LSO_MSS)
3064
3065 #define S_CPL_TX_TNL_LSO_ETHLENOFFSET 28
3066 #define M_CPL_TX_TNL_LSO_ETHLENOFFSET 0xf
3067 #define V_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \
3068 ((x) << S_CPL_TX_TNL_LSO_ETHLENOFFSET)
3069 #define G_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \
3070 (((x) >> S_CPL_TX_TNL_LSO_ETHLENOFFSET) & M_CPL_TX_TNL_LSO_ETHLENOFFSET)
3071
3072 #define S_CPL_TX_TNL_LSO_SIZE 0
3073 #define M_CPL_TX_TNL_LSO_SIZE 0xfffffff
3074 #define V_CPL_TX_TNL_LSO_SIZE(x) ((x) << S_CPL_TX_TNL_LSO_SIZE)
3075 #define G_CPL_TX_TNL_LSO_SIZE(x) \
3076 (((x) >> S_CPL_TX_TNL_LSO_SIZE) & M_CPL_TX_TNL_LSO_SIZE)
3077
3078 struct cpl_rx_mps_pkt {
3079 __be32 op_to_r1_hi;
3080 __be32 r1_lo_length;
3081 };
3082
3083 #define S_CPL_RX_MPS_PKT_OP 24
3084 #define M_CPL_RX_MPS_PKT_OP 0xff
3085 #define V_CPL_RX_MPS_PKT_OP(x) ((x) << S_CPL_RX_MPS_PKT_OP)
3086 #define G_CPL_RX_MPS_PKT_OP(x) \
3087 (((x) >> S_CPL_RX_MPS_PKT_OP) & M_CPL_RX_MPS_PKT_OP)
3088
3089 #define S_CPL_RX_MPS_PKT_TYPE 20
3090 #define M_CPL_RX_MPS_PKT_TYPE 0xf
3091 #define V_CPL_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_RX_MPS_PKT_TYPE)
3092 #define G_CPL_RX_MPS_PKT_TYPE(x) \
3093 (((x) >> S_CPL_RX_MPS_PKT_TYPE) & M_CPL_RX_MPS_PKT_TYPE)
3094
3095 #define S_CPL_RX_MPS_PKT_LENGTH 0
3096 #define M_CPL_RX_MPS_PKT_LENGTH 0xffff
3097 #define V_CPL_RX_MPS_PKT_LENGTH(x) ((x) << S_CPL_RX_MPS_PKT_LENGTH)
3098 #define G_CPL_RX_MPS_PKT_LENGTH(x) \
3099 (((x) >> S_CPL_RX_MPS_PKT_LENGTH) & M_CPL_RX_MPS_PKT_LENGTH)
3100
3101 /*
3102 * Values for CPL_RX_MPS_PKT_TYPE, a bit-wise orthogonal field.
3103 */
3104 #define X_CPL_RX_MPS_PKT_TYPE_PAUSE (1 << 0)
3105 #define X_CPL_RX_MPS_PKT_TYPE_PPP (1 << 1)
3106 #define X_CPL_RX_MPS_PKT_TYPE_QFC (1 << 2)
3107 #define X_CPL_RX_MPS_PKT_TYPE_PTP (1 << 3)
3108
3109 struct cpl_tx_tls_sfo {
3110 __be32 op_to_seg_len;
3111 __be32 pld_len;
3112 __be32 type_protover;
3113 __be32 r1_lo;
3114 __be32 seqno_numivs;
3115 __be32 ivgen_hdrlen;
3116 __be64 scmd1;
3117 };
3118
3119 /* cpl_tx_tls_sfo macros */
3120 #define S_CPL_TX_TLS_SFO_OPCODE 24
3121 #define M_CPL_TX_TLS_SFO_OPCODE 0xff
3122 #define V_CPL_TX_TLS_SFO_OPCODE(x) ((x) << S_CPL_TX_TLS_SFO_OPCODE)
3123 #define G_CPL_TX_TLS_SFO_OPCODE(x) \
3124 (((x) >> S_CPL_TX_TLS_SFO_OPCODE) & M_CPL_TX_TLS_SFO_OPCODE)
3125
3126 #define S_CPL_TX_TLS_SFO_DATA_TYPE 20
3127 #define M_CPL_TX_TLS_SFO_DATA_TYPE 0xf
3128 #define V_CPL_TX_TLS_SFO_DATA_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_DATA_TYPE)
3129 #define G_CPL_TX_TLS_SFO_DATA_TYPE(x) \
3130 (((x) >> S_CPL_TX_TLS_SFO_DATA_TYPE) & M_CPL_TX_TLS_SFO_DATA_TYPE)
3131
3132 #define S_CPL_TX_TLS_SFO_CPL_LEN 16
3133 #define M_CPL_TX_TLS_SFO_CPL_LEN 0xf
3134 #define V_CPL_TX_TLS_SFO_CPL_LEN(x) ((x) << S_CPL_TX_TLS_SFO_CPL_LEN)
3135 #define G_CPL_TX_TLS_SFO_CPL_LEN(x) \
3136 (((x) >> S_CPL_TX_TLS_SFO_CPL_LEN) & M_CPL_TX_TLS_SFO_CPL_LEN)
3137
3138 #define S_CPL_TX_TLS_SFO_SEG_LEN 0
3139 #define M_CPL_TX_TLS_SFO_SEG_LEN 0xffff
3140 #define V_CPL_TX_TLS_SFO_SEG_LEN(x) ((x) << S_CPL_TX_TLS_SFO_SEG_LEN)
3141 #define G_CPL_TX_TLS_SFO_SEG_LEN(x) \
3142 (((x) >> S_CPL_TX_TLS_SFO_SEG_LEN) & M_CPL_TX_TLS_SFO_SEG_LEN)
3143
3144 #define S_CPL_TX_TLS_SFO_TYPE 24
3145 #define M_CPL_TX_TLS_SFO_TYPE 0xff
3146 #define V_CPL_TX_TLS_SFO_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_TYPE)
3147 #define G_CPL_TX_TLS_SFO_TYPE(x) \
3148 (((x) >> S_CPL_TX_TLS_SFO_TYPE) & M_CPL_TX_TLS_SFO_TYPE)
3149
3150 #define S_CPL_TX_TLS_SFO_PROTOVER 8
3151 #define M_CPL_TX_TLS_SFO_PROTOVER 0xffff
3152 #define V_CPL_TX_TLS_SFO_PROTOVER(x) ((x) << S_CPL_TX_TLS_SFO_PROTOVER)
3153 #define G_CPL_TX_TLS_SFO_PROTOVER(x) \
3154 (((x) >> S_CPL_TX_TLS_SFO_PROTOVER) & M_CPL_TX_TLS_SFO_PROTOVER)
3155
3156 struct cpl_tls_data {
3157 RSS_HDR
3158 __be32 op_tid;
3159 __be32 length_pkd;
3160 __be32 seq;
3161 __be32 r1;
3162 };
3163
3164 #define S_CPL_TLS_DATA_OPCODE 24
3165 #define M_CPL_TLS_DATA_OPCODE 0xff
3166 #define V_CPL_TLS_DATA_OPCODE(x) ((x) << S_CPL_TLS_DATA_OPCODE)
3167 #define G_CPL_TLS_DATA_OPCODE(x) \
3168 (((x) >> S_CPL_TLS_DATA_OPCODE) & M_CPL_TLS_DATA_OPCODE)
3169
3170 #define S_CPL_TLS_DATA_TID 0
3171 #define M_CPL_TLS_DATA_TID 0xffffff
3172 #define V_CPL_TLS_DATA_TID(x) ((x) << S_CPL_TLS_DATA_TID)
3173 #define G_CPL_TLS_DATA_TID(x) \
3174 (((x) >> S_CPL_TLS_DATA_TID) & M_CPL_TLS_DATA_TID)
3175
3176 #define S_CPL_TLS_DATA_LENGTH 0
3177 #define M_CPL_TLS_DATA_LENGTH 0xffff
3178 #define V_CPL_TLS_DATA_LENGTH(x) ((x) << S_CPL_TLS_DATA_LENGTH)
3179 #define G_CPL_TLS_DATA_LENGTH(x) \
3180 (((x) >> S_CPL_TLS_DATA_LENGTH) & M_CPL_TLS_DATA_LENGTH)
3181
3182 struct cpl_rx_tls_cmp {
3183 RSS_HDR
3184 __be32 op_tid;
3185 __be32 pdulength_length;
3186 __be32 seq;
3187 __be32 ddp_report;
3188 __be32 r;
3189 __be32 ddp_valid;
3190 };
3191
3192 #define S_CPL_RX_TLS_CMP_OPCODE 24
3193 #define M_CPL_RX_TLS_CMP_OPCODE 0xff
3194 #define V_CPL_RX_TLS_CMP_OPCODE(x) ((x) << S_CPL_RX_TLS_CMP_OPCODE)
3195 #define G_CPL_RX_TLS_CMP_OPCODE(x) \
3196 (((x) >> S_CPL_RX_TLS_CMP_OPCODE) & M_CPL_RX_TLS_CMP_OPCODE)
3197
3198 #define S_CPL_RX_TLS_CMP_TID 0
3199 #define M_CPL_RX_TLS_CMP_TID 0xffffff
3200 #define V_CPL_RX_TLS_CMP_TID(x) ((x) << S_CPL_RX_TLS_CMP_TID)
3201 #define G_CPL_RX_TLS_CMP_TID(x) \
3202 (((x) >> S_CPL_RX_TLS_CMP_TID) & M_CPL_RX_TLS_CMP_TID)
3203
3204 #define S_CPL_RX_TLS_CMP_PDULENGTH 16
3205 #define M_CPL_RX_TLS_CMP_PDULENGTH 0xffff
3206 #define V_CPL_RX_TLS_CMP_PDULENGTH(x) ((x) << S_CPL_RX_TLS_CMP_PDULENGTH)
3207 #define G_CPL_RX_TLS_CMP_PDULENGTH(x) \
3208 (((x) >> S_CPL_RX_TLS_CMP_PDULENGTH) & M_CPL_RX_TLS_CMP_PDULENGTH)
3209
3210 #define S_CPL_RX_TLS_CMP_LENGTH 0
3211 #define M_CPL_RX_TLS_CMP_LENGTH 0xffff
3212 #define V_CPL_RX_TLS_CMP_LENGTH(x) ((x) << S_CPL_RX_TLS_CMP_LENGTH)
3213 #define G_CPL_RX_TLS_CMP_LENGTH(x) \
3214 (((x) >> S_CPL_RX_TLS_CMP_LENGTH) & M_CPL_RX_TLS_CMP_LENGTH)
3215
3216 #define S_SCMD_SEQ_NO_CTRL 29
3217 #define M_SCMD_SEQ_NO_CTRL 0x3
3218 #define V_SCMD_SEQ_NO_CTRL(x) ((x) << S_SCMD_SEQ_NO_CTRL)
3219 #define G_SCMD_SEQ_NO_CTRL(x) \
3220 (((x) >> S_SCMD_SEQ_NO_CTRL) & M_SCMD_SEQ_NO_CTRL)
3221
3222 /* StsFieldPrsnt- Status field at the end of the TLS PDU */
3223 #define S_SCMD_STATUS_PRESENT 28
3224 #define M_SCMD_STATUS_PRESENT 0x1
3225 #define V_SCMD_STATUS_PRESENT(x) ((x) << S_SCMD_STATUS_PRESENT)
3226 #define G_SCMD_STATUS_PRESENT(x) \
3227 (((x) >> S_SCMD_STATUS_PRESENT) & M_SCMD_STATUS_PRESENT)
3228 #define F_SCMD_STATUS_PRESENT V_SCMD_STATUS_PRESENT(1U)
3229
3230 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic,
3231 * 3-15: Reserved. */
3232 #define S_SCMD_PROTO_VERSION 24
3233 #define M_SCMD_PROTO_VERSION 0xf
3234 #define V_SCMD_PROTO_VERSION(x) ((x) << S_SCMD_PROTO_VERSION)
3235 #define G_SCMD_PROTO_VERSION(x) \
3236 (((x) >> S_SCMD_PROTO_VERSION) & M_SCMD_PROTO_VERSION)
3237
3238 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */
3239 #define S_SCMD_ENC_DEC_CTRL 23
3240 #define M_SCMD_ENC_DEC_CTRL 0x1
3241 #define V_SCMD_ENC_DEC_CTRL(x) ((x) << S_SCMD_ENC_DEC_CTRL)
3242 #define G_SCMD_ENC_DEC_CTRL(x) \
3243 (((x) >> S_SCMD_ENC_DEC_CTRL) & M_SCMD_ENC_DEC_CTRL)
3244 #define F_SCMD_ENC_DEC_CTRL V_SCMD_ENC_DEC_CTRL(1U)
3245
3246 /* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */
3247 #define S_SCMD_CIPH_AUTH_SEQ_CTRL 22
3248 #define M_SCMD_CIPH_AUTH_SEQ_CTRL 0x1
3249 #define V_SCMD_CIPH_AUTH_SEQ_CTRL(x) \
3250 ((x) << S_SCMD_CIPH_AUTH_SEQ_CTRL)
3251 #define G_SCMD_CIPH_AUTH_SEQ_CTRL(x) \
3252 (((x) >> S_SCMD_CIPH_AUTH_SEQ_CTRL) & M_SCMD_CIPH_AUTH_SEQ_CTRL)
3253 #define F_SCMD_CIPH_AUTH_SEQ_CTRL V_SCMD_CIPH_AUTH_SEQ_CTRL(1U)
3254
3255 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR,
3256 * 4:Generic-AES, 5-15: Reserved. */
3257 #define S_SCMD_CIPH_MODE 18
3258 #define M_SCMD_CIPH_MODE 0xf
3259 #define V_SCMD_CIPH_MODE(x) ((x) << S_SCMD_CIPH_MODE)
3260 #define G_SCMD_CIPH_MODE(x) \
3261 (((x) >> S_SCMD_CIPH_MODE) & M_SCMD_CIPH_MODE)
3262
3263 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256
3264 * 4-15: Reserved */
3265 #define S_SCMD_AUTH_MODE 14
3266 #define M_SCMD_AUTH_MODE 0xf
3267 #define V_SCMD_AUTH_MODE(x) ((x) << S_SCMD_AUTH_MODE)
3268 #define G_SCMD_AUTH_MODE(x) \
3269 (((x) >> S_SCMD_AUTH_MODE) & M_SCMD_AUTH_MODE)
3270
3271 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation
3272 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved
3273 */
3274 #define S_SCMD_HMAC_CTRL 11
3275 #define M_SCMD_HMAC_CTRL 0x7
3276 #define V_SCMD_HMAC_CTRL(x) ((x) << S_SCMD_HMAC_CTRL)
3277 #define G_SCMD_HMAC_CTRL(x) \
3278 (((x) >> S_SCMD_HMAC_CTRL) & M_SCMD_HMAC_CTRL)
3279
3280 /* IvSize - IV size in units of 2 bytes */
3281 #define S_SCMD_IV_SIZE 7
3282 #define M_SCMD_IV_SIZE 0xf
3283 #define V_SCMD_IV_SIZE(x) ((x) << S_SCMD_IV_SIZE)
3284 #define G_SCMD_IV_SIZE(x) \
3285 (((x) >> S_SCMD_IV_SIZE) & M_SCMD_IV_SIZE)
3286
3287 /* NumIVs - Number of IVs */
3288 #define S_SCMD_NUM_IVS 0
3289 #define M_SCMD_NUM_IVS 0x7f
3290 #define V_SCMD_NUM_IVS(x) ((x) << S_SCMD_NUM_IVS)
3291 #define G_SCMD_NUM_IVS(x) \
3292 (((x) >> S_SCMD_NUM_IVS) & M_SCMD_NUM_IVS)
3293
3294 /* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber
3295 * (below) are used as Cid (connection id for debug status), these
3296 * bits are padded to zero for forming the 64 bit
3297 * sequence number for TLS
3298 */
3299 #define S_SCMD_ENB_DBGID 31
3300 #define M_SCMD_ENB_DBGID 0x1
3301 #define V_SCMD_ENB_DBGID(x) ((x) << S_SCMD_ENB_DBGID)
3302 #define G_SCMD_ENB_DBGID(x) \
3303 (((x) >> S_SCMD_ENB_DBGID) & M_SCMD_ENB_DBGID)
3304
3305 /* IV generation in SW. */
3306 #define S_SCMD_IV_GEN_CTRL 30
3307 #define M_SCMD_IV_GEN_CTRL 0x1
3308 #define V_SCMD_IV_GEN_CTRL(x) ((x) << S_SCMD_IV_GEN_CTRL)
3309 #define G_SCMD_IV_GEN_CTRL(x) \
3310 (((x) >> S_SCMD_IV_GEN_CTRL) & M_SCMD_IV_GEN_CTRL)
3311 #define F_SCMD_IV_GEN_CTRL V_SCMD_IV_GEN_CTRL(1U)
3312
3313 /* More frags */
3314 #define S_SCMD_MORE_FRAGS 20
3315 #define M_SCMD_MORE_FRAGS 0x1
3316 #define V_SCMD_MORE_FRAGS(x) ((x) << S_SCMD_MORE_FRAGS)
3317 #define G_SCMD_MORE_FRAGS(x) (((x) >> S_SCMD_MORE_FRAGS) & M_SCMD_MORE_FRAGS)
3318
3319 /*last frag */
3320 #define S_SCMD_LAST_FRAG 19
3321 #define M_SCMD_LAST_FRAG 0x1
3322 #define V_SCMD_LAST_FRAG(x) ((x) << S_SCMD_LAST_FRAG)
3323 #define G_SCMD_LAST_FRAG(x) (((x) >> S_SCMD_LAST_FRAG) & M_SCMD_LAST_FRAG)
3324
3325 /* TlsCompPdu */
3326 #define S_SCMD_TLS_COMPPDU 18
3327 #define M_SCMD_TLS_COMPPDU 0x1
3328 #define V_SCMD_TLS_COMPPDU(x) ((x) << S_SCMD_TLS_COMPPDU)
3329 #define G_SCMD_TLS_COMPPDU(x) (((x) >> S_SCMD_TLS_COMPPDU) & M_SCMD_TLS_COMPPDU)
3330
3331 /* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/
3332 #define S_SCMD_KEY_CTX_INLINE 17
3333 #define M_SCMD_KEY_CTX_INLINE 0x1
3334 #define V_SCMD_KEY_CTX_INLINE(x) ((x) << S_SCMD_KEY_CTX_INLINE)
3335 #define G_SCMD_KEY_CTX_INLINE(x) \
3336 (((x) >> S_SCMD_KEY_CTX_INLINE) & M_SCMD_KEY_CTX_INLINE)
3337 #define F_SCMD_KEY_CTX_INLINE V_SCMD_KEY_CTX_INLINE(1U)
3338
3339 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */
3340 #define S_SCMD_TLS_FRAG_ENABLE 16
3341 #define M_SCMD_TLS_FRAG_ENABLE 0x1
3342 #define V_SCMD_TLS_FRAG_ENABLE(x) ((x) << S_SCMD_TLS_FRAG_ENABLE)
3343 #define G_SCMD_TLS_FRAG_ENABLE(x) \
3344 (((x) >> S_SCMD_TLS_FRAG_ENABLE) & M_SCMD_TLS_FRAG_ENABLE)
3345 #define F_SCMD_TLS_FRAG_ENABLE V_SCMD_TLS_FRAG_ENABLE(1U)
3346
3347 /* MacOnly - Only send the MAC and discard PDU. This is valid for hash only
3348 * modes, in this case TLS_TX will drop the PDU and only
3349 * send back the MAC bytes. */
3350 #define S_SCMD_MAC_ONLY 15
3351 #define M_SCMD_MAC_ONLY 0x1
3352 #define V_SCMD_MAC_ONLY(x) ((x) << S_SCMD_MAC_ONLY)
3353 #define G_SCMD_MAC_ONLY(x) \
3354 (((x) >> S_SCMD_MAC_ONLY) & M_SCMD_MAC_ONLY)
3355 #define F_SCMD_MAC_ONLY V_SCMD_MAC_ONLY(1U)
3356
3357 /* AadIVDrop - Drop the AAD and IV fields. Useful in protocols
3358 * which have complex AAD and IV formations Eg:AES-CCM
3359 */
3360 #define S_SCMD_AADIVDROP 14
3361 #define M_SCMD_AADIVDROP 0x1
3362 #define V_SCMD_AADIVDROP(x) ((x) << S_SCMD_AADIVDROP)
3363 #define G_SCMD_AADIVDROP(x) \
3364 (((x) >> S_SCMD_AADIVDROP) & M_SCMD_AADIVDROP)
3365 #define F_SCMD_AADIVDROP V_SCMD_AADIVDROP(1U)
3366
3367 /* HdrLength - Length of all headers excluding TLS header
3368 * present before start of crypto PDU/payload. */
3369 #define S_SCMD_HDR_LEN 0
3370 #define M_SCMD_HDR_LEN 0x3fff
3371 #define V_SCMD_HDR_LEN(x) ((x) << S_SCMD_HDR_LEN)
3372 #define G_SCMD_HDR_LEN(x) \
3373 (((x) >> S_SCMD_HDR_LEN) & M_SCMD_HDR_LEN)
3374
3375 struct cpl_tx_sec_pdu {
3376 __be32 op_ivinsrtofst;
3377 __be32 pldlen;
3378 __be32 aadstart_cipherstop_hi;
3379 __be32 cipherstop_lo_authinsert;
3380 __be32 seqno_numivs;
3381 __be32 ivgen_hdrlen;
3382 __be64 scmd1;
3383 };
3384
3385 #define S_CPL_TX_SEC_PDU_OPCODE 24
3386 #define M_CPL_TX_SEC_PDU_OPCODE 0xff
3387 #define V_CPL_TX_SEC_PDU_OPCODE(x) ((x) << S_CPL_TX_SEC_PDU_OPCODE)
3388 #define G_CPL_TX_SEC_PDU_OPCODE(x) \
3389 (((x) >> S_CPL_TX_SEC_PDU_OPCODE) & M_CPL_TX_SEC_PDU_OPCODE)
3390
3391 /* RX Channel Id */
3392 #define S_CPL_TX_SEC_PDU_RXCHID 22
3393 #define M_CPL_TX_SEC_PDU_RXCHID 0x1
3394 #define V_CPL_TX_SEC_PDU_RXCHID(x) ((x) << S_CPL_TX_SEC_PDU_RXCHID)
3395 #define G_CPL_TX_SEC_PDU_RXCHID(x) \
3396 (((x) >> S_CPL_TX_SEC_PDU_RXCHID) & M_CPL_TX_SEC_PDU_RXCHID)
3397 #define F_CPL_TX_SEC_PDU_RXCHID V_CPL_TX_SEC_PDU_RXCHID(1U)
3398
3399 /* Ack Follows */
3400 #define S_CPL_TX_SEC_PDU_ACKFOLLOWS 21
3401 #define M_CPL_TX_SEC_PDU_ACKFOLLOWS 0x1
3402 #define V_CPL_TX_SEC_PDU_ACKFOLLOWS(x) ((x) << S_CPL_TX_SEC_PDU_ACKFOLLOWS)
3403 #define G_CPL_TX_SEC_PDU_ACKFOLLOWS(x) \
3404 (((x) >> S_CPL_TX_SEC_PDU_ACKFOLLOWS) & M_CPL_TX_SEC_PDU_ACKFOLLOWS)
3405 #define F_CPL_TX_SEC_PDU_ACKFOLLOWS V_CPL_TX_SEC_PDU_ACKFOLLOWS(1U)
3406
3407 /* Loopback bit in cpl_tx_sec_pdu */
3408 #define S_CPL_TX_SEC_PDU_ULPTXLPBK 20
3409 #define M_CPL_TX_SEC_PDU_ULPTXLPBK 0x1
3410 #define V_CPL_TX_SEC_PDU_ULPTXLPBK(x) ((x) << S_CPL_TX_SEC_PDU_ULPTXLPBK)
3411 #define G_CPL_TX_SEC_PDU_ULPTXLPBK(x) \
3412 (((x) >> S_CPL_TX_SEC_PDU_ULPTXLPBK) & M_CPL_TX_SEC_PDU_ULPTXLPBK)
3413 #define F_CPL_TX_SEC_PDU_ULPTXLPBK V_CPL_TX_SEC_PDU_ULPTXLPBK(1U)
3414
3415 /* Length of cpl header encapsulated */
3416 #define S_CPL_TX_SEC_PDU_CPLLEN 16
3417 #define M_CPL_TX_SEC_PDU_CPLLEN 0xf
3418 #define V_CPL_TX_SEC_PDU_CPLLEN(x) ((x) << S_CPL_TX_SEC_PDU_CPLLEN)
3419 #define G_CPL_TX_SEC_PDU_CPLLEN(x) \
3420 (((x) >> S_CPL_TX_SEC_PDU_CPLLEN) & M_CPL_TX_SEC_PDU_CPLLEN)
3421
3422 /* PlaceHolder */
3423 #define S_CPL_TX_SEC_PDU_PLACEHOLDER 10
3424 #define M_CPL_TX_SEC_PDU_PLACEHOLDER 0x1
3425 #define V_CPL_TX_SEC_PDU_PLACEHOLDER(x) ((x) << S_CPL_TX_SEC_PDU_PLACEHOLDER)
3426 #define G_CPL_TX_SEC_PDU_PLACEHOLDER(x) \
3427 (((x) >> S_CPL_TX_SEC_PDU_PLACEHOLDER) & \
3428 M_CPL_TX_SEC_PDU_PLACEHOLDER)
3429
3430 /* IvInsrtOffset: Insertion location for IV */
3431 #define S_CPL_TX_SEC_PDU_IVINSRTOFST 0
3432 #define M_CPL_TX_SEC_PDU_IVINSRTOFST 0x3ff
3433 #define V_CPL_TX_SEC_PDU_IVINSRTOFST(x) ((x) << S_CPL_TX_SEC_PDU_IVINSRTOFST)
3434 #define G_CPL_TX_SEC_PDU_IVINSRTOFST(x) \
3435 (((x) >> S_CPL_TX_SEC_PDU_IVINSRTOFST) & \
3436 M_CPL_TX_SEC_PDU_IVINSRTOFST)
3437
3438 /* AadStartOffset: Offset in bytes for AAD start from
3439 * the first byte following
3440 * the pkt headers (0-255
3441 * bytes) */
3442 #define S_CPL_TX_SEC_PDU_AADSTART 24
3443 #define M_CPL_TX_SEC_PDU_AADSTART 0xff
3444 #define V_CPL_TX_SEC_PDU_AADSTART(x) ((x) << S_CPL_TX_SEC_PDU_AADSTART)
3445 #define G_CPL_TX_SEC_PDU_AADSTART(x) \
3446 (((x) >> S_CPL_TX_SEC_PDU_AADSTART) & \
3447 M_CPL_TX_SEC_PDU_AADSTART)
3448
3449 /* AadStopOffset: offset in bytes for AAD stop/end from the first byte following
3450 * the pkt headers (0-511 bytes) */
3451 #define S_CPL_TX_SEC_PDU_AADSTOP 15
3452 #define M_CPL_TX_SEC_PDU_AADSTOP 0x1ff
3453 #define V_CPL_TX_SEC_PDU_AADSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AADSTOP)
3454 #define G_CPL_TX_SEC_PDU_AADSTOP(x) \
3455 (((x) >> S_CPL_TX_SEC_PDU_AADSTOP) & M_CPL_TX_SEC_PDU_AADSTOP)
3456
3457 /* CipherStartOffset: offset in bytes for encryption/decryption start from the
3458 * first byte following the pkt headers (0-1023
3459 * bytes) */
3460 #define S_CPL_TX_SEC_PDU_CIPHERSTART 5
3461 #define M_CPL_TX_SEC_PDU_CIPHERSTART 0x3ff
3462 #define V_CPL_TX_SEC_PDU_CIPHERSTART(x) ((x) << S_CPL_TX_SEC_PDU_CIPHERSTART)
3463 #define G_CPL_TX_SEC_PDU_CIPHERSTART(x) \
3464 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTART) & \
3465 M_CPL_TX_SEC_PDU_CIPHERSTART)
3466
3467 /* CipherStopOffset: offset in bytes for encryption/decryption end
3468 * from end of the payload of this command (0-511 bytes) */
3469 #define S_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0
3470 #define M_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0x1f
3471 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \
3472 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_HI)
3473 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \
3474 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) & \
3475 M_CPL_TX_SEC_PDU_CIPHERSTOP_HI)
3476
3477 #define S_CPL_TX_SEC_PDU_CIPHERSTOP_LO 28
3478 #define M_CPL_TX_SEC_PDU_CIPHERSTOP_LO 0xf
3479 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \
3480 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_LO)
3481 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \
3482 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) & \
3483 M_CPL_TX_SEC_PDU_CIPHERSTOP_LO)
3484
3485 /* AuthStartOffset: offset in bytes for authentication start from
3486 * the first byte following the pkt headers (0-1023)
3487 * */
3488 #define S_CPL_TX_SEC_PDU_AUTHSTART 18
3489 #define M_CPL_TX_SEC_PDU_AUTHSTART 0x3ff
3490 #define V_CPL_TX_SEC_PDU_AUTHSTART(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTART)
3491 #define G_CPL_TX_SEC_PDU_AUTHSTART(x) \
3492 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTART) & \
3493 M_CPL_TX_SEC_PDU_AUTHSTART)
3494
3495 /* AuthStopOffset: offset in bytes for authentication
3496 * end from end of the payload of this command (0-511 Bytes) */
3497 #define S_CPL_TX_SEC_PDU_AUTHSTOP 9
3498 #define M_CPL_TX_SEC_PDU_AUTHSTOP 0x1ff
3499 #define V_CPL_TX_SEC_PDU_AUTHSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTOP)
3500 #define G_CPL_TX_SEC_PDU_AUTHSTOP(x) \
3501 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTOP) & \
3502 M_CPL_TX_SEC_PDU_AUTHSTOP)
3503
3504 /* AuthInsrtOffset: offset in bytes for authentication insertion
3505 * from end of the payload of this command (0-511 bytes) */
3506 #define S_CPL_TX_SEC_PDU_AUTHINSERT 0
3507 #define M_CPL_TX_SEC_PDU_AUTHINSERT 0x1ff
3508 #define V_CPL_TX_SEC_PDU_AUTHINSERT(x) ((x) << S_CPL_TX_SEC_PDU_AUTHINSERT)
3509 #define G_CPL_TX_SEC_PDU_AUTHINSERT(x) \
3510 (((x) >> S_CPL_TX_SEC_PDU_AUTHINSERT) & \
3511 M_CPL_TX_SEC_PDU_AUTHINSERT)
3512
3513 struct cpl_rx_phys_dsgl {
3514 __be32 op_to_tid;
3515 __be32 pcirlxorder_to_noofsgentr;
3516 struct rss_header rss_hdr_int;
3517 };
3518
3519 #define S_CPL_RX_PHYS_DSGL_OPCODE 24
3520 #define M_CPL_RX_PHYS_DSGL_OPCODE 0xff
3521 #define V_CPL_RX_PHYS_DSGL_OPCODE(x) ((x) << S_CPL_RX_PHYS_DSGL_OPCODE)
3522 #define G_CPL_RX_PHYS_DSGL_OPCODE(x) \
3523 (((x) >> S_CPL_RX_PHYS_DSGL_OPCODE) & M_CPL_RX_PHYS_DSGL_OPCODE)
3524
3525 #define S_CPL_RX_PHYS_DSGL_ISRDMA 23
3526 #define M_CPL_RX_PHYS_DSGL_ISRDMA 0x1
3527 #define V_CPL_RX_PHYS_DSGL_ISRDMA(x) ((x) << S_CPL_RX_PHYS_DSGL_ISRDMA)
3528 #define G_CPL_RX_PHYS_DSGL_ISRDMA(x) \
3529 (((x) >> S_CPL_RX_PHYS_DSGL_ISRDMA) & M_CPL_RX_PHYS_DSGL_ISRDMA)
3530 #define F_CPL_RX_PHYS_DSGL_ISRDMA V_CPL_RX_PHYS_DSGL_ISRDMA(1U)
3531
3532 #define S_CPL_RX_PHYS_DSGL_RSVD1 20
3533 #define M_CPL_RX_PHYS_DSGL_RSVD1 0x7
3534 #define V_CPL_RX_PHYS_DSGL_RSVD1(x) ((x) << S_CPL_RX_PHYS_DSGL_RSVD1)
3535 #define G_CPL_RX_PHYS_DSGL_RSVD1(x) \
3536 (((x) >> S_CPL_RX_PHYS_DSGL_RSVD1) & M_CPL_RX_PHYS_DSGL_RSVD1)
3537
3538 #define S_CPL_RX_PHYS_DSGL_PCIRLXORDER 31
3539 #define M_CPL_RX_PHYS_DSGL_PCIRLXORDER 0x1
3540 #define V_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \
3541 ((x) << S_CPL_RX_PHYS_DSGL_PCIRLXORDER)
3542 #define G_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \
3543 (((x) >> S_CPL_RX_PHYS_DSGL_PCIRLXORDER) & \
3544 M_CPL_RX_PHYS_DSGL_PCIRLXORDER)
3545 #define F_CPL_RX_PHYS_DSGL_PCIRLXORDER V_CPL_RX_PHYS_DSGL_PCIRLXORDER(1U)
3546
3547 #define S_CPL_RX_PHYS_DSGL_PCINOSNOOP 30
3548 #define M_CPL_RX_PHYS_DSGL_PCINOSNOOP 0x1
3549 #define V_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \
3550 ((x) << S_CPL_RX_PHYS_DSGL_PCINOSNOOP)
3551 #define G_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \
3552 (((x) >> S_CPL_RX_PHYS_DSGL_PCINOSNOOP) & \
3553 M_CPL_RX_PHYS_DSGL_PCINOSNOOP)
3554 #define F_CPL_RX_PHYS_DSGL_PCINOSNOOP V_CPL_RX_PHYS_DSGL_PCINOSNOOP(1U)
3555
3556 #define S_CPL_RX_PHYS_DSGL_PCITPHNTENB 29
3557 #define M_CPL_RX_PHYS_DSGL_PCITPHNTENB 0x1
3558 #define V_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \
3559 ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNTENB)
3560 #define G_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \
3561 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNTENB) & \
3562 M_CPL_RX_PHYS_DSGL_PCITPHNTENB)
3563 #define F_CPL_RX_PHYS_DSGL_PCITPHNTENB V_CPL_RX_PHYS_DSGL_PCITPHNTENB(1U)
3564
3565 #define S_CPL_RX_PHYS_DSGL_PCITPHNT 27
3566 #define M_CPL_RX_PHYS_DSGL_PCITPHNT 0x3
3567 #define V_CPL_RX_PHYS_DSGL_PCITPHNT(x) ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNT)
3568 #define G_CPL_RX_PHYS_DSGL_PCITPHNT(x) \
3569 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNT) & \
3570 M_CPL_RX_PHYS_DSGL_PCITPHNT)
3571
3572 #define S_CPL_RX_PHYS_DSGL_DCAID 16
3573 #define M_CPL_RX_PHYS_DSGL_DCAID 0x7ff
3574 #define V_CPL_RX_PHYS_DSGL_DCAID(x) ((x) << S_CPL_RX_PHYS_DSGL_DCAID)
3575 #define G_CPL_RX_PHYS_DSGL_DCAID(x) \
3576 (((x) >> S_CPL_RX_PHYS_DSGL_DCAID) & \
3577 M_CPL_RX_PHYS_DSGL_DCAID)
3578
3579 #define S_CPL_RX_PHYS_DSGL_NOOFSGENTR 0
3580 #define M_CPL_RX_PHYS_DSGL_NOOFSGENTR 0xffff
3581 #define V_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \
3582 ((x) << S_CPL_RX_PHYS_DSGL_NOOFSGENTR)
3583 #define G_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \
3584 (((x) >> S_CPL_RX_PHYS_DSGL_NOOFSGENTR) & \
3585 M_CPL_RX_PHYS_DSGL_NOOFSGENTR)
3586
3587 /* CPL_TX_TLS_ACK */
3588 struct cpl_tx_tls_ack {
3589 __be32 op_to_Rsvd2;
3590 __be32 PldLen;
3591 __be64 Rsvd3;
3592 };
3593
3594 #define S_CPL_TX_TLS_ACK_OPCODE 24
3595 #define M_CPL_TX_TLS_ACK_OPCODE 0xff
3596 #define V_CPL_TX_TLS_ACK_OPCODE(x) ((x) << S_CPL_TX_TLS_ACK_OPCODE)
3597 #define G_CPL_TX_TLS_ACK_OPCODE(x) \
3598 (((x) >> S_CPL_TX_TLS_ACK_OPCODE) & M_CPL_TX_TLS_ACK_OPCODE)
3599
3600 #define S_CPL_TX_TLS_ACK_RSVD1 23
3601 #define M_CPL_TX_TLS_ACK_RSVD1 0x1
3602 #define V_CPL_TX_TLS_ACK_RSVD1(x) ((x) << S_CPL_TX_TLS_ACK_RSVD1)
3603 #define G_CPL_TX_TLS_ACK_RSVD1(x) \
3604 (((x) >> S_CPL_TX_TLS_ACK_RSVD1) & M_CPL_TX_TLS_ACK_RSVD1)
3605 #define F_CPL_TX_TLS_ACK_RSVD1 V_CPL_TX_TLS_ACK_RSVD1(1U)
3606
3607 #define S_CPL_TX_TLS_ACK_RXCHID 22
3608 #define M_CPL_TX_TLS_ACK_RXCHID 0x1
3609 #define V_CPL_TX_TLS_ACK_RXCHID(x) ((x) << S_CPL_TX_TLS_ACK_RXCHID)
3610 #define G_CPL_TX_TLS_ACK_RXCHID(x) \
3611 (((x) >> S_CPL_TX_TLS_ACK_RXCHID) & M_CPL_TX_TLS_ACK_RXCHID)
3612 #define F_CPL_TX_TLS_ACK_RXCHID V_CPL_TX_TLS_ACK_RXCHID(1U)
3613
3614 #define S_CPL_TX_TLS_ACK_FWMSG 21
3615 #define M_CPL_TX_TLS_ACK_FWMSG 0x1
3616 #define V_CPL_TX_TLS_ACK_FWMSG(x) ((x) << S_CPL_TX_TLS_ACK_FWMSG)
3617 #define G_CPL_TX_TLS_ACK_FWMSG(x) \
3618 (((x) >> S_CPL_TX_TLS_ACK_FWMSG) & M_CPL_TX_TLS_ACK_FWMSG)
3619 #define F_CPL_TX_TLS_ACK_FWMSG V_CPL_TX_TLS_ACK_FWMSG(1U)
3620
3621 #define S_CPL_TX_TLS_ACK_ULPTXLPBK 20
3622 #define M_CPL_TX_TLS_ACK_ULPTXLPBK 0x1
3623 #define V_CPL_TX_TLS_ACK_ULPTXLPBK(x) ((x) << S_CPL_TX_TLS_ACK_ULPTXLPBK)
3624 #define G_CPL_TX_TLS_ACK_ULPTXLPBK(x) \
3625 (((x) >> S_CPL_TX_TLS_ACK_ULPTXLPBK) & M_CPL_TX_TLS_ACK_ULPTXLPBK)
3626 #define F_CPL_TX_TLS_ACK_ULPTXLPBK V_CPL_TX_TLS_ACK_ULPTXLPBK(1U)
3627
3628 #define S_CPL_TX_TLS_ACK_CPLLEN 16
3629 #define M_CPL_TX_TLS_ACK_CPLLEN 0xf
3630 #define V_CPL_TX_TLS_ACK_CPLLEN(x) ((x) << S_CPL_TX_TLS_ACK_CPLLEN)
3631 #define G_CPL_TX_TLS_ACK_CPLLEN(x) \
3632 (((x) >> S_CPL_TX_TLS_ACK_CPLLEN) & M_CPL_TX_TLS_ACK_CPLLEN)
3633
3634 #define S_CPL_TX_TLS_ACK_COMPLONERR 15
3635 #define M_CPL_TX_TLS_ACK_COMPLONERR 0x1
3636 #define V_CPL_TX_TLS_ACK_COMPLONERR(x) ((x) << S_CPL_TX_TLS_ACK_COMPLONERR)
3637 #define G_CPL_TX_TLS_ACK_COMPLONERR(x) \
3638 (((x) >> S_CPL_TX_TLS_ACK_COMPLONERR) & M_CPL_TX_TLS_ACK_COMPLONERR)
3639 #define F_CPL_TX_TLS_ACK_COMPLONERR V_CPL_TX_TLS_ACK_COMPLONERR(1U)
3640
3641 #define S_CPL_TX_TLS_ACK_LCB 14
3642 #define M_CPL_TX_TLS_ACK_LCB 0x1
3643 #define V_CPL_TX_TLS_ACK_LCB(x) ((x) << S_CPL_TX_TLS_ACK_LCB)
3644 #define G_CPL_TX_TLS_ACK_LCB(x) \
3645 (((x) >> S_CPL_TX_TLS_ACK_LCB) & M_CPL_TX_TLS_ACK_LCB)
3646 #define F_CPL_TX_TLS_ACK_LCB V_CPL_TX_TLS_ACK_LCB(1U)
3647
3648 #define S_CPL_TX_TLS_ACK_PHASH 13
3649 #define M_CPL_TX_TLS_ACK_PHASH 0x1
3650 #define V_CPL_TX_TLS_ACK_PHASH(x) ((x) << S_CPL_TX_TLS_ACK_PHASH)
3651 #define G_CPL_TX_TLS_ACK_PHASH(x) \
3652 (((x) >> S_CPL_TX_TLS_ACK_PHASH) & M_CPL_TX_TLS_ACK_PHASH)
3653 #define F_CPL_TX_TLS_ACK_PHASH V_CPL_TX_TLS_ACK_PHASH(1U)
3654
3655 #define S_CPL_TX_TLS_ACK_RSVD2 0
3656 #define M_CPL_TX_TLS_ACK_RSVD2 0x1fff
3657 #define V_CPL_TX_TLS_ACK_RSVD2(x) ((x) << S_CPL_TX_TLS_ACK_RSVD2)
3658 #define G_CPL_TX_TLS_ACK_RSVD2(x) \
3659 (((x) >> S_CPL_TX_TLS_ACK_RSVD2) & M_CPL_TX_TLS_ACK_RSVD2)
3660
3661 #endif /* T4_MSG_H */
3662