1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, v.1, (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://opensource.org/licenses/CDDL-1.0. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014-2017 Cavium, Inc. 24 * The contents of this file are subject to the terms of the Common Development 25 * and Distribution License, v.1, (the "License"). 26 27 * You may not use this file except in compliance with the License. 28 29 * You can obtain a copy of the License at available 30 * at http://opensource.org/licenses/CDDL-1.0 31 32 * See the License for the specific language governing permissions and 33 * limitations under the License. 34 */ 35 36 #ifndef __ECORE_MCP_API_H__ 37 #define __ECORE_MCP_API_H__ 38 39 #include "ecore_status.h" 40 41 struct ecore_mcp_link_speed_params { 42 bool autoneg; 43 u32 advertised_speeds; /* bitmask of DRV_SPEED_CAPABILITY */ 44 u32 forced_speed; /* In Mb/s */ 45 }; 46 47 struct ecore_mcp_link_pause_params { 48 bool autoneg; 49 bool forced_rx; 50 bool forced_tx; 51 }; 52 53 enum ecore_mcp_eee_mode { 54 ECORE_MCP_EEE_DISABLED, 55 ECORE_MCP_EEE_ENABLED, 56 ECORE_MCP_EEE_UNSUPPORTED 57 }; 58 59 #ifndef __EXTRACT__LINUX__ 60 struct ecore_link_eee_params { 61 u32 tx_lpi_timer; 62 #define ECORE_EEE_1G_ADV (1 << 0) 63 #define ECORE_EEE_10G_ADV (1 << 1) 64 /* Capabilities are represented using ECORE_EEE_*_ADV values */ 65 u8 adv_caps; 66 u8 lp_adv_caps; 67 bool enable; 68 bool tx_lpi_enable; 69 }; 70 #endif 71 72 struct ecore_mcp_link_params { 73 struct ecore_mcp_link_speed_params speed; 74 struct ecore_mcp_link_pause_params pause; 75 u32 loopback_mode; /* in PMM_LOOPBACK values */ 76 struct ecore_link_eee_params eee; 77 }; 78 79 struct ecore_mcp_link_capabilities { 80 u32 speed_capabilities; 81 bool default_speed_autoneg; /* In Mb/s */ 82 u32 default_speed; /* In Mb/s */ 83 enum ecore_mcp_eee_mode default_eee; 84 u32 eee_lpi_timer; 85 }; 86 87 struct ecore_mcp_link_state { 88 bool link_up; 89 90 u32 line_speed; /* In Mb/s */ 91 u32 min_pf_rate; /* In Mb/s */ 92 u32 speed; /* In Mb/s */ 93 bool full_duplex; 94 95 bool an; 96 bool an_complete; 97 bool parallel_detection; 98 bool pfc_enabled; 99 100 #define ECORE_LINK_PARTNER_SPEED_1G_HD (1 << 0) 101 #define ECORE_LINK_PARTNER_SPEED_1G_FD (1 << 1) 102 #define ECORE_LINK_PARTNER_SPEED_10G (1 << 2) 103 #define ECORE_LINK_PARTNER_SPEED_20G (1 << 3) 104 #define ECORE_LINK_PARTNER_SPEED_25G (1 << 4) 105 #define ECORE_LINK_PARTNER_SPEED_40G (1 << 5) 106 #define ECORE_LINK_PARTNER_SPEED_50G (1 << 6) 107 #define ECORE_LINK_PARTNER_SPEED_100G (1 << 7) 108 u32 partner_adv_speed; 109 110 bool partner_tx_flow_ctrl_en; 111 bool partner_rx_flow_ctrl_en; 112 113 #define ECORE_LINK_PARTNER_SYMMETRIC_PAUSE (1) 114 #define ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE (2) 115 #define ECORE_LINK_PARTNER_BOTH_PAUSE (3) 116 u8 partner_adv_pause; 117 118 bool sfp_tx_fault; 119 120 bool eee_active; 121 u8 eee_adv_caps; 122 u8 eee_lp_adv_caps; 123 }; 124 125 struct ecore_mcp_function_info { 126 u8 pause_on_host; 127 128 enum ecore_pci_personality protocol; 129 130 u8 bandwidth_min; 131 u8 bandwidth_max; 132 133 u8 mac[ETH_ALEN]; 134 135 u64 wwn_port; 136 u64 wwn_node; 137 138 #define ECORE_MCP_VLAN_UNSET (0xffff) 139 u16 ovlan; 140 141 u16 mtu; 142 }; 143 144 struct ecore_mcp_nvm_common { 145 u32 offset; 146 u32 param; 147 u32 resp; 148 u32 cmd; 149 }; 150 151 struct ecore_mcp_nvm_rd { 152 u32 *buf_size; 153 u32 *buf; 154 }; 155 156 struct ecore_mcp_nvm_wr { 157 u32 buf_size; 158 u32 *buf; 159 }; 160 161 struct ecore_mcp_nvm_params { 162 #define ECORE_MCP_CMD (1 << 0) 163 #define ECORE_MCP_NVM_RD (1 << 1) 164 #define ECORE_MCP_NVM_WR (1 << 2) 165 u8 type; 166 167 struct ecore_mcp_nvm_common nvm_common; 168 169 union { 170 struct ecore_mcp_nvm_rd nvm_rd; 171 struct ecore_mcp_nvm_wr nvm_wr; 172 }; 173 }; 174 175 #ifndef __EXTRACT__LINUX__ 176 enum ecore_nvm_images { 177 ECORE_NVM_IMAGE_ISCSI_CFG, 178 ECORE_NVM_IMAGE_FCOE_CFG, 179 ECORE_NVM_IMAGE_MDUMP, 180 }; 181 #endif 182 183 struct ecore_mcp_drv_version { 184 u32 version; 185 u8 name[MCP_DRV_VER_STR_SIZE - 4]; 186 }; 187 188 struct ecore_mcp_lan_stats { 189 u64 ucast_rx_pkts; 190 u64 ucast_tx_pkts; 191 u32 fcs_err; 192 }; 193 194 #ifndef ECORE_PROTO_STATS 195 #define ECORE_PROTO_STATS 196 struct ecore_mcp_fcoe_stats { 197 u64 rx_pkts; 198 u64 tx_pkts; 199 u32 fcs_err; 200 u32 login_failure; 201 }; 202 203 struct ecore_mcp_iscsi_stats { 204 u64 rx_pdus; 205 u64 tx_pdus; 206 u64 rx_bytes; 207 u64 tx_bytes; 208 }; 209 210 struct ecore_mcp_rdma_stats { 211 u64 rx_pkts; 212 u64 tx_pkts; 213 u64 rx_bytes; 214 u64 tx_byts; 215 }; 216 217 enum ecore_mcp_protocol_type { 218 ECORE_MCP_LAN_STATS, 219 ECORE_MCP_FCOE_STATS, 220 ECORE_MCP_ISCSI_STATS, 221 ECORE_MCP_RDMA_STATS 222 }; 223 224 union ecore_mcp_protocol_stats { 225 struct ecore_mcp_lan_stats lan_stats; 226 struct ecore_mcp_fcoe_stats fcoe_stats; 227 struct ecore_mcp_iscsi_stats iscsi_stats; 228 struct ecore_mcp_rdma_stats rdma_stats; 229 }; 230 #endif 231 232 enum ecore_ov_client { 233 ECORE_OV_CLIENT_DRV, 234 ECORE_OV_CLIENT_USER, 235 ECORE_OV_CLIENT_VENDOR_SPEC 236 }; 237 238 enum ecore_ov_driver_state { 239 ECORE_OV_DRIVER_STATE_NOT_LOADED, 240 ECORE_OV_DRIVER_STATE_DISABLED, 241 ECORE_OV_DRIVER_STATE_ACTIVE 242 }; 243 244 enum ecore_ov_wol { 245 ECORE_OV_WOL_DEFAULT, 246 ECORE_OV_WOL_DISABLED, 247 ECORE_OV_WOL_ENABLED 248 }; 249 250 #ifndef __EXTRACT__LINUX__ 251 #define ECORE_MAX_NPIV_ENTRIES 128 252 #define ECORE_WWN_SIZE 8 253 struct ecore_fc_npiv_tbl { 254 u16 num_wwpn; 255 u16 num_wwnn; 256 u8 wwpn[ECORE_MAX_NPIV_ENTRIES][ECORE_WWN_SIZE]; 257 u8 wwnn[ECORE_MAX_NPIV_ENTRIES][ECORE_WWN_SIZE]; 258 }; 259 260 enum ecore_led_mode { 261 ECORE_LED_MODE_OFF, 262 ECORE_LED_MODE_ON, 263 ECORE_LED_MODE_RESTORE 264 }; 265 #endif 266 267 struct ecore_temperature_sensor { 268 u8 sensor_location; 269 u8 threshold_high; 270 u8 critical; 271 u8 current_temp; 272 }; 273 274 #define ECORE_MAX_NUM_OF_SENSORS 7 275 struct ecore_temperature_info { 276 u32 num_sensors; 277 struct ecore_temperature_sensor sensors[ECORE_MAX_NUM_OF_SENSORS]; 278 }; 279 280 enum ecore_mba_img_idx { 281 ECORE_MBA_LEGACY_IDX, 282 ECORE_MBA_PCI3CLP_IDX, 283 ECORE_MBA_PCI3_IDX, 284 ECORE_MBA_FCODE_IDX, 285 ECORE_EFI_X86_IDX, 286 ECORE_EFI_IPF_IDX, 287 ECORE_EFI_EBC_IDX, 288 ECORE_EFI_X64_IDX, 289 ECORE_MAX_NUM_OF_ROMIMG 290 }; 291 292 struct ecore_mba_vers { 293 u32 mba_vers[ECORE_MAX_NUM_OF_ROMIMG]; 294 }; 295 296 enum ecore_mfw_tlv_type { 297 ECORE_MFW_TLV_GENERIC = 0x1, /* Core driver TLVs */ 298 ECORE_MFW_TLV_ETH = 0x2, /* L2 driver TLVs */ 299 ECORE_MFW_TLV_FCOE = 0x4, /* FCoE protocol TLVs */ 300 ECORE_MFW_TLV_ISCSI = 0x8, /* SCSI protocol TLVs */ 301 ECORE_MFW_TLV_MAX = 0x16, 302 }; 303 304 struct ecore_mfw_tlv_generic { 305 struct { 306 u8 ipv4_csum_offload; 307 u8 lso_supported; 308 bool b_set; 309 } flags; 310 311 #define ECORE_MFW_TLV_MAC_COUNT 3 312 /* First entry for primary MAC, 2 secondary MACs possible */ 313 u8 mac[ECORE_MFW_TLV_MAC_COUNT][6]; 314 bool mac_set[ECORE_MFW_TLV_MAC_COUNT]; 315 316 u64 rx_frames; 317 bool rx_frames_set; 318 u64 rx_bytes; 319 bool rx_bytes_set; 320 u64 tx_frames; 321 bool tx_frames_set; 322 u64 tx_bytes; 323 bool tx_bytes_set; 324 }; 325 326 #ifndef __EXTRACT__LINUX__ 327 struct ecore_mfw_tlv_eth { 328 u16 lso_maxoff_size; 329 bool lso_maxoff_size_set; 330 u16 lso_minseg_size; 331 bool lso_minseg_size_set; 332 u8 prom_mode; 333 bool prom_mode_set; 334 u16 tx_descr_size; 335 bool tx_descr_size_set; 336 u16 rx_descr_size; 337 bool rx_descr_size_set; 338 u16 netq_count; 339 bool netq_count_set; 340 u32 tcp4_offloads; 341 bool tcp4_offloads_set; 342 u32 tcp6_offloads; 343 bool tcp6_offloads_set; 344 u16 tx_descr_qdepth; 345 bool tx_descr_qdepth_set; 346 u16 rx_descr_qdepth; 347 bool rx_descr_qdepth_set; 348 u8 iov_offload; 349 #define ECORE_MFW_TLV_IOV_OFFLOAD_NONE (0) 350 #define ECORE_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE (1) 351 #define ECORE_MFW_TLV_IOV_OFFLOAD_VEB (2) 352 #define ECORE_MFW_TLV_IOV_OFFLOAD_VEPA (3) 353 bool iov_offload_set; 354 u8 txqs_empty; 355 bool txqs_empty_set; 356 u8 rxqs_empty; 357 bool rxqs_empty_set; 358 u8 num_txqs_full; 359 bool num_txqs_full_set; 360 u8 num_rxqs_full; 361 bool num_rxqs_full_set; 362 }; 363 364 struct ecore_mfw_tlv_time { 365 bool b_set; 366 u8 month; 367 u8 day; 368 u8 hour; 369 u8 min; 370 u16 msec; 371 u16 usec; 372 }; 373 374 struct ecore_mfw_tlv_fcoe { 375 u8 scsi_timeout; 376 bool scsi_timeout_set; 377 u32 rt_tov; 378 bool rt_tov_set; 379 u32 ra_tov; 380 bool ra_tov_set; 381 u32 ed_tov; 382 bool ed_tov_set; 383 u32 cr_tov; 384 bool cr_tov_set; 385 u8 boot_type; 386 bool boot_type_set; 387 u8 npiv_state; 388 bool npiv_state_set; 389 u32 num_npiv_ids; 390 bool num_npiv_ids_set; 391 u8 switch_name[8]; 392 bool switch_name_set; 393 u16 switch_portnum; 394 bool switch_portnum_set; 395 u8 switch_portid[3]; 396 bool switch_portid_set; 397 u8 vendor_name[8]; 398 bool vendor_name_set; 399 u8 switch_model[8]; 400 bool switch_model_set; 401 u8 switch_fw_version[8]; 402 bool switch_fw_version_set; 403 u8 qos_pri; 404 bool qos_pri_set; 405 u8 port_alias[3]; 406 bool port_alias_set; 407 u8 port_state; 408 #define ECORE_MFW_TLV_PORT_STATE_OFFLINE (0) 409 #define ECORE_MFW_TLV_PORT_STATE_LOOP (1) 410 #define ECORE_MFW_TLV_PORT_STATE_P2P (2) 411 #define ECORE_MFW_TLV_PORT_STATE_FABRIC (3) 412 bool port_state_set; 413 u16 fip_tx_descr_size; 414 bool fip_tx_descr_size_set; 415 u16 fip_rx_descr_size; 416 bool fip_rx_descr_size_set; 417 u16 link_failures; 418 bool link_failures_set; 419 u8 fcoe_boot_progress; 420 bool fcoe_boot_progress_set; 421 u64 rx_bcast; 422 bool rx_bcast_set; 423 u64 tx_bcast; 424 bool tx_bcast_set; 425 u16 fcoe_txq_depth; 426 bool fcoe_txq_depth_set; 427 u16 fcoe_rxq_depth; 428 bool fcoe_rxq_depth_set; 429 u64 fcoe_rx_frames; 430 bool fcoe_rx_frames_set; 431 u64 fcoe_rx_bytes; 432 bool fcoe_rx_bytes_set; 433 u64 fcoe_tx_frames; 434 bool fcoe_tx_frames_set; 435 u64 fcoe_tx_bytes; 436 bool fcoe_tx_bytes_set; 437 u16 crc_count; 438 bool crc_count_set; 439 u32 crc_err_src_fcid[5]; 440 bool crc_err_src_fcid_set[5]; 441 struct ecore_mfw_tlv_time crc_err[5]; 442 u16 losync_err; 443 bool losync_err_set; 444 u16 losig_err; 445 bool losig_err_set; 446 u16 primtive_err; 447 bool primtive_err_set; 448 u16 disparity_err; 449 bool disparity_err_set; 450 u16 code_violation_err; 451 bool code_violation_err_set; 452 u32 flogi_param[4]; 453 bool flogi_param_set[4]; 454 struct ecore_mfw_tlv_time flogi_tstamp; 455 u32 flogi_acc_param[4]; 456 bool flogi_acc_param_set[4]; 457 struct ecore_mfw_tlv_time flogi_acc_tstamp; 458 u32 flogi_rjt; 459 bool flogi_rjt_set; 460 struct ecore_mfw_tlv_time flogi_rjt_tstamp; 461 u32 fdiscs; 462 bool fdiscs_set; 463 u8 fdisc_acc; 464 bool fdisc_acc_set; 465 u8 fdisc_rjt; 466 bool fdisc_rjt_set; 467 u8 plogi; 468 bool plogi_set; 469 u8 plogi_acc; 470 bool plogi_acc_set; 471 u8 plogi_rjt; 472 bool plogi_rjt_set; 473 u32 plogi_dst_fcid[5]; 474 bool plogi_dst_fcid_set[5]; 475 struct ecore_mfw_tlv_time plogi_tstamp[5]; 476 u32 plogi_acc_src_fcid[5]; 477 bool plogi_acc_src_fcid_set[5]; 478 struct ecore_mfw_tlv_time plogi_acc_tstamp[5]; 479 u8 tx_plogos; 480 bool tx_plogos_set; 481 u8 plogo_acc; 482 bool plogo_acc_set; 483 u8 plogo_rjt; 484 bool plogo_rjt_set; 485 u32 plogo_src_fcid[5]; 486 bool plogo_src_fcid_set[5]; 487 struct ecore_mfw_tlv_time plogo_tstamp[5]; 488 u8 rx_logos; 489 bool rx_logos_set; 490 u8 tx_accs; 491 bool tx_accs_set; 492 u8 tx_prlis; 493 bool tx_prlis_set; 494 u8 rx_accs; 495 bool rx_accs_set; 496 u8 tx_abts; 497 bool tx_abts_set; 498 u8 rx_abts_acc; 499 bool rx_abts_acc_set; 500 u8 rx_abts_rjt; 501 bool rx_abts_rjt_set; 502 u32 abts_dst_fcid[5]; 503 bool abts_dst_fcid_set[5]; 504 struct ecore_mfw_tlv_time abts_tstamp[5]; 505 u8 rx_rscn; 506 bool rx_rscn_set; 507 u32 rx_rscn_nport[4]; 508 bool rx_rscn_nport_set[4]; 509 u8 tx_lun_rst; 510 bool tx_lun_rst_set; 511 u8 abort_task_sets; 512 bool abort_task_sets_set; 513 u8 tx_tprlos; 514 bool tx_tprlos_set; 515 u8 tx_nos; 516 bool tx_nos_set; 517 u8 rx_nos; 518 bool rx_nos_set; 519 u8 ols; 520 bool ols_set; 521 u8 lr; 522 bool lr_set; 523 u8 lrr; 524 bool lrr_set; 525 u8 tx_lip; 526 bool tx_lip_set; 527 u8 rx_lip; 528 bool rx_lip_set; 529 u8 eofa; 530 bool eofa_set; 531 u8 eofni; 532 bool eofni_set; 533 u8 scsi_chks; 534 bool scsi_chks_set; 535 u8 scsi_cond_met; 536 bool scsi_cond_met_set; 537 u8 scsi_busy; 538 bool scsi_busy_set; 539 u8 scsi_inter; 540 bool scsi_inter_set; 541 u8 scsi_inter_cond_met; 542 bool scsi_inter_cond_met_set; 543 u8 scsi_rsv_conflicts; 544 bool scsi_rsv_conflicts_set; 545 u8 scsi_tsk_full; 546 bool scsi_tsk_full_set; 547 u8 scsi_aca_active; 548 bool scsi_aca_active_set; 549 u8 scsi_tsk_abort; 550 bool scsi_tsk_abort_set; 551 u32 scsi_rx_chk[5]; 552 bool scsi_rx_chk_set[5]; 553 struct ecore_mfw_tlv_time scsi_chk_tstamp[5]; 554 }; 555 556 struct ecore_mfw_tlv_iscsi { 557 u8 target_llmnr; 558 bool target_llmnr_set; 559 u8 header_digest; 560 bool header_digest_set; 561 u8 data_digest; 562 bool data_digest_set; 563 u8 auth_method; 564 #define ECORE_MFW_TLV_AUTH_METHOD_NONE (1) 565 #define ECORE_MFW_TLV_AUTH_METHOD_CHAP (2) 566 #define ECORE_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP (3) 567 bool auth_method_set; 568 u16 boot_taget_portal; 569 bool boot_taget_portal_set; 570 u16 frame_size; 571 bool frame_size_set; 572 u16 tx_desc_size; 573 bool tx_desc_size_set; 574 u16 rx_desc_size; 575 bool rx_desc_size_set; 576 u8 boot_progress; 577 bool boot_progress_set; 578 u16 tx_desc_qdepth; 579 bool tx_desc_qdepth_set; 580 u16 rx_desc_qdepth; 581 bool rx_desc_qdepth_set; 582 u64 rx_frames; 583 bool rx_frames_set; 584 u64 rx_bytes; 585 bool rx_bytes_set; 586 u64 tx_frames; 587 bool tx_frames_set; 588 u64 tx_bytes; 589 bool tx_bytes_set; 590 }; 591 #endif 592 593 union ecore_mfw_tlv_data { 594 struct ecore_mfw_tlv_generic generic; 595 struct ecore_mfw_tlv_eth eth; 596 struct ecore_mfw_tlv_fcoe fcoe; 597 struct ecore_mfw_tlv_iscsi iscsi; 598 }; 599 600 enum ecore_hw_info_change { 601 ECORE_HW_INFO_CHANGE_OVLAN, 602 }; 603 604 /** 605 * @brief - returns the link params of the hw function 606 * 607 * @param p_hwfn 608 * 609 * @returns pointer to link params 610 */ 611 struct ecore_mcp_link_params *ecore_mcp_get_link_params(struct ecore_hwfn*); 612 613 /** 614 * @brief - return the link state of the hw function 615 * 616 * @param p_hwfn 617 * 618 * @returns pointer to link state 619 */ 620 struct ecore_mcp_link_state *ecore_mcp_get_link_state(struct ecore_hwfn*); 621 622 /** 623 * @brief - return the link capabilities of the hw function 624 * 625 * @param p_hwfn 626 * 627 * @returns pointer to link capabilities 628 */ 629 struct ecore_mcp_link_capabilities 630 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn); 631 632 /** 633 * @brief Request the MFW to set the the link according to 'link_input'. 634 * 635 * @param p_hwfn 636 * @param p_ptt 637 * @param b_up - raise link if `true'. Reset link if `false'. 638 * 639 * @return enum _ecore_status_t 640 */ 641 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn, 642 struct ecore_ptt *p_ptt, 643 bool b_up); 644 645 /** 646 * @brief Get the management firmware version value 647 * 648 * @param p_hwfn 649 * @param p_ptt 650 * @param p_mfw_ver - mfw version value 651 * @param p_running_bundle_id - image id in nvram; Optional. 652 * 653 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 654 */ 655 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn, 656 struct ecore_ptt *p_ptt, 657 u32 *p_mfw_ver, 658 u32 *p_running_bundle_id); 659 660 /** 661 * @brief Get the MBI version value 662 * 663 * @param p_hwfn 664 * @param p_ptt 665 * @param p_mbi_ver - A pointer to a variable to be filled with the MBI version. 666 * 667 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 668 */ 669 enum _ecore_status_t ecore_mcp_get_mbi_ver(struct ecore_hwfn *p_hwfn, 670 struct ecore_ptt *p_ptt, 671 u32 *p_mbi_ver); 672 673 /** 674 * @brief Get media type value of the port. 675 * 676 * @param p_dev - ecore dev pointer 677 * @param mfw_ver - media type value 678 * 679 * @return enum _ecore_status_t - 680 * ECORE_SUCCESS - Operation was successful. 681 * ECORE_BUSY - Operation failed 682 */ 683 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev, 684 u32 *media_type); 685 686 /** 687 * @brief - Sends a command to the MCP mailbox. 688 * 689 * @param p_hwfn - hw function 690 * @param p_ptt - PTT required for register access 691 * @param cmd - command to be sent to the MCP 692 * @param param - optional param 693 * @param o_mcp_resp - the MCP response code (exclude sequence) 694 * @param o_mcp_param - optional parameter provided by the MCP response 695 * 696 * @return enum _ecore_status_t - 697 * ECORE_SUCCESS - operation was successful 698 * ECORE_BUSY - operation failed 699 */ 700 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn, 701 struct ecore_ptt *p_ptt, u32 cmd, u32 param, 702 u32 *o_mcp_resp, u32 *o_mcp_param); 703 704 /** 705 * @brief - drains the nig, allowing completion to pass in case of pauses. 706 * (Should be called only from sleepable context) 707 * 708 * @param p_hwfn 709 * @param p_ptt 710 */ 711 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn, 712 struct ecore_ptt *p_ptt); 713 714 #ifndef LINUX_REMOVE 715 /** 716 * @brief - return the mcp function info of the hw function 717 * 718 * @param p_hwfn 719 * 720 * @returns pointer to mcp function info 721 */ 722 const struct ecore_mcp_function_info 723 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn); 724 #endif 725 726 /** 727 * @brief - Function for reading/manipulating the nvram. Following are supported 728 * functionalities. 729 * 1. Read: Read the specified nvram offset. 730 * input values: 731 * type - ECORE_MCP_NVM_RD 732 * cmd - command code (e.g. DRV_MSG_CODE_NVM_READ_NVRAM) 733 * offset - nvm offset 734 * 735 * output values: 736 * buf - buffer 737 * buf_size - buffer size 738 * 739 * 2. Write: Write the data at the specified nvram offset 740 * input values: 741 * type - ECORE_MCP_NVM_WR 742 * cmd - command code (e.g. DRV_MSG_CODE_NVM_WRITE_NVRAM) 743 * offset - nvm offset 744 * buf - buffer 745 * buf_size - buffer size 746 * 747 * 3. Command: Send the NVM command to MCP. 748 * input values: 749 * type - ECORE_MCP_CMD 750 * cmd - command code (e.g. DRV_MSG_CODE_NVM_DEL_FILE) 751 * offset - nvm offset 752 * 753 * 754 * @param p_hwfn 755 * @param p_ptt 756 * @param params 757 * 758 * @return ECORE_SUCCESS - operation was successful. 759 */ 760 enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn, 761 struct ecore_ptt *p_ptt, 762 struct ecore_mcp_nvm_params *params); 763 764 #ifndef LINUX_REMOVE 765 /** 766 * @brief - count number of function with a matching personality on engine. 767 * 768 * @param p_hwfn 769 * @param p_ptt 770 * @param personalities - a bitmask of ecore_pci_personality values 771 * 772 * @returns the count of all devices on engine whose personality match one of 773 * the bitsmasks. 774 */ 775 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn, 776 struct ecore_ptt *p_ptt, 777 u32 personalities); 778 #endif 779 780 /** 781 * @brief Get the flash size value 782 * 783 * @param p_hwfn 784 * @param p_ptt 785 * @param p_flash_size - flash size in bytes to be filled. 786 * 787 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 788 */ 789 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn, 790 struct ecore_ptt *p_ptt, 791 u32 *p_flash_size); 792 793 /** 794 * @brief Send driver version to MFW 795 * 796 * @param p_hwfn 797 * @param p_ptt 798 * @param version - Version value 799 * @param name - Protocol driver name 800 * 801 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 802 */ 803 enum _ecore_status_t 804 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 805 struct ecore_mcp_drv_version *p_ver); 806 807 /** 808 * @brief Read the MFW process kill counter 809 * 810 * @param p_hwfn 811 * @param p_ptt 812 * 813 * @return u32 814 */ 815 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn, 816 struct ecore_ptt *p_ptt); 817 818 /** 819 * @brief Trigger a recovery process 820 * 821 * @param p_hwfn 822 * @param p_ptt 823 * 824 * @return enum _ecore_status_t 825 */ 826 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn, 827 struct ecore_ptt *p_ptt); 828 829 /** 830 * @brief Notify MFW about the change in base device properties 831 * 832 * @param p_hwfn 833 * @param p_ptt 834 * @param client - ecore client type 835 * 836 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 837 */ 838 enum _ecore_status_t 839 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn, 840 struct ecore_ptt *p_ptt, 841 enum ecore_ov_client client); 842 843 /** 844 * @brief Notify MFW about the driver state 845 * 846 * @param p_hwfn 847 * @param p_ptt 848 * @param drv_state - Driver state 849 * 850 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 851 */ 852 enum _ecore_status_t 853 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn, 854 struct ecore_ptt *p_ptt, 855 enum ecore_ov_driver_state drv_state); 856 857 /** 858 * @brief Read NPIV settings form the MFW 859 * 860 * @param p_hwfn 861 * @param p_ptt 862 * @param p_table - Array to hold the FC NPIV data. Client need allocate the 863 * required buffer. The field 'count' specifies number of NPIV 864 * entries. A value of 0 means the table was not populated. 865 * 866 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 867 */ 868 enum _ecore_status_t 869 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 870 struct ecore_fc_npiv_tbl *p_table); 871 872 /** 873 * @brief Send MTU size to MFW 874 * 875 * @param p_hwfn 876 * @param p_ptt 877 * @param mtu - MTU size 878 * 879 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 880 */ 881 enum _ecore_status_t ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn, 882 struct ecore_ptt *p_ptt, u16 mtu); 883 884 /** 885 * @brief Send MAC address to MFW 886 * 887 * @param p_hwfn 888 * @param p_ptt 889 * @param mac - MAC address 890 * 891 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 892 */ 893 enum _ecore_status_t 894 ecore_mcp_ov_update_mac(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 895 u8 *mac); 896 897 /** 898 * @brief Send WOL mode to MFW 899 * 900 * @param p_hwfn 901 * @param p_ptt 902 * @param wol - WOL mode 903 * 904 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 905 */ 906 enum _ecore_status_t 907 ecore_mcp_ov_update_wol(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 908 enum ecore_ov_wol wol); 909 910 /** 911 * @brief Set LED status 912 * 913 * @param p_hwfn 914 * @param p_ptt 915 * @param mode - LED mode 916 * 917 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 918 */ 919 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn, 920 struct ecore_ptt *p_ptt, 921 enum ecore_led_mode mode); 922 923 /** 924 * @brief Set secure mode 925 * 926 * @param p_dev 927 * @param addr - nvm offset 928 * 929 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 930 */ 931 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev, 932 u32 addr); 933 934 /** 935 * @brief Write to phy 936 * 937 * @param p_dev 938 * @param addr - nvm offset 939 * @param cmd - nvm command 940 * @param p_buf - nvm write buffer 941 * @param len - buffer len 942 * 943 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 944 */ 945 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd, 946 u32 addr, u8 *p_buf, u32 len); 947 948 /** 949 * @brief Write to nvm 950 * 951 * @param p_dev 952 * @param addr - nvm offset 953 * @param cmd - nvm command 954 * @param p_buf - nvm write buffer 955 * @param len - buffer len 956 * 957 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 958 */ 959 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd, 960 u32 addr, u8 *p_buf, u32 len); 961 962 /** 963 * @brief Put file begin 964 * 965 * @param p_dev 966 * @param addr - nvm offset 967 * 968 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 969 */ 970 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev, 971 u32 addr); 972 973 /** 974 * @brief Delete file 975 * 976 * @param p_dev 977 * @param addr - nvm offset 978 * 979 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 980 */ 981 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, 982 u32 addr); 983 984 /** 985 * @brief Check latest response 986 * 987 * @param p_dev 988 * @param p_buf - nvm write buffer 989 * 990 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 991 */ 992 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf); 993 994 /** 995 * @brief Read from phy 996 * 997 * @param p_dev 998 * @param addr - nvm offset 999 * @param cmd - nvm command 1000 * @param p_buf - nvm write buffer 1001 * @param len - buffer len 1002 * 1003 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1004 */ 1005 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd, 1006 u32 addr, u8 *p_buf, u32 len); 1007 1008 /** 1009 * @brief Read from nvm 1010 * 1011 * @param p_dev 1012 * @param addr - nvm offset 1013 * @param p_buf - nvm write buffer 1014 * @param len - buffer len 1015 * 1016 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1017 */ 1018 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr, 1019 u8 *p_buf, u32 len); 1020 1021 struct ecore_nvm_image_att { 1022 u32 start_addr; 1023 u32 length; 1024 }; 1025 1026 /** 1027 * @brief Allows reading a whole nvram image 1028 * 1029 * @param p_hwfn 1030 * @param p_ptt 1031 * @param image_id - image to get attributes for 1032 * @param p_image_att - image attributes structure into which to fill data 1033 * 1034 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1035 */ 1036 enum _ecore_status_t 1037 ecore_mcp_get_nvm_image_att(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1038 enum ecore_nvm_images image_id, 1039 struct ecore_nvm_image_att *p_image_att); 1040 1041 /** 1042 * @brief Allows reading a whole nvram image 1043 * 1044 * @param p_hwfn 1045 * @param p_ptt 1046 * @param image_id - image requested for reading 1047 * @param p_buffer - allocated buffer into which to fill data 1048 * @param buffer_len - length of the allocated buffer. 1049 * 1050 * @return ECORE_SUCCESS iff p_buffer now contains the nvram image. 1051 */ 1052 enum _ecore_status_t ecore_mcp_get_nvm_image(struct ecore_hwfn *p_hwfn, 1053 struct ecore_ptt *p_ptt, 1054 enum ecore_nvm_images image_id, 1055 u8 *p_buffer, u32 buffer_len); 1056 1057 /** 1058 * @brief Read from sfp 1059 * 1060 * @param p_hwfn - hw function 1061 * @param p_ptt - PTT required for register access 1062 * @param port - transceiver port 1063 * @param addr - I2C address 1064 * @param offset - offset in sfp 1065 * @param len - buffer length 1066 * @param p_buf - buffer to read into 1067 * 1068 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1069 */ 1070 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn, 1071 struct ecore_ptt *p_ptt, 1072 u32 port, u32 addr, u32 offset, 1073 u32 len, u8 *p_buf); 1074 1075 /** 1076 * @brief Write to sfp 1077 * 1078 * @param p_hwfn - hw function 1079 * @param p_ptt - PTT required for register access 1080 * @param port - transceiver port 1081 * @param addr - I2C address 1082 * @param offset - offset in sfp 1083 * @param len - buffer length 1084 * @param p_buf - buffer to write from 1085 * 1086 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1087 */ 1088 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn, 1089 struct ecore_ptt *p_ptt, 1090 u32 port, u32 addr, u32 offset, 1091 u32 len, u8 *p_buf); 1092 1093 /** 1094 * @brief Gpio read 1095 * 1096 * @param p_hwfn - hw function 1097 * @param p_ptt - PTT required for register access 1098 * @param gpio - gpio number 1099 * @param gpio_val - value read from gpio 1100 * 1101 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1102 */ 1103 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn, 1104 struct ecore_ptt *p_ptt, 1105 u16 gpio, u32 *gpio_val); 1106 1107 /** 1108 * @brief Gpio write 1109 * 1110 * @param p_hwfn - hw function 1111 * @param p_ptt - PTT required for register access 1112 * @param gpio - gpio number 1113 * @param gpio_val - value to write to gpio 1114 * 1115 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1116 */ 1117 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn, 1118 struct ecore_ptt *p_ptt, 1119 u16 gpio, u16 gpio_val); 1120 1121 /** 1122 * @brief Gpio get information 1123 * 1124 * @param p_hwfn - hw function 1125 * @param p_ptt - PTT required for register access 1126 * @param gpio - gpio number 1127 * @param gpio_direction - gpio is output (0) or input (1) 1128 * @param gpio_ctrl - gpio control is uninitialized (0), 1129 * path 0 (1), path 1 (2) or shared(3) 1130 * 1131 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1132 */ 1133 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn, 1134 struct ecore_ptt *p_ptt, 1135 u16 gpio, u32 *gpio_direction, 1136 u32 *gpio_ctrl); 1137 1138 /** 1139 * @brief Bist register test 1140 * 1141 * @param p_hwfn - hw function 1142 * @param p_ptt - PTT required for register access 1143 * 1144 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1145 */ 1146 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn, 1147 struct ecore_ptt *p_ptt); 1148 1149 /** 1150 * @brief Bist clock test 1151 * 1152 * @param p_hwfn - hw function 1153 * @param p_ptt - PTT required for register access 1154 * 1155 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1156 */ 1157 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn, 1158 struct ecore_ptt *p_ptt); 1159 1160 /** 1161 * @brief Bist nvm test - get number of images 1162 * 1163 * @param p_hwfn - hw function 1164 * @param p_ptt - PTT required for register access 1165 * @param num_images - number of images if operation was 1166 * successful. 0 if not. 1167 * 1168 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1169 */ 1170 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(struct ecore_hwfn *p_hwfn, 1171 struct ecore_ptt *p_ptt, 1172 u32 *num_images); 1173 1174 /** 1175 * @brief Bist nvm test - get image attributes by index 1176 * 1177 * @param p_hwfn - hw function 1178 * @param p_ptt - PTT required for register access 1179 * @param p_image_att - Attributes of image 1180 * @param image_index - Index of image to get information for 1181 * 1182 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1183 */ 1184 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(struct ecore_hwfn *p_hwfn, 1185 struct ecore_ptt *p_ptt, 1186 struct bist_nvm_image_att *p_image_att, 1187 u32 image_index); 1188 1189 /** 1190 * @brief ecore_mcp_get_temperature_info - get the status of the temperature 1191 * sensors 1192 * 1193 * @param p_hwfn - hw function 1194 * @param p_ptt - PTT required for register access 1195 * @param p_temp_status - A pointer to an ecore_temperature_info structure to 1196 * be filled with the temperature data 1197 * 1198 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1199 */ 1200 enum _ecore_status_t 1201 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn, 1202 struct ecore_ptt *p_ptt, 1203 struct ecore_temperature_info *p_temp_info); 1204 1205 /** 1206 * @brief Get MBA versions - get MBA sub images versions 1207 * 1208 * @param p_hwfn - hw function 1209 * @param p_ptt - PTT required for register access 1210 * @param p_mba_vers - MBA versions array to fill 1211 * 1212 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1213 */ 1214 enum _ecore_status_t ecore_mcp_get_mba_versions( 1215 struct ecore_hwfn *p_hwfn, 1216 struct ecore_ptt *p_ptt, 1217 struct ecore_mba_vers *p_mba_vers); 1218 1219 /** 1220 * @brief Count memory ecc events 1221 * 1222 * @param p_hwfn - hw function 1223 * @param p_ptt - PTT required for register access 1224 * @param num_events - number of memory ecc events 1225 * 1226 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1227 */ 1228 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn, 1229 struct ecore_ptt *p_ptt, 1230 u64 *num_events); 1231 1232 struct ecore_mdump_info { 1233 u32 reason; 1234 u32 version; 1235 u32 config; 1236 u32 epoch; 1237 u32 num_of_logs; 1238 u32 valid_logs; 1239 }; 1240 1241 /** 1242 * @brief - Gets the MFW crash dump configuration and logs info. 1243 * 1244 * @param p_hwfn 1245 * @param p_ptt 1246 * @param p_mdump_info 1247 * 1248 * @param return ECORE_SUCCESS upon success. 1249 */ 1250 enum _ecore_status_t 1251 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1252 struct ecore_mdump_info *p_mdump_info); 1253 1254 /** 1255 * @brief - Clears the MFW crash dump logs. 1256 * 1257 * @param p_hwfn 1258 * @param p_ptt 1259 * 1260 * @param return ECORE_SUCCESS upon success. 1261 */ 1262 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn, 1263 struct ecore_ptt *p_ptt); 1264 1265 /** 1266 * @brief - Gets the LLDP MAC address. 1267 * 1268 * @param p_hwfn 1269 * @param p_ptt 1270 * @param lldp_mac_addr - a buffer to be filled with the read LLDP MAC address. 1271 * 1272 * @param return ECORE_SUCCESS upon success. 1273 */ 1274 enum _ecore_status_t ecore_mcp_get_lldp_mac(struct ecore_hwfn *p_hwfn, 1275 struct ecore_ptt *p_ptt, 1276 u8 lldp_mac_addr[ETH_ALEN]); 1277 1278 /** 1279 * @brief - Sets the LLDP MAC address. 1280 * 1281 * @param p_hwfn 1282 * @param p_ptt 1283 * @param lldp_mac_addr - a buffer with the LLDP MAC address to be written. 1284 * 1285 * @param return ECORE_SUCCESS upon success. 1286 */ 1287 enum _ecore_status_t ecore_mcp_set_lldp_mac(struct ecore_hwfn *p_hwfn, 1288 struct ecore_ptt *p_ptt, 1289 u8 lldp_mac_addr[ETH_ALEN]); 1290 1291 /** 1292 * @brief - Processes the TLV request from MFW i.e., get the required TLV info 1293 * from the ecore client and send it to the MFW. 1294 * 1295 * @param p_hwfn 1296 * @param p_ptt 1297 * 1298 * @param return ECORE_SUCCESS upon success. 1299 */ 1300 enum _ecore_status_t ecore_mfw_process_tlv_req(struct ecore_hwfn *p_hwfn, 1301 struct ecore_ptt *p_ptt); 1302 1303 /** 1304 * @brief - Update fcoe vlan id value to the MFW. 1305 * 1306 * @param p_hwfn 1307 * @param p_ptt 1308 * @param vlan - fcoe vlan 1309 * 1310 * @param return ECORE_SUCCESS upon success. 1311 */ 1312 enum _ecore_status_t 1313 ecore_mcp_update_fcoe_cvid(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1314 u16 vlan); 1315 1316 /** 1317 * @brief - Update fabric name (wwn) value to the MFW. 1318 * 1319 * @param p_hwfn 1320 * @param p_ptt 1321 * @param wwn - world wide name 1322 * 1323 * @param return ECORE_SUCCESS upon success. 1324 */ 1325 enum _ecore_status_t 1326 ecore_mcp_update_fcoe_fabric_name(struct ecore_hwfn *p_hwfn, 1327 struct ecore_ptt *p_ptt, u8 *wwn); 1328 #endif 1329