1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2020, The University of Queensland 14 * Copyright (c) 2018, Joyent, Inc. 15 * Copyright 2020 RackTop Systems, Inc. 16 * Copyright 2023 MNX Cloud, Inc. 17 */ 18 19 #ifndef _MLXCX_REG_H 20 #define _MLXCX_REG_H 21 22 #include <sys/types.h> 23 #include <sys/byteorder.h> 24 25 #include <mlxcx_endint.h> 26 27 #if !defined(_BIT_FIELDS_HTOL) && !defined(_BIT_FIELDS_LTOH) 28 #error "Need _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH" 29 #endif 30 31 /* 32 * Register offsets. 33 */ 34 35 #define MLXCX_ISS_FIRMWARE 0x0000 36 #define MLXCX_ISS_FW_MAJOR(x) (((x) & 0xffff)) 37 #define MLXCX_ISS_FW_MINOR(x) (((x) >> 16) & 0xffff) 38 #define MLXCX_ISS_FW_CMD 0x0004 39 #define MLXCX_ISS_FW_REV(x) (((x) & 0xffff)) 40 #define MLXCX_ISS_CMD_REV(x) (((x) >> 16) & 0xffff) 41 #define MLXCX_ISS_CMD_HIGH 0x0010 42 #define MLXCX_ISS_CMD_LOW 0x0014 43 #define MLXCX_ISS_CMDQ_SIZE(x) (((x) >> 4) & 0xf) 44 #define MLXCX_ISS_CMDQ_STRIDE(x) ((x) & 0xf) 45 46 #define MLXCX_ISS_CMD_DOORBELL 0x0018 47 #define MLXCX_ISS_INIT 0x01fc 48 #define MLXCX_ISS_INITIALIZING(x) (((x) >> 31) & 0x1) 49 #define MLXCX_ISS_HEALTH_BUF 0x0200 50 #define MLXCX_ISS_NO_DRAM_NIC 0x0240 51 #define MLXCX_ISS_TIMER 0x1000 52 #define MLXCX_ISS_HEALTH_COUNT 0x1010 53 #define MLXCX_ISS_HEALTH_SYND 0x1013 54 55 #define MLXCX_CMD_INLINE_INPUT_LEN 16 56 #define MLXCX_CMD_INLINE_OUTPUT_LEN 16 57 58 #define MLXCX_CMD_MAILBOX_LEN 512 59 60 #define MLXCX_CMD_TRANSPORT_PCI 7 61 #define MLXCX_CMD_HW_OWNED 0x01 62 #define MLXCX_CMD_STATUS(x) ((x) >> 1) 63 64 /* 65 * You can't have more commands pending, than bit size of a doorbell 66 */ 67 #define MLXCX_CMD_MAX (sizeof (uint32_t) * NBBY) 68 69 #define MLXCX_UAR_CQ_ARM 0x0020 70 #define MLXCX_UAR_EQ_ARM 0x0040 71 #define MLXCX_UAR_EQ_NOARM 0x0048 72 73 /* Number of blue flame reg pairs per UAR */ 74 #define MLXCX_BF_PER_UAR 2 75 #define MLXCX_BF_PER_UAR_MASK 0x1 76 #define MLXCX_BF_SIZE 0x100 77 #define MLXCX_BF_BASE 0x0800 78 79 /* CSTYLED */ 80 #define MLXCX_EQ_ARM_EQN (bitdef_t){24, 0xff000000} 81 /* CSTYLED */ 82 #define MLXCX_EQ_ARM_CI (bitdef_t){0, 0x00ffffff} 83 84 /* 85 * Hardware structure that is used to represent a command. 86 */ 87 #pragma pack(1) 88 typedef struct { 89 uint8_t mce_type; 90 uint8_t mce_rsvd[3]; 91 uint32be_t mce_in_length; 92 uint64be_t mce_in_mbox; 93 uint8_t mce_input[MLXCX_CMD_INLINE_INPUT_LEN]; 94 uint8_t mce_output[MLXCX_CMD_INLINE_OUTPUT_LEN]; 95 uint64be_t mce_out_mbox; 96 uint32be_t mce_out_length; 97 uint8_t mce_token; 98 uint8_t mce_sig; 99 uint8_t mce_rsvd1; 100 uint8_t mce_status; 101 } mlxcx_cmd_ent_t; 102 103 typedef struct { 104 uint8_t mlxb_data[MLXCX_CMD_MAILBOX_LEN]; 105 uint8_t mlxb_rsvd[48]; 106 uint64be_t mlxb_nextp; 107 uint32be_t mlxb_blockno; 108 uint8_t mlxb_rsvd1; 109 uint8_t mlxb_token; 110 uint8_t mlxb_ctrl_sig; 111 uint8_t mlxb_sig; 112 } mlxcx_cmd_mailbox_t; 113 114 typedef struct { 115 uint8_t mled_page_request_rsvd[2]; 116 uint16be_t mled_page_request_function_id; 117 uint32be_t mled_page_request_num_pages; 118 } mlxcx_evdata_page_request_t; 119 120 /* CSTYLED */ 121 #define MLXCX_EVENT_PORT_NUM (bitdef_t){ .bit_shift = 4, .bit_mask = 0xF0 } 122 123 typedef struct { 124 uint8_t mled_port_state_rsvd[8]; 125 bits8_t mled_port_state_port_num; 126 } mlxcx_evdata_port_state_t; 127 128 typedef enum { 129 MLXCX_MODULE_INITIALIZING = 0x0, 130 MLXCX_MODULE_PLUGGED = 0x1, 131 MLXCX_MODULE_UNPLUGGED = 0x2, 132 MLXCX_MODULE_ERROR = 0x3 133 } mlxcx_module_status_t; 134 135 typedef enum { 136 MLXCX_MODULE_ERR_POWER_BUDGET = 0x0, 137 MLXCX_MODULE_ERR_LONG_RANGE = 0x1, 138 MLXCX_MODULE_ERR_BUS_STUCK = 0x2, 139 MLXCX_MODULE_ERR_NO_EEPROM = 0x3, 140 MLXCX_MODULE_ERR_ENFORCEMENT = 0x4, 141 MLXCX_MODULE_ERR_UNKNOWN_IDENT = 0x5, 142 MLXCX_MODULE_ERR_HIGH_TEMP = 0x6, 143 MLXCX_MODULE_ERR_CABLE_SHORTED = 0x7, 144 } mlxcx_module_error_type_t; 145 146 typedef struct { 147 uint8_t mled_port_mod_rsvd; 148 uint8_t mled_port_mod_module; 149 uint8_t mled_port_mod_rsvd2; 150 uint8_t mled_port_mod_module_status; 151 uint8_t mled_port_mod_rsvd3[2]; 152 uint8_t mled_port_mod_error_type; 153 uint8_t mled_port_mod_rsvd4; 154 } mlxcx_evdata_port_mod_t; 155 156 typedef struct { 157 uint8_t mled_completion_rsvd[25]; 158 uint24be_t mled_completion_cqn; 159 } mlxcx_evdata_completion_t; 160 161 typedef struct { 162 uint32be_t mled_cmd_completion_vec; 163 uint8_t mled_cmd_completion_rsvd[24]; 164 } mlxcx_evdata_cmd_completion_t; 165 166 typedef enum { 167 MLXCX_EV_QUEUE_TYPE_QP = 0x0, 168 MLXCX_EV_QUEUE_TYPE_RQ = 0x1, 169 MLXCX_EV_QUEUE_TYPE_SQ = 0x2, 170 } mlxcx_evdata_queue_type_t; 171 172 typedef struct { 173 uint8_t mled_queue_rsvd[20]; 174 uint8_t mled_queue_type; 175 uint8_t mled_queue_rsvd2[4]; 176 uint24be_t mled_queue_num; 177 } mlxcx_evdata_queue_t; 178 179 #define MLXCX_EQ_OWNER_INIT 1 180 181 typedef struct { 182 uint8_t mleqe_rsvd[1]; 183 uint8_t mleqe_event_type; 184 uint8_t mleqe_rsvd2[1]; 185 uint8_t mleqe_event_sub_type; 186 uint8_t mleqe_rsvd3[28]; 187 union { 188 uint8_t mleqe_unknown_data[28]; 189 mlxcx_evdata_cmd_completion_t mleqe_cmd_completion; 190 mlxcx_evdata_completion_t mleqe_completion; 191 mlxcx_evdata_page_request_t mleqe_page_request; 192 mlxcx_evdata_port_state_t mleqe_port_state; 193 mlxcx_evdata_port_mod_t mleqe_port_mod; 194 mlxcx_evdata_queue_t mleqe_queue; 195 }; 196 uint8_t mleqe_rsvd4[2]; 197 uint8_t mleqe_signature; 198 uint8_t mleqe_owner; 199 } mlxcx_eventq_ent_t; 200 201 typedef enum { 202 MLXCX_CQE_L3_HDR_NONE = 0x0, 203 MLXCX_CQE_L3_HDR_RCV_BUF = 0x1, 204 MLXCX_CQE_L3_HDR_CQE = 0x2, 205 } mlxcx_cqe_l3_hdr_placement_t; 206 207 typedef enum { 208 MLXCX_CQE_CSFLAGS_L4_OK = 1 << 2, 209 MLXCX_CQE_CSFLAGS_L3_OK = 1 << 1, 210 MLXCX_CQE_CSFLAGS_L2_OK = 1 << 0, 211 } mlxcx_cqe_csflags_t; 212 213 typedef enum { 214 MLXCX_CQE_L4_TYPE_NONE = 0, 215 MLXCX_CQE_L4_TYPE_TCP = 1, 216 MLXCX_CQE_L4_TYPE_UDP = 2, 217 MLXCX_CQE_L4_TYPE_TCP_EMPTY_ACK = 3, 218 MLXCX_CQE_L4_TYPE_TCP_ACK = 4, 219 } mlxcx_cqe_l4_hdr_type_t; 220 221 typedef enum { 222 MLXCX_CQE_L3_TYPE_NONE = 0, 223 MLXCX_CQE_L3_TYPE_IPv6 = 1, 224 MLXCX_CQE_L3_TYPE_IPv4 = 2, 225 } mlxcx_cqe_l3_hdr_type_t; 226 227 typedef enum { 228 MLXCX_CQE_RX_HASH_NONE = 0, 229 MLXCX_CQE_RX_HASH_IPv4 = 1, 230 MLXCX_CQE_RX_HASH_IPv6 = 2, 231 MLXCX_CQE_RX_HASH_IPSEC_SPI = 3, 232 } mlxcx_cqe_rx_hash_type_t; 233 /* BEGIN CSTYLED */ 234 #define MLXCX_CQE_RX_HASH_IP_SRC (bitdef_t){0, 0x3} 235 #define MLXCX_CQE_RX_HASH_IP_DEST (bitdef_t){2, (0x3 << 2)} 236 #define MLXCX_CQE_RX_HASH_L4_SRC (bitdef_t){4, (0x3 << 4)} 237 #define MLXCX_CQE_RX_HASH_L4_DEST (bitdef_t){6, (0x3 << 6)} 238 /* END CSTYLED */ 239 240 typedef enum { 241 MLXCX_CQE_OP_REQ = 0x0, 242 MLXCX_CQE_OP_RESP_RDMA = 0x1, 243 MLXCX_CQE_OP_RESP = 0x2, 244 MLXCX_CQE_OP_RESP_IMMEDIATE = 0x3, 245 MLXCX_CQE_OP_RESP_INVALIDATE = 0x4, 246 MLXCX_CQE_OP_RESIZE_CQ = 0x5, 247 MLXCX_CQE_OP_SIG_ERR = 0x12, 248 MLXCX_CQE_OP_REQ_ERR = 0xd, 249 MLXCX_CQE_OP_RESP_ERR = 0xe, 250 MLXCX_CQE_OP_INVALID = 0xf 251 } mlxcx_cqe_opcode_t; 252 253 typedef enum { 254 MLXCX_CQE_FORMAT_BASIC = 0, 255 MLXCX_CQE_FORMAT_INLINE_32 = 1, 256 MLXCX_CQE_FORMAT_INLINE_64 = 2, 257 MLXCX_CQE_FORMAT_COMPRESSED = 3, 258 } mlxcx_cqe_format_t; 259 260 typedef enum { 261 MLXCX_CQE_OWNER_INIT = 1 262 } mlxcx_cqe_owner_t; 263 264 typedef enum { 265 MLXCX_VLAN_TYPE_NONE, 266 MLXCX_VLAN_TYPE_CVLAN, 267 MLXCX_VLAN_TYPE_SVLAN, 268 } mlxcx_vlan_type_t; 269 270 typedef enum { 271 MLXCX_CQ_ERR_LOCAL_LENGTH = 0x1, 272 MLXCX_CQ_ERR_LOCAL_QP_OP = 0x2, 273 MLXCX_CQ_ERR_LOCAL_PROTECTION = 0x4, 274 MLXCX_CQ_ERR_WR_FLUSHED = 0x5, 275 MLXCX_CQ_ERR_MEM_WINDOW_BIND = 0x6, 276 MLXCX_CQ_ERR_BAD_RESPONSE = 0x10, 277 MLXCX_CQ_ERR_LOCAL_ACCESS = 0x11, 278 MLXCX_CQ_ERR_XPORT_RETRY_CTR = 0x15, 279 MLXCX_CQ_ERR_RNR_RETRY_CTR = 0x16, 280 MLXCX_CQ_ERR_ABORTED = 0x22 281 } mlxcx_cq_error_syndrome_t; 282 283 typedef struct { 284 uint8_t mlcqee_rsvd[2]; 285 uint16be_t mlcqee_wqe_id; 286 uint8_t mlcqee_rsvd2[29]; 287 uint24be_t mlcqee_user_index; 288 uint8_t mlcqee_rsvd3[8]; 289 uint32be_t mlcqee_byte_cnt; 290 uint8_t mlcqee_rsvd4[6]; 291 uint8_t mlcqee_vendor_error_syndrome; 292 uint8_t mlcqee_syndrome; 293 uint8_t mlcqee_wqe_opcode; 294 uint24be_t mlcqee_flow_tag; 295 uint16be_t mlcqee_wqe_counter; 296 uint8_t mlcqee_signature; 297 struct { 298 #if defined(_BIT_FIELDS_HTOL) 299 uint8_t mlcqe_opcode:4; 300 uint8_t mlcqe_rsvd5:3; 301 uint8_t mlcqe_owner:1; 302 #elif defined(_BIT_FIELDS_LTOH) 303 uint8_t mlcqe_owner:1; 304 uint8_t mlcqe_rsvd5:3; 305 uint8_t mlcqe_opcode:4; 306 #endif 307 }; 308 } mlxcx_completionq_error_ent_t; 309 310 typedef struct { 311 uint8_t mlcqe_tunnel_flags; 312 uint8_t mlcqe_rsvd[3]; 313 uint8_t mlcqe_lro_flags; 314 uint8_t mlcqe_lro_min_ttl; 315 uint16be_t mlcqe_lro_tcp_win; 316 uint32be_t mlcqe_lro_ack_seq_num; 317 uint32be_t mlcqe_rx_hash_result; 318 bits8_t mlcqe_rx_hash_type; 319 uint8_t mlcqe_ml_path; 320 uint8_t mlcqe_rsvd2[2]; 321 uint16be_t mlcqe_checksum; 322 uint16be_t mlcqe_slid_smac_lo; 323 struct { 324 #if defined(_BIT_FIELDS_HTOL) 325 uint8_t mlcqe_rsvd3:1; 326 uint8_t mlcqe_force_loopback:1; 327 uint8_t mlcqe_l3_hdr:2; 328 uint8_t mlcqe_sl_roce_pktype:4; 329 #elif defined(_BIT_FIELDS_LTOH) 330 uint8_t mlcqe_sl_roce_pktype:4; 331 uint8_t mlcqe_l3_hdr:2; 332 uint8_t mlcqe_force_loopback:1; 333 uint8_t mlcqe_rsvd3:1; 334 #endif 335 }; 336 uint24be_t mlcqe_rqpn; 337 bits8_t mlcqe_csflags; 338 struct { 339 #if defined(_BIT_FIELDS_HTOL) 340 uint8_t mlcqe_ip_frag:1; 341 uint8_t mlcqe_l4_hdr_type:3; 342 uint8_t mlcqe_l3_hdr_type:2; 343 uint8_t mlcqe_ip_ext_opts:1; 344 uint8_t mlcqe_cv:1; 345 #elif defined(_BIT_FIELDS_LTOH) 346 uint8_t mlcqe_cv:1; 347 uint8_t mlcqe_ip_ext_opts:1; 348 uint8_t mlcqe_l3_hdr_type:2; 349 uint8_t mlcqe_l4_hdr_type:3; 350 uint8_t mlcqe_ip_frag:1; 351 #endif 352 }; 353 uint16be_t mlcqe_up_cfi_vid; 354 uint8_t mlcqe_lro_num_seg; 355 uint24be_t mlcqe_user_index; 356 uint32be_t mlcqe_immediate; 357 uint8_t mlcqe_rsvd4[4]; 358 uint32be_t mlcqe_byte_cnt; 359 union { 360 struct { 361 uint32be_t mlcqe_lro_timestamp_value; 362 uint32be_t mlcqe_lro_timestamp_echo; 363 }; 364 uint64be_t mlcqe_timestamp; 365 }; 366 union { 367 uint8_t mlcqe_rx_drop_counter; 368 uint8_t mlcqe_send_wqe_opcode; 369 }; 370 uint24be_t mlcqe_flow_tag; 371 uint16be_t mlcqe_wqe_counter; 372 uint8_t mlcqe_signature; 373 struct { 374 #if defined(_BIT_FIELDS_HTOL) 375 uint8_t mlcqe_opcode:4; 376 uint8_t mlcqe_format:2; 377 uint8_t mlcqe_se:1; 378 uint8_t mlcqe_owner:1; 379 #elif defined(_BIT_FIELDS_LTOH) 380 uint8_t mlcqe_owner:1; 381 uint8_t mlcqe_se:1; 382 uint8_t mlcqe_format:2; 383 uint8_t mlcqe_opcode:4; 384 #endif 385 }; 386 } mlxcx_completionq_ent_t; 387 388 typedef struct { 389 uint8_t mlcqe_data[64]; 390 mlxcx_completionq_ent_t mlcqe_ent; 391 } mlxcx_completionq_ent128_t; 392 393 typedef enum { 394 MLXCX_WQE_OP_NOP = 0x00, 395 MLXCX_WQE_OP_SEND_INVALIDATE = 0x01, 396 MLXCX_WQE_OP_RDMA_W = 0x08, 397 MLXCX_WQE_OP_RDMA_W_IMMEDIATE = 0x09, 398 MLXCX_WQE_OP_SEND = 0x0A, 399 MLXCX_WQE_OP_SEND_IMMEDIATE = 0x0B, 400 MLXCX_WQE_OP_LSO = 0x0E, 401 MLXCX_WQE_OP_WAIT = 0x0F, 402 MLXCX_WQE_OP_RDMA_R = 0x10, 403 } mlxcx_wqe_opcode_t; 404 405 #define MLXCX_WQE_OCTOWORD 16 406 #define MLXCX_SQE_MAX_DS ((1 << 6) - 1) 407 /* 408 * Calculate the max number of address pointers in a single ethernet 409 * send message. This is the remainder from MLXCX_SQE_MAX_DS 410 * after accounting for the Control and Ethernet segements. 411 */ 412 #define MLXCX_SQE_MAX_PTRS (MLXCX_SQE_MAX_DS - \ 413 (sizeof (mlxcx_wqe_eth_seg_t) + sizeof (mlxcx_wqe_control_seg_t)) / \ 414 MLXCX_WQE_OCTOWORD) 415 416 typedef enum { 417 MLXCX_SQE_FENCE_NONE = 0x0, 418 MLXCX_SQE_FENCE_WAIT_OTHERS = 0x1, 419 MLXCX_SQE_FENCE_START = 0x2, 420 MLXCX_SQE_FENCE_STRONG_ORDER = 0x3, 421 MLXCX_SQE_FENCE_START_WAIT = 0x4 422 } mlxcx_sqe_fence_mode_t; 423 424 typedef enum { 425 MLXCX_SQE_CQE_ON_EACH_ERROR = 0x0, 426 MLXCX_SQE_CQE_ON_FIRST_ERROR = 0x1, 427 MLXCX_SQE_CQE_ALWAYS = 0x2, 428 MLXCX_SQE_CQE_ALWAYS_PLUS_EQE = 0x3 429 } mlxcx_sqe_completion_mode_t; 430 431 #define MLXCX_SQE_SOLICITED (1 << 1) 432 /* CSTYLED */ 433 #define MLXCX_SQE_FENCE_MODE (bitdef_t){5, 0xe0} 434 /* CSTYLED */ 435 #define MLXCX_SQE_COMPLETION_MODE (bitdef_t){2, 0x0c} 436 437 typedef struct { 438 uint8_t mlcs_opcode_mod; 439 uint16be_t mlcs_wqe_index; 440 uint8_t mlcs_opcode; 441 uint24be_t mlcs_qp_or_sq; 442 uint8_t mlcs_ds; 443 uint8_t mlcs_signature; 444 uint8_t mlcs_rsvd2[2]; 445 bits8_t mlcs_flags; 446 uint32be_t mlcs_immediate; 447 } mlxcx_wqe_control_seg_t; 448 449 typedef enum { 450 MLXCX_SQE_ETH_CSFLAG_L4_CHECKSUM = 1 << 7, 451 MLXCX_SQE_ETH_CSFLAG_L3_CHECKSUM = 1 << 6, 452 MLXCX_SQE_ETH_CSFLAG_L4_INNER_CHECKSUM = 1 << 5, 453 MLXCX_SQE_ETH_CSFLAG_L3_INNER_CHECKSUM = 1 << 4, 454 } mlxcx_wqe_eth_flags_t; 455 456 /* CSTYLED */ 457 #define MLXCX_SQE_ETH_INLINE_HDR_SZ (bitdef_t){0, 0x03ff} 458 #define MLXCX_SQE_ETH_SZFLAG_VLAN (1 << 15) 459 #define MLXCX_MAX_INLINE_HEADERLEN 64 460 461 typedef struct { 462 uint8_t mles_rsvd[4]; 463 bits8_t mles_csflags; 464 uint8_t mles_rsvd2[1]; 465 uint16_t mles_mss; 466 uint8_t mles_rsvd3[4]; 467 bits16_t mles_szflags; 468 uint8_t mles_inline_headers[18]; 469 } mlxcx_wqe_eth_seg_t; 470 471 typedef struct { 472 uint32be_t mlds_byte_count; 473 uint32be_t mlds_lkey; 474 uint64be_t mlds_address; 475 } mlxcx_wqe_data_seg_t; 476 477 #define MLXCX_SENDQ_STRIDE_SHIFT 6 478 479 typedef struct { 480 mlxcx_wqe_control_seg_t mlsqe_control; 481 mlxcx_wqe_eth_seg_t mlsqe_eth; 482 mlxcx_wqe_data_seg_t mlsqe_data[1]; 483 } mlxcx_sendq_ent_t; 484 485 typedef struct { 486 uint64be_t mlsqbf_qwords[8]; 487 } mlxcx_sendq_bf_t; 488 489 typedef struct { 490 mlxcx_wqe_data_seg_t mlsqe_data[4]; 491 } mlxcx_sendq_extra_ent_t; 492 493 #define MLXCX_RECVQ_STRIDE_SHIFT 7 494 /* 495 * Each mlxcx_wqe_data_seg_t is 1<<4 bytes long (there's a CTASSERT to verify 496 * this in mlxcx_cmd.c), so the number of pointers is 1 << (shift - 4). 497 */ 498 #define MLXCX_RECVQ_MAX_PTRS (1 << (MLXCX_RECVQ_STRIDE_SHIFT - 4)) 499 typedef struct { 500 mlxcx_wqe_data_seg_t mlrqe_data[MLXCX_RECVQ_MAX_PTRS]; 501 } mlxcx_recvq_ent_t; 502 503 /* CSTYLED */ 504 #define MLXCX_CQ_ARM_CI (bitdef_t){ .bit_shift = 0, \ 505 .bit_mask = 0x00ffffff } 506 /* CSTYLED */ 507 #define MLXCX_CQ_ARM_SEQ (bitdef_t){ .bit_shift = 28, \ 508 .bit_mask = 0x30000000 } 509 #define MLXCX_CQ_ARM_SOLICITED (1 << 24) 510 511 typedef struct { 512 uint8_t mlcqd_rsvd; 513 uint24be_t mlcqd_update_ci; 514 bits32_t mlcqd_arm_ci; 515 } mlxcx_completionq_doorbell_t; 516 517 typedef struct { 518 uint16be_t mlwqd_rsvd; 519 uint16be_t mlwqd_recv_counter; 520 uint16be_t mlwqd_rsvd2; 521 uint16be_t mlwqd_send_counter; 522 } mlxcx_workq_doorbell_t; 523 524 #define MLXCX_EQ_STATUS_OK (0x0 << 4) 525 #define MLXCX_EQ_STATUS_WRITE_FAILURE (0xA << 4) 526 527 #define MLXCX_EQ_OI (1 << 1) 528 #define MLXCX_EQ_EC (1 << 2) 529 530 #define MLXCX_EQ_ST_ARMED 0x9 531 #define MLXCX_EQ_ST_FIRED 0xA 532 533 /* CSTYLED */ 534 #define MLXCX_EQ_LOG_PAGE_SIZE (bitdef_t){ .bit_shift = 24, \ 535 .bit_mask = 0x1F000000 } 536 537 typedef struct { 538 uint8_t mleqc_status; 539 uint8_t mleqc_ecoi; 540 uint8_t mleqc_state; 541 uint8_t mleqc_rsvd[7]; 542 uint16be_t mleqc_page_offset; 543 uint8_t mleqc_log_eq_size; 544 uint24be_t mleqc_uar_page; 545 uint8_t mleqc_rsvd3[7]; 546 uint8_t mleqc_intr; 547 uint32be_t mleqc_log_page; 548 uint8_t mleqc_rsvd4[13]; 549 uint24be_t mleqc_consumer_counter; 550 uint8_t mleqc_rsvd5; 551 uint24be_t mleqc_producer_counter; 552 uint8_t mleqc_rsvd6[16]; 553 } mlxcx_eventq_ctx_t; 554 555 typedef enum { 556 MLXCX_CQC_CQE_SIZE_64 = 0x0, 557 MLXCX_CQC_CQE_SIZE_128 = 0x1, 558 } mlxcx_cqc_cqe_sz_t; 559 560 typedef enum { 561 MLXCX_CQC_STATUS_OK = 0x0, 562 MLXCX_CQC_STATUS_OVERFLOW = 0x9, 563 MLXCX_CQC_STATUS_WRITE_FAIL = 0xA, 564 MLXCX_CQC_STATUS_INVALID = 0xF 565 } mlxcx_cqc_status_t; 566 567 typedef enum { 568 MLXCX_CQC_STATE_ARMED_SOLICITED = 0x6, 569 MLXCX_CQC_STATE_ARMED = 0x9, 570 MLXCX_CQC_STATE_FIRED = 0xA 571 } mlxcx_cqc_state_t; 572 573 /* CSTYLED */ 574 #define MLXCX_CQ_CTX_STATUS (bitdef_t){28, 0xf0000000} 575 /* CSTYLED */ 576 #define MLXCX_CQ_CTX_CQE_SZ (bitdef_t){21, 0x00e00000} 577 /* CSTYLED */ 578 #define MLXCX_CQ_CTX_PERIOD_MODE (bitdef_t){15, 0x00018000} 579 /* CSTYLED */ 580 #define MLXCX_CQ_CTX_MINI_CQE_FORMAT (bitdef_t){12, 0x00003000} 581 /* CSTYLED */ 582 #define MLXCX_CQ_CTX_STATE (bitdef_t){8, 0x00000f00} 583 584 typedef struct mlxcx_completionq_ctx { 585 bits32_t mlcqc_flags; 586 587 uint8_t mlcqc_rsvd4[4]; 588 589 uint8_t mlcqc_rsvd5[2]; 590 uint16be_t mlcqc_page_offset; 591 592 uint8_t mlcqc_log_cq_size; 593 uint24be_t mlcqc_uar_page; 594 595 uint16be_t mlcqc_cq_period; 596 uint16be_t mlcqc_cq_max_count; 597 598 uint8_t mlcqc_rsvd7[3]; 599 uint8_t mlcqc_eqn; 600 601 uint8_t mlcqc_log_page_size; 602 uint8_t mlcqc_rsvd8[3]; 603 604 uint8_t mlcqc_rsvd9[4]; 605 606 uint8_t mlcqc_rsvd10; 607 uint24be_t mlcqc_last_notified_index; 608 uint8_t mlcqc_rsvd11; 609 uint24be_t mlcqc_last_solicit_index; 610 uint8_t mlcqc_rsvd12; 611 uint24be_t mlcqc_consumer_counter; 612 uint8_t mlcqc_rsvd13; 613 uint24be_t mlcqc_producer_counter; 614 615 uint8_t mlcqc_rsvd14[8]; 616 617 uint64be_t mlcqc_dbr_addr; 618 } mlxcx_completionq_ctx_t; 619 620 typedef enum { 621 MLXCX_WORKQ_TYPE_LINKED_LIST = 0x0, 622 MLXCX_WORKQ_TYPE_CYCLIC = 0x1, 623 MLXCX_WORKQ_TYPE_LINKED_LIST_STRIDING = 0x2, 624 MLXCX_WORKQ_TYPE_CYCLIC_STRIDING = 0x3 625 } mlxcx_workq_ctx_type_t; 626 627 typedef enum { 628 MLXCX_WORKQ_END_PAD_NONE = 0x0, 629 MLXCX_WORKQ_END_PAD_ALIGN = 0x1 630 } mlxcx_workq_end_padding_t; 631 632 /* CSTYLED */ 633 #define MLXCX_WORKQ_CTX_TYPE (bitdef_t){ \ 634 .bit_shift = 28, \ 635 .bit_mask = 0xf0000000 } 636 #define MLXCX_WORKQ_CTX_SIGNATURE (1 << 27) 637 #define MLXCX_WORKQ_CTX_CD_SLAVE (1 << 24) 638 /* CSTYLED */ 639 #define MLXCX_WORKQ_CTX_END_PADDING (bitdef_t){ \ 640 .bit_shift = 25, \ 641 .bit_mask = 0x06000000 } 642 643 #define MLXCX_WORKQ_CTX_MAX_ADDRESSES 128 644 645 typedef struct mlxcx_workq_ctx { 646 bits32_t mlwqc_flags; 647 uint8_t mlwqc_rsvd[2]; 648 uint16be_t mlwqc_lwm; 649 uint8_t mlwqc_rsvd2; 650 uint24be_t mlwqc_pd; 651 uint8_t mlwqc_rsvd3; 652 uint24be_t mlwqc_uar_page; 653 uint64be_t mlwqc_dbr_addr; 654 uint32be_t mlwqc_hw_counter; 655 uint32be_t mlwqc_sw_counter; 656 uint8_t mlwqc_rsvd4; 657 uint8_t mlwqc_log_wq_stride; 658 uint8_t mlwqc_log_wq_pg_sz; 659 uint8_t mlwqc_log_wq_sz; 660 uint8_t mlwqc_rsvd5[2]; 661 bits16_t mlwqc_strides; 662 uint8_t mlwqc_rsvd6[152]; 663 uint64be_t mlwqc_pas[MLXCX_WORKQ_CTX_MAX_ADDRESSES]; 664 } mlxcx_workq_ctx_t; 665 666 #define MLXCX_RQ_FLAGS_RLKEY (1UL << 31) 667 #define MLXCX_RQ_FLAGS_SCATTER_FCS (1 << 29) 668 #define MLXCX_RQ_FLAGS_VLAN_STRIP_DISABLE (1 << 28) 669 #define MLXCX_RQ_FLAGS_FLUSH_IN_ERROR (1 << 18) 670 /* CSTYLED */ 671 #define MLXCX_RQ_MEM_RQ_TYPE (bitdef_t){ \ 672 .bit_shift = 24, \ 673 .bit_mask = 0x0f000000 } 674 /* CSTYLED */ 675 #define MLXCX_RQ_STATE (bitdef_t){ \ 676 .bit_shift = 20, \ 677 .bit_mask = 0x00f00000 } 678 679 typedef struct mlxcx_rq_ctx { 680 bits32_t mlrqc_flags; 681 uint8_t mlrqc_rsvd; 682 uint24be_t mlrqc_user_index; 683 uint8_t mlrqc_rsvd2; 684 uint24be_t mlrqc_cqn; 685 uint8_t mlrqc_counter_set_id; 686 uint8_t mlrqc_rsvd3[4]; 687 uint24be_t mlrqc_rmpn; 688 uint8_t mlrqc_rsvd4[28]; 689 mlxcx_workq_ctx_t mlrqc_wq; 690 } mlxcx_rq_ctx_t; 691 692 #define MLXCX_SQ_FLAGS_RLKEY (1UL << 31) 693 #define MLXCX_SQ_FLAGS_CD_MASTER (1 << 30) 694 #define MLXCX_SQ_FLAGS_FRE (1 << 29) 695 #define MLXCX_SQ_FLAGS_FLUSH_IN_ERROR (1 << 28) 696 #define MLXCX_SQ_FLAGS_ALLOW_MULTI_PKT (1 << 27) 697 #define MLXCX_SQ_FLAGS_REG_UMR (1 << 19) 698 699 typedef enum { 700 MLXCX_ETH_CAP_INLINE_REQUIRE_L2 = 0, 701 MLXCX_ETH_CAP_INLINE_VPORT_CTX = 1, 702 MLXCX_ETH_CAP_INLINE_NOT_REQUIRED = 2 703 } mlxcx_eth_cap_inline_mode_t; 704 705 typedef enum { 706 MLXCX_ETH_INLINE_NONE = 0, 707 MLXCX_ETH_INLINE_L2 = 1, 708 MLXCX_ETH_INLINE_L3 = 2, 709 MLXCX_ETH_INLINE_L4 = 3, 710 MLXCX_ETH_INLINE_INNER_L2 = 5, 711 MLXCX_ETH_INLINE_INNER_L3 = 6, 712 MLXCX_ETH_INLINE_INNER_L4 = 7 713 } mlxcx_eth_inline_mode_t; 714 715 /* CSTYLED */ 716 #define MLXCX_SQ_MIN_WQE_INLINE (bitdef_t){ \ 717 .bit_shift = 24, \ 718 .bit_mask = 0x07000000 } 719 /* CSTYLED */ 720 #define MLXCX_SQ_STATE (bitdef_t){ \ 721 .bit_shift = 20, \ 722 .bit_mask = 0x00f00000 } 723 724 typedef struct mlxcx_sq_ctx { 725 bits32_t mlsqc_flags; 726 uint8_t mlsqc_rsvd; 727 uint24be_t mlsqc_user_index; 728 uint8_t mlsqc_rsvd2; 729 uint24be_t mlsqc_cqn; 730 uint8_t mlsqc_rsvd3[18]; 731 uint16be_t mlsqc_packet_pacing_rate_limit_index; 732 uint16be_t mlsqc_tis_lst_sz; 733 uint8_t mlsqc_rsvd4[11]; 734 uint24be_t mlsqc_tis_num; 735 mlxcx_workq_ctx_t mlsqc_wq; 736 } mlxcx_sq_ctx_t; 737 738 #define MLXCX_NIC_VPORT_CTX_MAX_ADDRESSES 64 739 740 typedef enum { 741 MLXCX_VPORT_PROMISC_UCAST = 1 << 15, 742 MLXCX_VPORT_PROMISC_MCAST = 1 << 14, 743 MLXCX_VPORT_PROMISC_ALL = 1 << 13 744 } mlxcx_nic_vport_ctx_promisc_t; 745 746 #define MLXCX_VPORT_LIST_TYPE_MASK 0x07 747 #define MLXCX_VPORT_LIST_TYPE_SHIFT 0 748 749 /* CSTYLED */ 750 #define MLXCX_VPORT_CTX_MIN_WQE_INLINE (bitdef_t){56, 0x0700000000000000} 751 752 typedef struct { 753 bits64_t mlnvc_flags; 754 uint8_t mlnvc_rsvd[28]; 755 uint8_t mlnvc_rsvd2[2]; 756 uint16be_t mlnvc_mtu; 757 uint64be_t mlnvc_system_image_guid; 758 uint64be_t mlnvc_port_guid; 759 uint64be_t mlnvc_node_guid; 760 uint8_t mlnvc_rsvd3[40]; 761 uint16be_t mlnvc_qkey_violation_counter; 762 uint8_t mlnvc_rsvd4[2]; 763 uint8_t mlnvc_rsvd5[132]; 764 bits16_t mlnvc_promisc_list_type; 765 uint16be_t mlnvc_allowed_list_size; 766 uint8_t mlnvc_rsvd6[2]; 767 uint8_t mlnvc_permanent_address[6]; 768 uint8_t mlnvc_rsvd7[4]; 769 uint64be_t mlnvc_address[MLXCX_NIC_VPORT_CTX_MAX_ADDRESSES]; 770 } mlxcx_nic_vport_ctx_t; 771 772 typedef struct { 773 uint8_t mlftc_flags; 774 uint8_t mlftc_level; 775 uint8_t mlftc_rsvd; 776 uint8_t mlftc_log_size; 777 uint8_t mlftc_rsvd2; 778 uint24be_t mlftc_table_miss_id; 779 uint8_t mlftc_rsvd3[4]; 780 uint8_t mlftc_rsvd4[28]; 781 } mlxcx_flow_table_ctx_t; 782 783 /* CSTYLED */ 784 #define MLXCX_FLOW_HDR_FIRST_VID (bitdef_t){0, 0x07ff} 785 /* CSTYLED */ 786 #define MLXCX_FLOW_HDR_FIRST_PRIO (bitdef_t){13,0x7000} 787 #define MLXCX_FLOW_HDR_FIRST_CFI (1 << 12) 788 789 #define MLXCX_FLOW_HDR_IP_DSCP_SHIFT 18 790 #define MLXCX_FLOW_HDR_IP_DSCP_MASK 0xfc0000 791 #define MLXCX_FLOW_HDR_IP_ECN_SHIFT 16 792 #define MLXCX_FLOW_HDR_IP_ECN_MASK 0x030000 793 #define MLXCX_FLOW_HDR_CVLAN_TAG (1 << 15) 794 #define MLXCX_FLOW_HDR_SVLAN_TAG (1 << 14) 795 #define MLXCX_FLOW_HDR_FRAG (1 << 13) 796 /* CSTYLED */ 797 #define MLXCX_FLOW_HDR_IP_VERSION (bitdef_t){ \ 798 .bit_shift = 9, \ 799 .bit_mask = 0x001e00 } 800 /* CSTYLED */ 801 #define MLXCX_FLOW_HDR_TCP_FLAGS (bitdef_t){ \ 802 .bit_shift = 0, \ 803 .bit_mask = 0x0001ff } 804 805 typedef struct { 806 uint8_t mlfh_smac[6]; 807 uint16be_t mlfh_ethertype; 808 uint8_t mlfh_dmac[6]; 809 bits16_t mlfh_first_vid_flags; 810 uint8_t mlfh_ip_protocol; 811 bits24_t mlfh_tcp_ip_flags; 812 uint16be_t mlfh_tcp_sport; 813 uint16be_t mlfh_tcp_dport; 814 uint8_t mlfh_rsvd[3]; 815 uint8_t mlfh_ip_ttl_hoplimit; 816 uint16be_t mlfh_udp_sport; 817 uint16be_t mlfh_udp_dport; 818 uint8_t mlfh_src_ip[16]; 819 uint8_t mlfh_dst_ip[16]; 820 } mlxcx_flow_header_match_t; 821 822 typedef struct { 823 uint8_t mlfp_rsvd; 824 uint24be_t mlfp_source_sqn; 825 uint8_t mlfp_rsvd2[2]; 826 uint16be_t mlfp_source_port; 827 bits16_t mlfp_outer_second_vid_flags; 828 bits16_t mlfp_inner_second_vid_flags; 829 bits16_t mlfp_vlan_flags; 830 uint16be_t mlfp_gre_protocol; 831 uint32be_t mlfp_gre_key; 832 uint24be_t mlfp_vxlan_vni; 833 uint8_t mlfp_rsvd3; 834 uint8_t mlfp_rsvd4[4]; 835 uint8_t mlfp_rsvd5; 836 uint24be_t mlfp_outer_ipv6_flow_label; 837 uint8_t mlfp_rsvd6; 838 uint24be_t mlfp_inner_ipv6_flow_label; 839 uint8_t mlfp_rsvd7[28]; 840 } mlxcx_flow_params_match_t; 841 842 typedef struct { 843 mlxcx_flow_header_match_t mlfm_outer_headers; 844 mlxcx_flow_params_match_t mlfm_misc_parameters; 845 mlxcx_flow_header_match_t mlfm_inner_headers; 846 uint8_t mlfm_rsvd[320]; 847 } mlxcx_flow_match_t; 848 849 #define MLXCX_FLOW_MAX_DESTINATIONS 64 850 typedef enum { 851 MLXCX_FLOW_DEST_VPORT = 0x0, 852 MLXCX_FLOW_DEST_FLOW_TABLE = 0x1, 853 MLXCX_FLOW_DEST_TIR = 0x2, 854 MLXCX_FLOW_DEST_QP = 0x3 855 } mlxcx_flow_destination_type_t; 856 857 typedef struct { 858 uint8_t mlfd_destination_type; 859 uint24be_t mlfd_destination_id; 860 uint8_t mlfd_rsvd[4]; 861 } mlxcx_flow_dest_t; 862 863 typedef enum { 864 MLXCX_FLOW_ACTION_ALLOW = 1 << 0, 865 MLXCX_FLOW_ACTION_DROP = 1 << 1, 866 MLXCX_FLOW_ACTION_FORWARD = 1 << 2, 867 MLXCX_FLOW_ACTION_COUNT = 1 << 3, 868 MLXCX_FLOW_ACTION_ENCAP = 1 << 4, 869 MLXCX_FLOW_ACTION_DECAP = 1 << 5 870 } mlxcx_flow_action_t; 871 872 typedef struct { 873 uint8_t mlfec_rsvd[4]; 874 uint32be_t mlfec_group_id; 875 uint8_t mlfec_rsvd2; 876 uint24be_t mlfec_flow_tag; 877 uint8_t mlfec_rsvd3[2]; 878 uint16be_t mlfec_action; 879 uint8_t mlfec_rsvd4; 880 uint24be_t mlfec_destination_list_size; 881 uint8_t mlfec_rsvd5; 882 uint24be_t mlfec_flow_counter_list_size; 883 uint32be_t mlfec_encap_id; 884 uint8_t mlfec_rsvd6[36]; 885 mlxcx_flow_match_t mlfec_match_value; 886 uint8_t mlfec_rsvd7[192]; 887 mlxcx_flow_dest_t mlfec_destination[MLXCX_FLOW_MAX_DESTINATIONS]; 888 } mlxcx_flow_entry_ctx_t; 889 890 /* CSTYLED */ 891 #define MLXCX_TIR_CTX_DISP_TYPE (bitdef_t){ 4, 0xf0 } 892 typedef enum { 893 MLXCX_TIR_DIRECT = 0x0, 894 MLXCX_TIR_INDIRECT = 0x1, 895 } mlxcx_tir_type_t; 896 897 /* CSTYLED */ 898 #define MLXCX_TIR_LRO_TIMEOUT (bitdef_t){ 12, 0x0ffff000 } 899 /* CSTYLED */ 900 #define MLXCX_TIR_LRO_ENABLE_MASK (bitdef_t){ 8, 0x00000f00 } 901 /* CSTYLED */ 902 #define MLXCX_TIR_LRO_MAX_MSG_SZ (bitdef_t){ 0, 0x000000ff } 903 904 /* CSTYLED */ 905 #define MLXCX_TIR_RX_HASH_FN (bitdef_t){ 4, 0xf0 } 906 typedef enum { 907 MLXCX_TIR_HASH_NONE = 0x0, 908 MLXCX_TIR_HASH_XOR8 = 0x1, 909 MLXCX_TIR_HASH_TOEPLITZ = 0x2 910 } mlxcx_tir_hash_fn_t; 911 #define MLXCX_TIR_LB_UNICAST (1 << 24) 912 #define MLXCX_TIR_LB_MULTICAST (1 << 25) 913 914 /* CSTYLED */ 915 #define MLXCX_RX_HASH_L3_TYPE (bitdef_t){ 31, 0x80000000 } 916 typedef enum { 917 MLXCX_RX_HASH_L3_IPv4 = 0, 918 MLXCX_RX_HASH_L3_IPv6 = 1 919 } mlxcx_tir_rx_hash_l3_type_t; 920 /* CSTYLED */ 921 #define MLXCX_RX_HASH_L4_TYPE (bitdef_t){ 30, 0x40000000 } 922 typedef enum { 923 MLXCX_RX_HASH_L4_TCP = 0, 924 MLXCX_RX_HASH_L4_UDP = 1 925 } mlxcx_tir_rx_hash_l4_type_t; 926 /* CSTYLED */ 927 #define MLXCX_RX_HASH_FIELDS (bitdef_t){ 0, 0x3fffffff } 928 typedef enum { 929 MLXCX_RX_HASH_SRC_IP = 1 << 0, 930 MLXCX_RX_HASH_DST_IP = 1 << 1, 931 MLXCX_RX_HASH_L4_SPORT = 1 << 2, 932 MLXCX_RX_HASH_L4_DPORT = 1 << 3, 933 MLXCX_RX_HASH_IPSEC_SPI = 1 << 4 934 } mlxcx_tir_rx_hash_fields_t; 935 936 typedef struct { 937 uint8_t mltirc_rsvd[4]; 938 bits8_t mltirc_disp_type; 939 uint8_t mltirc_rsvd2[11]; 940 bits32_t mltirc_lro; 941 uint8_t mltirc_rsvd3[9]; 942 uint24be_t mltirc_inline_rqn; 943 bits8_t mltirc_flags; 944 uint24be_t mltirc_indirect_table; 945 bits8_t mltirc_hash_lb; 946 uint24be_t mltirc_transport_domain; 947 uint8_t mltirc_rx_hash_toeplitz_key[40]; 948 bits32_t mltirc_rx_hash_fields_outer; 949 bits32_t mltirc_rx_hash_fields_inner; 950 uint8_t mltirc_rsvd4[152]; 951 } mlxcx_tir_ctx_t; 952 953 typedef struct { 954 uint8_t mltisc_rsvd; 955 uint8_t mltisc_prio_or_sl; 956 uint8_t mltisc_rsvd2[35]; 957 uint24be_t mltisc_transport_domain; 958 uint8_t mltisc_rsvd3[120]; 959 } mlxcx_tis_ctx_t; 960 961 #define MLXCX_RQT_MAX_RQ_REFS 64 962 963 typedef struct { 964 uint8_t mlrqtr_rsvd; 965 uint24be_t mlrqtr_rqn; 966 } mlxcx_rqtable_rq_ref_t; 967 968 typedef struct { 969 uint8_t mlrqtc_rsvd[22]; 970 uint16be_t mlrqtc_max_size; 971 uint8_t mlrqtc_rsvd2[2]; 972 uint16be_t mlrqtc_actual_size; 973 uint8_t mlrqtc_rsvd3[212]; 974 mlxcx_rqtable_rq_ref_t mlrqtc_rqref[MLXCX_RQT_MAX_RQ_REFS]; 975 } mlxcx_rqtable_ctx_t; 976 977 #pragma pack() 978 979 typedef enum { 980 MLXCX_EVENT_COMPLETION = 0x00, 981 MLXCX_EVENT_PATH_MIGRATED = 0x01, 982 MLXCX_EVENT_COMM_ESTABLISH = 0x02, 983 MLXCX_EVENT_SENDQ_DRAIN = 0x03, 984 MLXCX_EVENT_LAST_WQE = 0x13, 985 MLXCX_EVENT_SRQ_LIMIT = 0x14, 986 MLXCX_EVENT_DCT_ALL_CLOSED = 0x1C, 987 MLXCX_EVENT_DCT_ACCKEY_VIOL = 0x1D, 988 MLXCX_EVENT_CQ_ERROR = 0x04, 989 MLXCX_EVENT_WQ_CATASTROPHE = 0x05, 990 MLXCX_EVENT_PATH_MIGRATE_FAIL = 0x07, 991 MLXCX_EVENT_PAGE_FAULT = 0x0C, 992 MLXCX_EVENT_WQ_INVALID_REQ = 0x10, 993 MLXCX_EVENT_WQ_ACCESS_VIOL = 0x11, 994 MLXCX_EVENT_SRQ_CATASTROPHE = 0x12, 995 MLXCX_EVENT_INTERNAL_ERROR = 0x08, 996 MLXCX_EVENT_PORT_STATE = 0x09, 997 MLXCX_EVENT_GPIO = 0x15, 998 MLXCX_EVENT_PORT_MODULE = 0x16, 999 MLXCX_EVENT_TEMP_WARNING = 0x17, 1000 MLXCX_EVENT_REMOTE_CONFIG = 0x19, 1001 MLXCX_EVENT_DCBX_CHANGE = 0x1E, 1002 MLXCX_EVENT_DOORBELL_CONGEST = 0x1A, 1003 MLXCX_EVENT_STALL_VL = 0x1B, 1004 MLXCX_EVENT_CMD_COMPLETION = 0x0A, 1005 MLXCX_EVENT_PAGE_REQUEST = 0x0B, 1006 MLXCX_EVENT_NIC_VPORT = 0x0D, 1007 MLXCX_EVENT_EC_PARAMS_CHANGE = 0x0E, 1008 MLXCX_EVENT_XRQ_ERROR = 0x18 1009 } mlxcx_event_t; 1010 1011 typedef enum { 1012 MLXCX_CMD_R_OK = 0x00, 1013 MLXCX_CMD_R_INTERNAL_ERR = 0x01, 1014 MLXCX_CMD_R_BAD_OP = 0x02, 1015 MLXCX_CMD_R_BAD_PARAM = 0x03, 1016 MLXCX_CMD_R_BAD_SYS_STATE = 0x04, 1017 MLXCX_CMD_R_BAD_RESOURCE = 0x05, 1018 MLXCX_CMD_R_RESOURCE_BUSY = 0x06, 1019 MLXCX_CMD_R_EXCEED_LIM = 0x08, 1020 MLXCX_CMD_R_BAD_RES_STATE = 0x09, 1021 MLXCX_CMD_R_BAD_INDEX = 0x0a, 1022 MLXCX_CMD_R_NO_RESOURCES = 0x0f, 1023 MLXCX_CMD_R_BAD_INPUT_LEN = 0x50, 1024 MLXCX_CMD_R_BAD_OUTPUT_LEN = 0x51, 1025 MLXCX_CMD_R_BAD_RESOURCE_STATE = 0x10, 1026 MLXCX_CMD_R_BAD_PKT = 0x30, 1027 MLXCX_CMD_R_BAD_SIZE = 0x40, 1028 MLXCX_CMD_R_TIMEOUT = 0xFF 1029 } mlxcx_cmd_ret_t; 1030 1031 typedef enum { 1032 MLXCX_OP_QUERY_HCA_CAP = 0x100, 1033 MLXCX_OP_QUERY_ADAPTER = 0x101, 1034 MLXCX_OP_INIT_HCA = 0x102, 1035 MLXCX_OP_TEARDOWN_HCA = 0x103, 1036 MLXCX_OP_ENABLE_HCA = 0x104, 1037 MLXCX_OP_DISABLE_HCA = 0x105, 1038 MLXCX_OP_QUERY_PAGES = 0x107, 1039 MLXCX_OP_MANAGE_PAGES = 0x108, 1040 MLXCX_OP_SET_HCA_CAP = 0x109, 1041 MLXCX_OP_QUERY_ISSI = 0x10A, 1042 MLXCX_OP_SET_ISSI = 0x10B, 1043 MLXCX_OP_SET_DRIVER_VERSION = 0x10D, 1044 MLXCX_OP_QUERY_OTHER_HCA_CAP = 0x10E, 1045 MLXCX_OP_MODIFY_OTHER_HCA_CAP = 0x10F, 1046 MLXCX_OP_SET_TUNNELED_OPERATIONS = 0x110, 1047 MLXCX_OP_CREATE_MKEY = 0x200, 1048 MLXCX_OP_QUERY_MKEY = 0x201, 1049 MLXCX_OP_DESTROY_MKEY = 0x202, 1050 MLXCX_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 1051 MLXCX_OP_PAGE_FAULT_RESUME = 0x204, 1052 MLXCX_OP_CREATE_EQ = 0x301, 1053 MLXCX_OP_DESTROY_EQ = 0x302, 1054 MLXCX_OP_QUERY_EQ = 0x303, 1055 MLXCX_OP_GEN_EQE = 0x304, 1056 MLXCX_OP_CREATE_CQ = 0x400, 1057 MLXCX_OP_DESTROY_CQ = 0x401, 1058 MLXCX_OP_QUERY_CQ = 0x402, 1059 MLXCX_OP_MODIFY_CQ = 0x403, 1060 MLXCX_OP_CREATE_QP = 0x500, 1061 MLXCX_OP_DESTROY_QP = 0x501, 1062 MLXCX_OP_RST2INIT_QP = 0x502, 1063 MLXCX_OP_INIT2RTR_QP = 0x503, 1064 MLXCX_OP_RTR2RTS_QP = 0x504, 1065 MLXCX_OP_RTS2RTS_QP = 0x505, 1066 MLXCX_OP_SQERR2RTS_QP = 0x506, 1067 MLXCX_OP__2ERR_QP = 0x507, 1068 MLXCX_OP__2RST_QP = 0x50A, 1069 MLXCX_OP_QUERY_QP = 0x50B, 1070 MLXCX_OP_SQD_RTS_QP = 0x50C, 1071 MLXCX_OP_INIT2INIT_QP = 0x50E, 1072 MLXCX_OP_CREATE_PSV = 0x600, 1073 MLXCX_OP_DESTROY_PSV = 0x601, 1074 MLXCX_OP_CREATE_SRQ = 0x700, 1075 MLXCX_OP_DESTROY_SRQ = 0x701, 1076 MLXCX_OP_QUERY_SRQ = 0x702, 1077 MLXCX_OP_ARM_RQ = 0x703, 1078 MLXCX_OP_CREATE_XRC_SRQ = 0x705, 1079 MLXCX_OP_DESTROY_XRC_SRQ = 0x706, 1080 MLXCX_OP_QUERY_XRC_SRQ = 0x707, 1081 MLXCX_OP_ARM_XRC_SRQ = 0x708, 1082 MLXCX_OP_CREATE_DCT = 0x710, 1083 MLXCX_OP_DESTROY_DCT = 0x711, 1084 MLXCX_OP_DRAIN_DCT = 0x712, 1085 MLXCX_OP_QUERY_DCT = 0x713, 1086 MLXCX_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 1087 MLXCX_OP_CREATE_XRQ = 0x717, 1088 MLXCX_OP_DESTROY_XRQ = 0x718, 1089 MLXCX_OP_QUERY_XRQ = 0x719, 1090 MLXCX_OP_CREATE_NVMF_BACKEND_CONTROLLER = 0x720, 1091 MLXCX_OP_DESTROY_NVMF_BACKEND_CONTROLLER = 0x721, 1092 MLXCX_OP_QUERY_NVMF_BACKEND_CONTROLLER = 0x722, 1093 MLXCX_OP_ATTACH_NVMF_NAMESPACE = 0x723, 1094 MLXCX_OP_DETACH_NVMF_NAMESPACE = 0x724, 1095 MLXCX_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 1096 MLXCX_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 1097 MLXCX_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 1098 MLXCX_OP_QUERY_VPORT_STATE = 0x750, 1099 MLXCX_OP_MODIFY_VPORT_STATE = 0x751, 1100 MLXCX_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 1101 MLXCX_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 1102 MLXCX_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 1103 MLXCX_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 1104 MLXCX_OP_QUERY_ROCE_ADDRESS = 0x760, 1105 MLXCX_OP_SET_ROCE_ADDRESS = 0x761, 1106 MLXCX_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 1107 MLXCX_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 1108 MLXCX_OP_QUERY_HCA_VPORT_GID = 0x764, 1109 MLXCX_OP_QUERY_HCA_VPORT_PKEY = 0x765, 1110 MLXCX_OP_QUERY_VPORT_COUNTER = 0x770, 1111 MLXCX_OP_ALLOC_Q_COUNTER = 0x771, 1112 MLXCX_OP_DEALLOC_Q_COUNTER = 0x772, 1113 MLXCX_OP_QUERY_Q_COUNTER = 0x773, 1114 MLXCX_OP_SET_PP_RATE_LIMIT = 0x780, 1115 MLXCX_OP_QUERY_PP_RATE_LIMIT = 0x781, 1116 MLXCX_OP_ALLOC_PD = 0x800, 1117 MLXCX_OP_DEALLOC_PD = 0x801, 1118 MLXCX_OP_ALLOC_UAR = 0x802, 1119 MLXCX_OP_DEALLOC_UAR = 0x803, 1120 MLXCX_OP_CONFIG_INT_MODERATION = 0x804, 1121 MLXCX_OP_ACCESS_REG = 0x805, 1122 MLXCX_OP_ATTACH_TO_MCG = 0x806, 1123 MLXCX_OP_DETACH_FROM_MCG = 0x807, 1124 MLXCX_OP_MAD_IFC = 0x50D, 1125 MLXCX_OP_QUERY_MAD_DEMUX = 0x80B, 1126 MLXCX_OP_SET_MAD_DEMUX = 0x80C, 1127 MLXCX_OP_NOP = 0x80D, 1128 MLXCX_OP_ALLOC_XRCD = 0x80E, 1129 MLXCX_OP_DEALLOC_XRCD = 0x80F, 1130 MLXCX_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 1131 MLXCX_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 1132 MLXCX_OP_QUERY_CONG_STATUS = 0x822, 1133 MLXCX_OP_MODIFY_CONG_STATUS = 0x823, 1134 MLXCX_OP_QUERY_CONG_PARAMS = 0x824, 1135 MLXCX_OP_MODIFY_CONG_PARAMS = 0x825, 1136 MLXCX_OP_QUERY_CONG_STATISTICS = 0x826, 1137 MLXCX_OP_ADD_VXLAN_UDP_DPORT = 0x827, 1138 MLXCX_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 1139 MLXCX_OP_SET_L2_TABLE_ENTRY = 0x829, 1140 MLXCX_OP_QUERY_L2_TABLE_ENTRY = 0x82A, 1141 MLXCX_OP_DELETE_L2_TABLE_ENTRY = 0x82B, 1142 MLXCX_OP_SET_WOL_ROL = 0x830, 1143 MLXCX_OP_QUERY_WOL_ROL = 0x831, 1144 MLXCX_OP_CREATE_TIR = 0x900, 1145 MLXCX_OP_MODIFY_TIR = 0x901, 1146 MLXCX_OP_DESTROY_TIR = 0x902, 1147 MLXCX_OP_QUERY_TIR = 0x903, 1148 MLXCX_OP_CREATE_SQ = 0x904, 1149 MLXCX_OP_MODIFY_SQ = 0x905, 1150 MLXCX_OP_DESTROY_SQ = 0x906, 1151 MLXCX_OP_QUERY_SQ = 0x907, 1152 MLXCX_OP_CREATE_RQ = 0x908, 1153 MLXCX_OP_MODIFY_RQ = 0x909, 1154 MLXCX_OP_DESTROY_RQ = 0x90A, 1155 MLXCX_OP_QUERY_RQ = 0x90B, 1156 MLXCX_OP_CREATE_RMP = 0x90C, 1157 MLXCX_OP_MODIFY_RMP = 0x90D, 1158 MLXCX_OP_DESTROY_RMP = 0x90E, 1159 MLXCX_OP_QUERY_RMP = 0x90F, 1160 MLXCX_OP_CREATE_TIS = 0x912, 1161 MLXCX_OP_MODIFY_TIS = 0x913, 1162 MLXCX_OP_DESTROY_TIS = 0x914, 1163 MLXCX_OP_QUERY_TIS = 0x915, 1164 MLXCX_OP_CREATE_RQT = 0x916, 1165 MLXCX_OP_MODIFY_RQT = 0x917, 1166 MLXCX_OP_DESTROY_RQT = 0x918, 1167 MLXCX_OP_QUERY_RQT = 0x919, 1168 MLXCX_OP_SET_FLOW_TABLE_ROOT = 0x92f, 1169 MLXCX_OP_CREATE_FLOW_TABLE = 0x930, 1170 MLXCX_OP_DESTROY_FLOW_TABLE = 0x931, 1171 MLXCX_OP_QUERY_FLOW_TABLE = 0x932, 1172 MLXCX_OP_CREATE_FLOW_GROUP = 0x933, 1173 MLXCX_OP_DESTROY_FLOW_GROUP = 0x934, 1174 MLXCX_OP_QUERY_FLOW_GROUP = 0x935, 1175 MLXCX_OP_SET_FLOW_TABLE_ENTRY = 0x936, 1176 MLXCX_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 1177 MLXCX_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 1178 MLXCX_OP_ALLOC_FLOW_COUNTER = 0x939, 1179 MLXCX_OP_DEALLOC_FLOW_COUNTER = 0x93a, 1180 MLXCX_OP_QUERY_FLOW_COUNTER = 0x93b, 1181 MLXCX_OP_MODIFY_FLOW_TABLE = 0x93c, 1182 MLXCX_OP_ALLOC_ENCAP_HEADER = 0x93d, 1183 MLXCX_OP_DEALLOC_ENCAP_HEADER = 0x93e, 1184 MLXCX_OP_QUERY_ENCAP_HEADER = 0x93f 1185 } mlxcx_cmd_op_t; 1186 1187 /* 1188 * Definitions for relevant commands 1189 */ 1190 #pragma pack(1) 1191 typedef struct { 1192 uint16be_t mci_opcode; 1193 uint8_t mci_rsvd[4]; 1194 uint16be_t mci_op_mod; 1195 } mlxcx_cmd_in_t; 1196 1197 typedef struct { 1198 uint8_t mco_status; 1199 uint8_t mco_rsvd[3]; 1200 uint32be_t mco_syndrome; 1201 } mlxcx_cmd_out_t; 1202 1203 typedef struct { 1204 mlxcx_cmd_in_t mlxi_enable_hca_head; 1205 uint8_t mlxi_enable_hca_rsvd[2]; 1206 uint16be_t mlxi_enable_hca_func; 1207 uint8_t mlxi_enable_hca_rsvd1[4]; 1208 } mlxcx_cmd_enable_hca_in_t; 1209 1210 typedef struct { 1211 mlxcx_cmd_out_t mlxo_enable_hca_head; 1212 uint8_t mlxo_enable_hca_rsvd[8]; 1213 } mlxcx_cmd_enable_hca_out_t; 1214 1215 typedef struct { 1216 mlxcx_cmd_in_t mlxi_disable_hca_head; 1217 uint8_t mlxi_disable_hca_rsvd[2]; 1218 uint16be_t mlxi_disable_hca_func; 1219 uint8_t mlxi_disable_hca_rsvd1[4]; 1220 } mlxcx_cmd_disable_hca_in_t; 1221 1222 typedef struct { 1223 mlxcx_cmd_out_t mlxo_disable_hca_head; 1224 uint8_t mlxo_disable_hca_rsvd[8]; 1225 } mlxcx_cmd_disable_hca_out_t; 1226 1227 typedef struct { 1228 mlxcx_cmd_in_t mlxi_query_issi_head; 1229 uint8_t mlxi_query_issi_rsvd[8]; 1230 } mlxcx_cmd_query_issi_in_t; 1231 1232 typedef struct { 1233 mlxcx_cmd_out_t mlxo_query_issi_head; 1234 uint8_t mlxo_query_issi_rsv[2]; 1235 uint16be_t mlxo_query_issi_current; 1236 uint8_t mlxo_query_issi_rsvd1[20]; 1237 /* 1238 * To date we only support version 1 of the ISSI. The last byte has the 1239 * ISSI data that we care about, therefore we phrase the struct this 1240 * way. 1241 */ 1242 uint8_t mlxo_query_issi_rsvd2[79]; 1243 uint8_t mlxo_supported_issi; 1244 } mlxcx_cmd_query_issi_out_t; 1245 1246 typedef struct { 1247 mlxcx_cmd_in_t mlxi_set_issi_head; 1248 uint8_t mlxi_set_issi_rsvd[2]; 1249 uint16be_t mlxi_set_issi_current; 1250 uint8_t mlxi_set_iss_rsvd1[4]; 1251 } mlxcx_cmd_set_issi_in_t; 1252 1253 typedef struct { 1254 mlxcx_cmd_out_t mlxo_set_issi_head; 1255 uint8_t mlxo_set_issi_rsvd[8]; 1256 } mlxcx_cmd_set_issi_out_t; 1257 1258 typedef struct { 1259 mlxcx_cmd_in_t mlxi_init_hca_head; 1260 uint8_t mlxi_init_hca_rsvd[8]; 1261 } mlxcx_cmd_init_hca_in_t; 1262 1263 typedef struct { 1264 mlxcx_cmd_out_t mlxo_init_hca_head; 1265 uint8_t mlxo_init_hca_rsvd[8]; 1266 } mlxcx_cmd_init_hca_out_t; 1267 1268 #define MLXCX_TEARDOWN_HCA_GRACEFUL 0x00 1269 #define MLXCX_TEARDOWN_HCA_FORCE 0x01 1270 1271 typedef struct { 1272 mlxcx_cmd_in_t mlxi_teardown_hca_head; 1273 uint8_t mlxi_teardown_hca_rsvd[2]; 1274 uint16be_t mlxi_teardown_hca_profile; 1275 uint8_t mlxi_teardown_hca_rsvd1[4]; 1276 } mlxcx_cmd_teardown_hca_in_t; 1277 1278 typedef struct { 1279 mlxcx_cmd_out_t mlxo_teardown_hca_head; 1280 uint8_t mlxo_teardown_hca_rsvd[7]; 1281 uint8_t mlxo_teardown_hca_state; 1282 } mlxcx_cmd_teardown_hca_out_t; 1283 1284 #define MLXCX_QUERY_PAGES_OPMOD_BOOT 0x01 1285 #define MLXCX_QUERY_PAGES_OPMOD_INIT 0x02 1286 #define MLXCX_QUERY_PAGES_OPMOD_REGULAR 0x03 1287 1288 typedef struct { 1289 mlxcx_cmd_in_t mlxi_query_pages_head; 1290 uint8_t mlxi_query_pages_rsvd[2]; 1291 uint16be_t mlxi_query_pages_func; 1292 uint8_t mlxi_query_pages_rsvd1[4]; 1293 } mlxcx_cmd_query_pages_in_t; 1294 1295 typedef struct { 1296 mlxcx_cmd_out_t mlxo_query_pages_head; 1297 uint8_t mlxo_query_pages_rsvd[2]; 1298 uint16be_t mlxo_query_pages_func; 1299 uint32be_t mlxo_query_pages_npages; 1300 } mlxcx_cmd_query_pages_out_t; 1301 1302 #define MLXCX_MANAGE_PAGES_OPMOD_ALLOC_FAIL 0x00 1303 #define MLXCX_MANAGE_PAGES_OPMOD_GIVE_PAGES 0x01 1304 #define MLXCX_MANAGE_PAGES_OPMOD_RETURN_PAGES 0x02 1305 1306 /* 1307 * This is an artificial limit that we're imposing on our actions. 1308 * Large enough to limit the number of manage pages calls we have to 1309 * make, but not so large that it will overflow any of the command 1310 * mailboxes. 1311 */ 1312 #define MLXCX_MANAGE_PAGES_MAX_PAGES 4096 1313 1314 typedef struct { 1315 mlxcx_cmd_in_t mlxi_manage_pages_head; 1316 uint8_t mlxi_manage_pages_rsvd[2]; 1317 uint16be_t mlxi_manage_pages_func; 1318 uint32be_t mlxi_manage_pages_npages; 1319 uint64be_t mlxi_manage_pages_pas[]; 1320 } mlxcx_cmd_manage_pages_in_t; 1321 1322 typedef struct { 1323 mlxcx_cmd_out_t mlxo_manage_pages_head; 1324 uint32be_t mlxo_manage_pages_npages; 1325 uint8_t mlxo_manage_pages_rsvd[4]; 1326 uint64be_t mlxo_manage_pages_pas[]; 1327 } mlxcx_cmd_manage_pages_out_t; 1328 1329 typedef enum { 1330 MLXCX_HCA_CAP_MODE_MAX = 0x0, 1331 MLXCX_HCA_CAP_MODE_CURRENT = 0x1 1332 } mlxcx_hca_cap_mode_t; 1333 1334 typedef enum { 1335 MLXCX_HCA_CAP_GENERAL = 0x0, 1336 MLXCX_HCA_CAP_ETHERNET = 0x1, 1337 MLXCX_HCA_CAP_ODP = 0x2, 1338 MLXCX_HCA_CAP_ATOMIC = 0x3, 1339 MLXCX_HCA_CAP_ROCE = 0x4, 1340 MLXCX_HCA_CAP_IPoIB = 0x5, 1341 MLXCX_HCA_CAP_NIC_FLOW = 0x7, 1342 MLXCX_HCA_CAP_ESWITCH_FLOW = 0x8, 1343 MLXCX_HCA_CAP_ESWITCH = 0x9, 1344 MLXCX_HCA_CAP_VECTOR = 0xb, 1345 MLXCX_HCA_CAP_QoS = 0xc, 1346 MLXCX_HCA_CAP_NVMEoF = 0xe 1347 } mlxcx_hca_cap_type_t; 1348 1349 typedef enum { 1350 MLXCX_CAP_GENERAL_PORT_TYPE_IB = 0x0, 1351 MLXCX_CAP_GENERAL_PORT_TYPE_ETHERNET = 0x1, 1352 } mlxcx_hca_cap_general_port_type_t; 1353 1354 typedef enum { 1355 MLXCX_CAP_GENERAL_FLAGS_C_PCAM_REG = (1 << 5), 1356 MLXCX_CAP_GENERAL_FLAGS_C_ESW_FLOW_TABLE = (1 << 8), 1357 MLXCX_CAP_GENERAL_FLAGS_C_NIC_FLOW_TABLE = (1 << 9), 1358 } mlxcx_hca_cap_general_flags_c_t; 1359 1360 typedef struct { 1361 uint8_t mlcap_general_access_other_hca_roce; 1362 uint8_t mlcap_general_rsvd[3]; 1363 1364 uint8_t mlcap_general_rsvd2[12]; 1365 1366 uint8_t mlcap_general_log_max_srq_sz; 1367 uint8_t mlcap_general_log_max_qp_sz; 1368 uint8_t mlcap_general_rsvd3[1]; 1369 uint8_t mlcap_general_log_max_qp; 1370 1371 uint8_t mlcap_general_rsvd4[1]; 1372 uint8_t mlcap_general_log_max_srq; 1373 uint8_t mlcap_general_rsvd5[2]; 1374 1375 uint8_t mlcap_general_rsvd6[1]; 1376 uint8_t mlcap_general_log_max_cq_sz; 1377 uint8_t mlcap_general_access_register_user_max_fixed_mkey_bufs; 1378 uint8_t mlcap_general_log_max_cq; 1379 1380 uint8_t mlcap_general_log_max_eq_sz; 1381 /* NOTE: bits 0xc0 of mkey_flags are now for relaxed_ordering. */ 1382 bits8_t mlcap_general_log_max_mkey_flags; 1383 uint8_t mlcap_general_rsvd8[1]; 1384 /* NOTE: bit 0x80 of max_eq is now for fast_teardown. */ 1385 bits8_t mlcap_general_log_max_eq; 1386 1387 uint8_t mlcap_general_max_indirection; 1388 uint8_t mlcap_general_log_max_mrw_sz_flags; 1389 /* NOTE: bit 0x80 of bsf_list is now for force_teardown. */ 1390 bits8_t mlcap_general_log_max_bsf_list_size_flags; 1391 uint8_t mlcap_general_log_max_klm_list_size_flags; 1392 1393 uint8_t mlcap_general_rsvd9[1]; 1394 uint8_t mlcap_general_log_max_ra_req_dc; 1395 uint8_t mlcap_general_rsvd10[1]; 1396 uint8_t mlcap_general_log_max_ra_res_dc; 1397 1398 uint8_t mlcap_general_rsvd11[1]; 1399 uint8_t mlcap_general_log_max_ra_req_qp; 1400 uint8_t mlcap_general_rsvd12[1]; 1401 uint8_t mlcap_general_log_max_ra_res_qp; 1402 1403 uint16be_t mlcap_general_flags_a; 1404 uint16be_t mlcap_general_gid_table_size; 1405 1406 /* NOTE: bits 0x3ff of flags_b are for max_qp_count */ 1407 bits16_t mlcap_general_flags_b; 1408 uint16be_t mlcap_general_pkey_table_size; 1409 1410 bits16_t mlcap_general_flags_c; 1411 struct { 1412 #if defined(_BIT_FIELDS_HTOL) 1413 uint8_t mlcap_general_flags_d:6; 1414 uint8_t mlcap_general_port_type:2; 1415 #elif defined(_BIT_FIELDS_LTOH) 1416 uint8_t mlcap_general_port_type:2; 1417 uint8_t mlcap_general_flags_d:6; 1418 #endif 1419 }; 1420 uint8_t mlcap_general_num_ports; 1421 1422 struct { 1423 #if defined(_BIT_FIELDS_HTOL) 1424 uint8_t mlcap_general_rsvd13:3; 1425 uint8_t mlcap_general_log_max_msg:5; 1426 #elif defined(_BIT_FIELDS_LTOH) 1427 uint8_t mlcap_general_log_max_msg:5; 1428 uint8_t mlcap_general_rsvd13:3; 1429 #endif 1430 }; 1431 uint8_t mlcap_general_max_tc; 1432 bits16_t mlcap_general_flags_d_wol; 1433 1434 uint16be_t mlcap_general_state_rate_support; 1435 uint8_t mlcap_general_rsvd14[1]; 1436 struct { 1437 #if defined(_BIT_FIELDS_HTOL) 1438 uint8_t mlcap_general_rsvd15:4; 1439 uint8_t mlcap_general_cqe_version:4; 1440 #elif defined(_BIT_FIELDS_LTOH) 1441 uint8_t mlcap_general_cqe_version:4; 1442 uint8_t mlcap_general_rsvd15:4; 1443 #endif 1444 }; 1445 1446 uint32be_t mlcap_general_flags_e; 1447 1448 uint32be_t mlcap_general_flags_f; 1449 1450 uint8_t mlcap_general_rsvd16[1]; 1451 uint8_t mlcap_general_uar_sz; 1452 uint8_t mlcap_general_cnak; 1453 uint8_t mlcap_general_log_pg_sz; 1454 uint8_t mlcap_general_rsvd17[32]; 1455 bits8_t mlcap_general_log_max_rq_flags; 1456 uint8_t mlcap_general_log_max_sq; 1457 uint8_t mlcap_general_log_max_tir; 1458 uint8_t mlcap_general_log_max_tis; 1459 } mlxcx_hca_cap_general_caps_t; 1460 1461 typedef enum { 1462 MLXCX_ETH_CAP_TUNNEL_STATELESS_VXLAN = 1 << 0, 1463 MLXCX_ETH_CAP_TUNNEL_STATELESS_GRE = 1 << 1, 1464 MLXCX_ETH_CAP_TUNNEL_LSO_CONST_OUT_IP_ID = 1 << 4, 1465 MLXCX_ETH_CAP_SCATTER_FCS = 1 << 6, 1466 MLXCX_ETH_CAP_REG_UMR_SQ = 1 << 7, 1467 MLXCX_ETH_CAP_SELF_LB_UC = 1 << 21, 1468 MLXCX_ETH_CAP_SELF_LB_MC = 1 << 22, 1469 MLXCX_ETH_CAP_SELF_LB_EN_MODIFIABLE = 1 << 23, 1470 MLXCX_ETH_CAP_WQE_VLAN_INSERT = 1 << 24, 1471 MLXCX_ETH_CAP_LRO_TIME_STAMP = 1 << 27, 1472 MLXCX_ETH_CAP_LRO_PSH_FLAG = 1 << 28, 1473 MLXCX_ETH_CAP_LRO_CAP = 1 << 29, 1474 MLXCX_ETH_CAP_VLAN_STRIP = 1 << 30, 1475 MLXCX_ETH_CAP_CSUM_CAP = 1UL << 31 1476 } mlxcx_hca_eth_cap_flags_t; 1477 1478 /* CSTYLED */ 1479 #define MLXCX_ETH_CAP_RSS_IND_TBL_CAP (bitdef_t){8, 0x00000f00} 1480 /* CSTYLED */ 1481 #define MLXCX_ETH_CAP_WQE_INLINE_MODE (bitdef_t){12, 0x00003000} 1482 /* CSTYLED */ 1483 #define MLXCX_ETH_CAP_MULTI_PKT_SEND_WQE (bitdef_t){14, 0x0000c000} 1484 /* CSTYLED */ 1485 #define MLXCX_ETH_CAP_MAX_LSO_CAP (bitdef_t){16, 0x001f0000} 1486 /* CSTYLED */ 1487 #define MLXCX_ETH_CAP_LRO_MAX_MSG_SZ_MODE (bitdef_t){25, 0x06000000} 1488 1489 typedef struct { 1490 bits32_t mlcap_eth_flags; 1491 uint8_t mlcap_eth_rsvd[6]; 1492 uint16be_t mlcap_eth_lro_min_mss_size; 1493 uint8_t mlcap_eth_rsvd2[36]; 1494 uint32be_t mlcap_eth_lro_timer_supported_periods[4]; 1495 } mlxcx_hca_cap_eth_caps_t; 1496 1497 typedef enum { 1498 MLXCX_FLOW_CAP_PROPS_DECAP = 1 << 23, 1499 MLXCX_FLOW_CAP_PROPS_ENCAP = 1 << 24, 1500 MLXCX_FLOW_CAP_PROPS_MODIFY_TBL = 1 << 25, 1501 MLXCX_FLOW_CAP_PROPS_MISS_TABLE = 1 << 26, 1502 MLXCX_FLOW_CAP_PROPS_MODIFY_ROOT_TBL = 1 << 27, 1503 MLXCX_FLOW_CAP_PROPS_MODIFY = 1 << 28, 1504 MLXCX_FLOW_CAP_PROPS_COUNTER = 1 << 29, 1505 MLXCX_FLOW_CAP_PROPS_TAG = 1 << 30, 1506 MLXCX_FLOW_CAP_PROPS_SUPPORT = 1UL << 31 1507 } mlxcx_hca_cap_flow_cap_props_flags_t; 1508 1509 typedef struct { 1510 bits32_t mlcap_flow_prop_flags; 1511 uint8_t mlcap_flow_prop_log_max_ft_size; 1512 uint8_t mlcap_flow_prop_rsvd[2]; 1513 uint8_t mlcap_flow_prop_max_ft_level; 1514 uint8_t mlcap_flow_prop_rsvd2[7]; 1515 uint8_t mlcap_flow_prop_log_max_ft_num; 1516 uint8_t mlcap_flow_prop_rsvd3[2]; 1517 uint8_t mlcap_flow_prop_log_max_flow_counter; 1518 uint8_t mlcap_flow_prop_log_max_destination; 1519 uint8_t mlcap_flow_prop_rsvd4[3]; 1520 uint8_t mlcap_flow_prop_log_max_flow; 1521 uint8_t mlcap_flow_prop_rsvd5[8]; 1522 bits32_t mlcap_flow_prop_support[4]; 1523 bits32_t mlcap_flow_prop_bitmask[4]; 1524 } mlxcx_hca_cap_flow_cap_props_t; 1525 1526 typedef struct { 1527 bits32_t mlcap_flow_flags; 1528 uint8_t mlcap_flow_rsvd[60]; 1529 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_rx; 1530 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_rx_rdma; 1531 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_rx_sniffer; 1532 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_tx; 1533 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_tx_rdma; 1534 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_tx_sniffer; 1535 } mlxcx_hca_cap_flow_caps_t; 1536 1537 /* 1538 * Size of a buffer that is required to hold the output data. 1539 */ 1540 #define MLXCX_HCA_CAP_SIZE 0x1000 1541 1542 typedef struct { 1543 mlxcx_cmd_in_t mlxi_query_hca_cap_head; 1544 uint8_t mlxi_query_hca_cap_rsvd[8]; 1545 } mlxcx_cmd_query_hca_cap_in_t; 1546 1547 typedef struct { 1548 mlxcx_cmd_out_t mlxo_query_hca_cap_head; 1549 uint8_t mlxo_query_hca_cap_rsvd[8]; 1550 uint8_t mlxo_query_hca_cap_data[MLXCX_HCA_CAP_SIZE]; 1551 } mlxcx_cmd_query_hca_cap_out_t; 1552 1553 typedef struct { 1554 mlxcx_cmd_in_t mlxi_set_driver_version_head; 1555 uint8_t mlxi_set_driver_version_rsvd[8]; 1556 char mlxi_set_driver_version_version[64]; 1557 } mlxcx_cmd_set_driver_version_in_t; 1558 1559 typedef struct { 1560 mlxcx_cmd_out_t mlxo_set_driver_version_head; 1561 uint8_t mlxo_set_driver_version_rsvd[8]; 1562 } mlxcx_cmd_set_driver_version_out_t; 1563 1564 typedef struct { 1565 mlxcx_cmd_in_t mlxi_alloc_uar_head; 1566 uint8_t mlxi_alloc_uar_rsvd[8]; 1567 } mlxcx_cmd_alloc_uar_in_t; 1568 1569 typedef struct { 1570 mlxcx_cmd_out_t mlxo_alloc_uar_head; 1571 uint8_t mlxo_alloc_uar_rsvd; 1572 uint24be_t mlxo_alloc_uar_uar; 1573 uint8_t mlxo_alloc_uar_rsvd2[4]; 1574 } mlxcx_cmd_alloc_uar_out_t; 1575 1576 typedef struct { 1577 mlxcx_cmd_in_t mlxi_dealloc_uar_head; 1578 uint8_t mlxi_dealloc_uar_rsvd; 1579 uint24be_t mlxi_dealloc_uar_uar; 1580 uint8_t mlxi_dealloc_uar_rsvd2[4]; 1581 } mlxcx_cmd_dealloc_uar_in_t; 1582 1583 typedef struct { 1584 mlxcx_cmd_out_t mlxo_dealloc_uar_head; 1585 uint8_t mlxo_dealloc_uar_rsvd[8]; 1586 } mlxcx_cmd_dealloc_uar_out_t; 1587 1588 /* 1589 * This is an artificial limit that we're imposing on our actions. 1590 */ 1591 #define MLXCX_CREATE_QUEUE_MAX_PAGES 128 1592 1593 typedef struct { 1594 mlxcx_cmd_in_t mlxi_create_eq_head; 1595 uint8_t mlxi_create_eq_rsvd[8]; 1596 mlxcx_eventq_ctx_t mlxi_create_eq_context; 1597 uint8_t mlxi_create_eq_rsvd2[8]; 1598 uint64be_t mlxi_create_eq_event_bitmask; 1599 uint8_t mlxi_create_eq_rsvd3[176]; 1600 uint64be_t mlxi_create_eq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1601 } mlxcx_cmd_create_eq_in_t; 1602 1603 typedef struct { 1604 mlxcx_cmd_out_t mlxo_create_eq_head; 1605 uint8_t mlxo_create_eq_rsvd[3]; 1606 uint8_t mlxo_create_eq_eqn; 1607 uint8_t mlxo_create_eq_rsvd2[4]; 1608 } mlxcx_cmd_create_eq_out_t; 1609 1610 typedef struct { 1611 mlxcx_cmd_in_t mlxi_query_eq_head; 1612 uint8_t mlxi_query_eq_rsvd[3]; 1613 uint8_t mlxi_query_eq_eqn; 1614 uint8_t mlxi_query_eq_rsvd2[4]; 1615 } mlxcx_cmd_query_eq_in_t; 1616 1617 typedef struct { 1618 mlxcx_cmd_out_t mlxo_query_eq_head; 1619 uint8_t mlxo_query_eq_rsvd[8]; 1620 mlxcx_eventq_ctx_t mlxo_query_eq_context; 1621 uint8_t mlxi_query_eq_rsvd2[8]; 1622 uint64be_t mlxi_query_eq_event_bitmask; 1623 uint8_t mlxi_query_eq_rsvd3[176]; 1624 uint64be_t mlxi_create_eq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1625 } mlxcx_cmd_query_eq_out_t; 1626 1627 typedef struct { 1628 mlxcx_cmd_in_t mlxi_destroy_eq_head; 1629 uint8_t mlxi_destroy_eq_rsvd[3]; 1630 uint8_t mlxi_destroy_eq_eqn; 1631 uint8_t mlxi_destroy_eq_rsvd2[4]; 1632 } mlxcx_cmd_destroy_eq_in_t; 1633 1634 typedef struct { 1635 mlxcx_cmd_out_t mlxo_destroy_eq_head; 1636 uint8_t mlxo_destroy_eq_rsvd[8]; 1637 } mlxcx_cmd_destroy_eq_out_t; 1638 1639 typedef struct { 1640 mlxcx_cmd_in_t mlxi_alloc_pd_head; 1641 uint8_t mlxi_alloc_pd_rsvd[8]; 1642 } mlxcx_cmd_alloc_pd_in_t; 1643 1644 typedef struct { 1645 mlxcx_cmd_out_t mlxo_alloc_pd_head; 1646 uint8_t mlxo_alloc_pd_rsvd; 1647 uint24be_t mlxo_alloc_pd_pdn; 1648 uint8_t mlxo_alloc_pd_rsvd2[4]; 1649 } mlxcx_cmd_alloc_pd_out_t; 1650 1651 typedef struct { 1652 mlxcx_cmd_in_t mlxi_dealloc_pd_head; 1653 uint8_t mlxi_dealloc_pd_rsvd; 1654 uint24be_t mlxi_dealloc_pd_pdn; 1655 uint8_t mlxi_dealloc_pd_rsvd2[4]; 1656 } mlxcx_cmd_dealloc_pd_in_t; 1657 1658 typedef struct { 1659 mlxcx_cmd_out_t mlxo_dealloc_pd_head; 1660 uint8_t mlxo_dealloc_pd_rsvd[8]; 1661 } mlxcx_cmd_dealloc_pd_out_t; 1662 1663 typedef struct { 1664 mlxcx_cmd_in_t mlxi_alloc_tdom_head; 1665 uint8_t mlxi_alloc_tdom_rsvd[8]; 1666 } mlxcx_cmd_alloc_tdom_in_t; 1667 1668 typedef struct { 1669 mlxcx_cmd_out_t mlxo_alloc_tdom_head; 1670 uint8_t mlxo_alloc_tdom_rsvd; 1671 uint24be_t mlxo_alloc_tdom_tdomn; 1672 uint8_t mlxo_alloc_tdom_rsvd2[4]; 1673 } mlxcx_cmd_alloc_tdom_out_t; 1674 1675 typedef struct { 1676 mlxcx_cmd_in_t mlxi_dealloc_tdom_head; 1677 uint8_t mlxi_dealloc_tdom_rsvd; 1678 uint24be_t mlxi_dealloc_tdom_tdomn; 1679 uint8_t mlxi_dealloc_tdom_rsvd2[4]; 1680 } mlxcx_cmd_dealloc_tdom_in_t; 1681 1682 typedef struct { 1683 mlxcx_cmd_out_t mlxo_dealloc_tdom_head; 1684 uint8_t mlxo_dealloc_tdom_rsvd[8]; 1685 } mlxcx_cmd_dealloc_tdom_out_t; 1686 1687 typedef struct { 1688 mlxcx_cmd_in_t mlxi_create_tir_head; 1689 uint8_t mlxi_create_tir_rsvd[24]; 1690 mlxcx_tir_ctx_t mlxi_create_tir_context; 1691 } mlxcx_cmd_create_tir_in_t; 1692 1693 typedef struct { 1694 mlxcx_cmd_out_t mlxo_create_tir_head; 1695 uint8_t mlxo_create_tir_rsvd; 1696 uint24be_t mlxo_create_tir_tirn; 1697 uint8_t mlxo_create_tir_rsvd2[4]; 1698 } mlxcx_cmd_create_tir_out_t; 1699 1700 typedef struct { 1701 mlxcx_cmd_in_t mlxi_destroy_tir_head; 1702 uint8_t mlxi_destroy_tir_rsvd; 1703 uint24be_t mlxi_destroy_tir_tirn; 1704 uint8_t mlxi_destroy_tir_rsvd2[4]; 1705 } mlxcx_cmd_destroy_tir_in_t; 1706 1707 typedef struct { 1708 mlxcx_cmd_out_t mlxo_destroy_tir_head; 1709 uint8_t mlxo_destroy_tir_rsvd[8]; 1710 } mlxcx_cmd_destroy_tir_out_t; 1711 1712 typedef struct { 1713 mlxcx_cmd_in_t mlxi_create_tis_head; 1714 uint8_t mlxi_create_tis_rsvd[24]; 1715 mlxcx_tis_ctx_t mlxi_create_tis_context; 1716 } mlxcx_cmd_create_tis_in_t; 1717 1718 typedef struct { 1719 mlxcx_cmd_out_t mlxo_create_tis_head; 1720 uint8_t mlxo_create_tis_rsvd; 1721 uint24be_t mlxo_create_tis_tisn; 1722 uint8_t mlxo_create_tis_rsvd2[4]; 1723 } mlxcx_cmd_create_tis_out_t; 1724 1725 typedef struct { 1726 mlxcx_cmd_in_t mlxi_destroy_tis_head; 1727 uint8_t mlxi_destroy_tis_rsvd; 1728 uint24be_t mlxi_destroy_tis_tisn; 1729 uint8_t mlxi_destroy_tis_rsvd2[4]; 1730 } mlxcx_cmd_destroy_tis_in_t; 1731 1732 typedef struct { 1733 mlxcx_cmd_out_t mlxo_destroy_tis_head; 1734 uint8_t mlxo_destroy_tis_rsvd[8]; 1735 } mlxcx_cmd_destroy_tis_out_t; 1736 1737 typedef struct { 1738 mlxcx_cmd_in_t mlxi_query_special_ctxs_head; 1739 uint8_t mlxi_query_special_ctxs_rsvd[8]; 1740 } mlxcx_cmd_query_special_ctxs_in_t; 1741 1742 typedef struct { 1743 mlxcx_cmd_out_t mlxo_query_special_ctxs_head; 1744 uint8_t mlxo_query_special_ctxs_rsvd[4]; 1745 uint32be_t mlxo_query_special_ctxs_resd_lkey; 1746 uint32be_t mlxo_query_special_ctxs_null_mkey; 1747 uint8_t mlxo_query_special_ctxs_rsvd2[12]; 1748 } mlxcx_cmd_query_special_ctxs_out_t; 1749 1750 typedef enum { 1751 MLXCX_VPORT_TYPE_VNIC = 0x0, 1752 MLXCX_VPORT_TYPE_ESWITCH = 0x1, 1753 MLXCX_VPORT_TYPE_UPLINK = 0x2, 1754 } mlxcx_cmd_vport_op_mod_t; 1755 1756 typedef struct { 1757 mlxcx_cmd_in_t mlxi_query_nic_vport_ctx_head; 1758 uint8_t mlxi_query_nic_vport_ctx_other_vport; 1759 uint8_t mlxi_query_nic_vport_ctx_rsvd[1]; 1760 uint16be_t mlxi_query_nic_vport_ctx_vport_number; 1761 uint8_t mlxi_query_nic_vport_ctx_allowed_list_type; 1762 uint8_t mlxi_query_nic_vport_ctx_rsvd2[3]; 1763 } mlxcx_cmd_query_nic_vport_ctx_in_t; 1764 1765 typedef struct { 1766 mlxcx_cmd_out_t mlxo_query_nic_vport_ctx_head; 1767 uint8_t mlxo_query_nic_vport_ctx_rsvd[8]; 1768 mlxcx_nic_vport_ctx_t mlxo_query_nic_vport_ctx_context; 1769 } mlxcx_cmd_query_nic_vport_ctx_out_t; 1770 1771 typedef enum { 1772 MLXCX_MODIFY_NIC_VPORT_CTX_ROCE_EN = 1 << 1, 1773 MLXCX_MODIFY_NIC_VPORT_CTX_ADDR_LIST = 1 << 2, 1774 MLXCX_MODIFY_NIC_VPORT_CTX_PERM_ADDR = 1 << 3, 1775 MLXCX_MODIFY_NIC_VPORT_CTX_PROMISC = 1 << 4, 1776 MLXCX_MODIFY_NIC_VPORT_CTX_EVENT = 1 << 5, 1777 MLXCX_MODIFY_NIC_VPORT_CTX_MTU = 1 << 6, 1778 MLXCX_MODIFY_NIC_VPORT_CTX_WQE_INLINE = 1 << 7, 1779 MLXCX_MODIFY_NIC_VPORT_CTX_PORT_GUID = 1 << 8, 1780 MLXCX_MODIFY_NIC_VPORT_CTX_NODE_GUID = 1 << 9, 1781 } mlxcx_modify_nic_vport_ctx_fields_t; 1782 1783 typedef struct { 1784 mlxcx_cmd_in_t mlxi_modify_nic_vport_ctx_head; 1785 uint8_t mlxi_modify_nic_vport_ctx_other_vport; 1786 uint8_t mlxi_modify_nic_vport_ctx_rsvd[1]; 1787 uint16be_t mlxi_modify_nic_vport_ctx_vport_number; 1788 uint32be_t mlxi_modify_nic_vport_ctx_field_select; 1789 uint8_t mlxi_modify_nic_vport_ctx_rsvd2[240]; 1790 mlxcx_nic_vport_ctx_t mlxi_modify_nic_vport_ctx_context; 1791 } mlxcx_cmd_modify_nic_vport_ctx_in_t; 1792 1793 typedef struct { 1794 mlxcx_cmd_out_t mlxo_modify_nic_vport_ctx_head; 1795 uint8_t mlxo_modify_nic_vport_ctx_rsvd[8]; 1796 } mlxcx_cmd_modify_nic_vport_ctx_out_t; 1797 1798 typedef struct { 1799 mlxcx_cmd_in_t mlxi_query_vport_state_head; 1800 uint8_t mlxi_query_vport_state_other_vport; 1801 uint8_t mlxi_query_vport_state_rsvd[1]; 1802 uint16be_t mlxi_query_vport_state_vport_number; 1803 uint8_t mlxi_query_vport_state_rsvd2[4]; 1804 } mlxcx_cmd_query_vport_state_in_t; 1805 1806 /* CSTYLED */ 1807 #define MLXCX_VPORT_ADMIN_STATE (bitdef_t){4, 0xF0} 1808 /* CSTYLED */ 1809 #define MLXCX_VPORT_OPER_STATE (bitdef_t){0, 0x0F} 1810 1811 typedef enum { 1812 MLXCX_VPORT_OPER_STATE_DOWN = 0x0, 1813 MLXCX_VPORT_OPER_STATE_UP = 0x1, 1814 } mlxcx_vport_oper_state_t; 1815 1816 typedef enum { 1817 MLXCX_VPORT_ADMIN_STATE_DOWN = 0x0, 1818 MLXCX_VPORT_ADMIN_STATE_UP = 0x1, 1819 MLXCX_VPORT_ADMIN_STATE_FOLLOW = 0x2, 1820 } mlxcx_vport_admin_state_t; 1821 1822 typedef struct { 1823 mlxcx_cmd_out_t mlxo_query_vport_state_head; 1824 uint8_t mlxo_query_vport_state_rsvd[4]; 1825 uint16be_t mlxo_query_vport_state_max_tx_speed; 1826 uint8_t mlxo_query_vport_state_rsvd2[1]; 1827 uint8_t mlxo_query_vport_state_state; 1828 } mlxcx_cmd_query_vport_state_out_t; 1829 1830 typedef struct { 1831 mlxcx_cmd_in_t mlxi_create_cq_head; 1832 uint8_t mlxi_create_cq_rsvd[8]; 1833 mlxcx_completionq_ctx_t mlxi_create_cq_context; 1834 uint8_t mlxi_create_cq_rsvd2[192]; 1835 uint64be_t mlxi_create_cq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1836 } mlxcx_cmd_create_cq_in_t; 1837 1838 typedef struct { 1839 mlxcx_cmd_out_t mlxo_create_cq_head; 1840 uint8_t mlxo_create_cq_rsvd; 1841 uint24be_t mlxo_create_cq_cqn; 1842 uint8_t mlxo_create_cq_rsvd2[4]; 1843 } mlxcx_cmd_create_cq_out_t; 1844 1845 typedef struct { 1846 mlxcx_cmd_in_t mlxi_destroy_cq_head; 1847 uint8_t mlxi_destroy_cq_rsvd; 1848 uint24be_t mlxi_destroy_cq_cqn; 1849 uint8_t mlxi_destroy_cq_rsvd2[4]; 1850 } mlxcx_cmd_destroy_cq_in_t; 1851 1852 typedef struct { 1853 mlxcx_cmd_out_t mlxo_destroy_cq_head; 1854 uint8_t mlxo_destroy_cq_rsvd[8]; 1855 } mlxcx_cmd_destroy_cq_out_t; 1856 1857 typedef struct { 1858 mlxcx_cmd_in_t mlxi_query_cq_head; 1859 uint8_t mlxi_query_cq_rsvd; 1860 uint24be_t mlxi_query_cq_cqn; 1861 uint8_t mlxi_query_cq_rsvd2[4]; 1862 } mlxcx_cmd_query_cq_in_t; 1863 1864 typedef struct { 1865 mlxcx_cmd_out_t mlxo_query_cq_head; 1866 uint8_t mlxo_query_cq_rsvd[8]; 1867 mlxcx_completionq_ctx_t mlxo_query_cq_context; 1868 uint8_t mlxo_query_cq_rsvd2[192]; 1869 uint64be_t mlxo_query_cq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1870 } mlxcx_cmd_query_cq_out_t; 1871 1872 typedef struct { 1873 mlxcx_cmd_in_t mlxi_create_rq_head; 1874 uint8_t mlxi_create_rq_rsvd[24]; 1875 mlxcx_rq_ctx_t mlxi_create_rq_context; 1876 } mlxcx_cmd_create_rq_in_t; 1877 1878 typedef struct { 1879 mlxcx_cmd_out_t mlxo_create_rq_head; 1880 uint8_t mlxo_create_rq_rsvd; 1881 uint24be_t mlxo_create_rq_rqn; 1882 uint8_t mlxo_create_rq_rsvd2[4]; 1883 } mlxcx_cmd_create_rq_out_t; 1884 1885 /* CSTYLED */ 1886 #define MLXCX_CMD_MODIFY_RQ_STATE (bitdef_t){ \ 1887 .bit_shift = 4, .bit_mask = 0xF0 } 1888 1889 typedef enum { 1890 MLXCX_MODIFY_RQ_SCATTER_FCS = 1 << 2, 1891 MLXCX_MODIFY_RQ_VSD = 1 << 1, 1892 MLXCX_MODIFY_RQ_COUNTER_SET_ID = 1 << 3, 1893 MLXCX_MODIFY_RQ_LWM = 1 << 0 1894 } mlxcx_cmd_modify_rq_bitmask_t; 1895 1896 typedef enum { 1897 MLXCX_RQ_STATE_RST = 0x0, 1898 MLXCX_RQ_STATE_RDY = 0x1, 1899 MLXCX_RQ_STATE_ERR = 0x3 1900 } mlxcx_rq_state_t; 1901 1902 typedef struct { 1903 mlxcx_cmd_in_t mlxi_modify_rq_head; 1904 bits8_t mlxi_modify_rq_state; 1905 uint24be_t mlxi_modify_rq_rqn; 1906 uint8_t mlxi_modify_rq_rsvd[4]; 1907 uint64be_t mlxi_modify_rq_bitmask; 1908 uint8_t mlxi_modify_rq_rsvd2[8]; 1909 mlxcx_rq_ctx_t mlxi_modify_rq_context; 1910 } mlxcx_cmd_modify_rq_in_t; 1911 1912 typedef struct { 1913 mlxcx_cmd_out_t mlxo_modify_rq_head; 1914 uint8_t mlxo_modify_rq_rsvd[8]; 1915 } mlxcx_cmd_modify_rq_out_t; 1916 1917 typedef struct { 1918 mlxcx_cmd_in_t mlxi_query_rq_head; 1919 uint8_t mlxi_query_rq_rsvd; 1920 uint24be_t mlxi_query_rq_rqn; 1921 uint8_t mlxi_query_rq_rsvd2[4]; 1922 } mlxcx_cmd_query_rq_in_t; 1923 1924 typedef struct { 1925 mlxcx_cmd_out_t mlxo_query_rq_head; 1926 uint8_t mlxo_query_rq_rsvd[24]; 1927 mlxcx_rq_ctx_t mlxo_query_rq_context; 1928 } mlxcx_cmd_query_rq_out_t; 1929 1930 typedef struct { 1931 mlxcx_cmd_in_t mlxi_destroy_rq_head; 1932 uint8_t mlxi_destroy_rq_rsvd; 1933 uint24be_t mlxi_destroy_rq_rqn; 1934 uint8_t mlxi_destroy_rq_rsvd2[4]; 1935 } mlxcx_cmd_destroy_rq_in_t; 1936 1937 typedef struct { 1938 mlxcx_cmd_out_t mlxo_destroy_rq_head; 1939 uint8_t mlxo_destroy_rq_rsvd[8]; 1940 } mlxcx_cmd_destroy_rq_out_t; 1941 1942 typedef struct { 1943 mlxcx_cmd_in_t mlxi_create_sq_head; 1944 uint8_t mlxi_create_sq_rsvd[24]; 1945 mlxcx_sq_ctx_t mlxi_create_sq_context; 1946 } mlxcx_cmd_create_sq_in_t; 1947 1948 typedef struct { 1949 mlxcx_cmd_out_t mlxo_create_sq_head; 1950 uint8_t mlxo_create_sq_rsvd; 1951 uint24be_t mlxo_create_sq_sqn; 1952 uint8_t mlxo_create_sq_rsvd2[4]; 1953 } mlxcx_cmd_create_sq_out_t; 1954 1955 /* CSTYLED */ 1956 #define MLXCX_CMD_MODIFY_SQ_STATE (bitdef_t){ \ 1957 .bit_shift = 4, .bit_mask = 0xF0 } 1958 1959 typedef enum { 1960 MLXCX_MODIFY_SQ_PACKET_PACING_INDEX = 1 << 0, 1961 } mlxcx_cmd_modify_sq_bitmask_t; 1962 1963 typedef enum { 1964 MLXCX_SQ_STATE_RST = 0x0, 1965 MLXCX_SQ_STATE_RDY = 0x1, 1966 MLXCX_SQ_STATE_ERR = 0x3 1967 } mlxcx_sq_state_t; 1968 1969 typedef struct { 1970 mlxcx_cmd_in_t mlxi_modify_sq_head; 1971 bits8_t mlxi_modify_sq_state; 1972 uint24be_t mlxi_modify_sq_sqn; 1973 uint8_t mlxi_modify_sq_rsvd[4]; 1974 uint64be_t mlxi_modify_sq_bitmask; 1975 uint8_t mlxi_modify_sq_rsvd2[8]; 1976 mlxcx_sq_ctx_t mlxi_modify_sq_context; 1977 } mlxcx_cmd_modify_sq_in_t; 1978 1979 typedef struct { 1980 mlxcx_cmd_out_t mlxo_modify_sq_head; 1981 uint8_t mlxo_modify_sq_rsvd[8]; 1982 } mlxcx_cmd_modify_sq_out_t; 1983 1984 typedef struct { 1985 mlxcx_cmd_in_t mlxi_query_sq_head; 1986 uint8_t mlxi_query_sq_rsvd; 1987 uint24be_t mlxi_query_sq_sqn; 1988 uint8_t mlxi_query_sq_rsvd2[4]; 1989 } mlxcx_cmd_query_sq_in_t; 1990 1991 typedef struct { 1992 mlxcx_cmd_out_t mlxo_query_sq_head; 1993 uint8_t mlxo_query_sq_rsvd[24]; 1994 mlxcx_sq_ctx_t mlxo_query_sq_context; 1995 } mlxcx_cmd_query_sq_out_t; 1996 1997 typedef struct { 1998 mlxcx_cmd_in_t mlxi_destroy_sq_head; 1999 uint8_t mlxi_destroy_sq_rsvd; 2000 uint24be_t mlxi_destroy_sq_sqn; 2001 uint8_t mlxi_destroy_sq_rsvd2[4]; 2002 } mlxcx_cmd_destroy_sq_in_t; 2003 2004 typedef struct { 2005 mlxcx_cmd_out_t mlxo_destroy_sq_head; 2006 uint8_t mlxo_destroy_sq_rsvd[8]; 2007 } mlxcx_cmd_destroy_sq_out_t; 2008 2009 typedef struct { 2010 mlxcx_cmd_in_t mlxi_create_rqt_head; 2011 uint8_t mlxi_create_rqt_rsvd[24]; 2012 mlxcx_rqtable_ctx_t mlxi_create_rqt_context; 2013 } mlxcx_cmd_create_rqt_in_t; 2014 2015 typedef struct { 2016 mlxcx_cmd_out_t mlxo_create_rqt_head; 2017 uint8_t mlxo_create_rqt_rsvd; 2018 uint24be_t mlxo_create_rqt_rqtn; 2019 uint8_t mlxo_create_rqt_rsvd2[4]; 2020 } mlxcx_cmd_create_rqt_out_t; 2021 2022 typedef struct { 2023 mlxcx_cmd_in_t mlxi_destroy_rqt_head; 2024 uint8_t mlxi_destroy_rqt_rsvd; 2025 uint24be_t mlxi_destroy_rqt_rqtn; 2026 uint8_t mlxi_destroy_rqt_rsvd2[4]; 2027 } mlxcx_cmd_destroy_rqt_in_t; 2028 2029 typedef struct { 2030 mlxcx_cmd_out_t mlxo_destroy_rqt_head; 2031 uint8_t mlxo_destroy_rqt_rsvd[8]; 2032 } mlxcx_cmd_destroy_rqt_out_t; 2033 2034 typedef enum { 2035 MLXCX_FLOW_TABLE_NIC_RX = 0x0, 2036 MLXCX_FLOW_TABLE_NIC_TX = 0x1, 2037 MLXCX_FLOW_TABLE_ESW_OUT = 0x2, 2038 MLXCX_FLOW_TABLE_ESW_IN = 0x3, 2039 MLXCX_FLOW_TABLE_ESW_FDB = 0x4, 2040 MLXCX_FLOW_TABLE_NIC_RX_SNIFF = 0x5, 2041 MLXCX_FLOW_TABLE_NIC_TX_SNIFF = 0x6, 2042 MLXCX_FLOW_TABLE_NIC_RX_RDMA = 0x7, 2043 MLXCX_FLOW_TABLE_NIC_TX_RDMA = 0x8 2044 } mlxcx_flow_table_type_t; 2045 2046 typedef struct { 2047 mlxcx_cmd_in_t mlxi_create_flow_table_head; 2048 uint8_t mlxi_create_flow_table_other_vport; 2049 uint8_t mlxi_create_flow_table_rsvd; 2050 uint16be_t mlxi_create_flow_table_vport_number; 2051 uint8_t mlxi_create_flow_table_rsvd2[4]; 2052 uint8_t mlxi_create_flow_table_table_type; 2053 uint8_t mlxi_create_flow_table_rsvd3[7]; 2054 mlxcx_flow_table_ctx_t mlxi_create_flow_table_context; 2055 } mlxcx_cmd_create_flow_table_in_t; 2056 2057 typedef struct { 2058 mlxcx_cmd_out_t mlxo_create_flow_table_head; 2059 uint8_t mlxo_create_flow_table_rsvd; 2060 uint24be_t mlxo_create_flow_table_table_id; 2061 uint8_t mlxo_create_flow_table_rsvd2[4]; 2062 } mlxcx_cmd_create_flow_table_out_t; 2063 2064 typedef struct { 2065 mlxcx_cmd_in_t mlxi_destroy_flow_table_head; 2066 uint8_t mlxi_destroy_flow_table_other_vport; 2067 uint8_t mlxi_destroy_flow_table_rsvd; 2068 uint16be_t mlxi_destroy_flow_table_vport_number; 2069 uint8_t mlxi_destroy_flow_table_rsvd2[4]; 2070 uint8_t mlxi_destroy_flow_table_table_type; 2071 uint8_t mlxi_destroy_flow_table_rsvd3[4]; 2072 uint24be_t mlxi_destroy_flow_table_table_id; 2073 uint8_t mlxi_destroy_flow_table_rsvd4[4]; 2074 } mlxcx_cmd_destroy_flow_table_in_t; 2075 2076 typedef struct { 2077 mlxcx_cmd_out_t mlxo_destroy_flow_table_head; 2078 uint8_t mlxo_destroy_flow_table_rsvd[8]; 2079 } mlxcx_cmd_destroy_flow_table_out_t; 2080 2081 typedef struct { 2082 mlxcx_cmd_in_t mlxi_set_flow_table_root_head; 2083 uint8_t mlxi_set_flow_table_root_other_vport; 2084 uint8_t mlxi_set_flow_table_root_rsvd; 2085 uint16be_t mlxi_set_flow_table_root_vport_number; 2086 uint8_t mlxi_set_flow_table_root_rsvd2[4]; 2087 uint8_t mlxi_set_flow_table_root_table_type; 2088 uint8_t mlxi_set_flow_table_root_rsvd3[4]; 2089 uint24be_t mlxi_set_flow_table_root_table_id; 2090 uint8_t mlxi_set_flow_table_root_rsvd4[4]; 2091 uint8_t mlxi_set_flow_table_root_esw_owner_vhca_id_valid; 2092 uint8_t mlxi_set_flow_table_root_rsvd5; 2093 uint16be_t mlxi_set_flow_table_root_esw_owner_vhca_id; 2094 uint8_t mlxi_set_flow_table_root_rsvd6[32]; 2095 } mlxcx_cmd_set_flow_table_root_in_t; 2096 2097 typedef struct { 2098 mlxcx_cmd_out_t mlxo_set_flow_table_root_head; 2099 uint8_t mlxo_set_flow_table_root_rsvd[8]; 2100 } mlxcx_cmd_set_flow_table_root_out_t; 2101 2102 typedef enum { 2103 MLXCX_FLOW_GROUP_MATCH_OUTER_HDRS = 1 << 0, 2104 MLXCX_FLOW_GROUP_MATCH_MISC_PARAMS = 1 << 1, 2105 MLXCX_FLOW_GROUP_MATCH_INNER_HDRS = 1 << 2, 2106 } mlxcx_flow_group_match_criteria_t; 2107 2108 typedef struct { 2109 mlxcx_cmd_in_t mlxi_create_flow_group_head; 2110 uint8_t mlxi_create_flow_group_other_vport; 2111 uint8_t mlxi_create_flow_group_rsvd; 2112 uint16be_t mlxi_create_flow_group_vport_number; 2113 uint8_t mlxi_create_flow_group_rsvd2[4]; 2114 uint8_t mlxi_create_flow_group_table_type; 2115 uint8_t mlxi_create_flow_group_rsvd3[4]; 2116 uint24be_t mlxi_create_flow_group_table_id; 2117 uint8_t mlxi_create_flow_group_rsvd4[4]; 2118 uint32be_t mlxi_create_flow_group_start_flow_index; 2119 uint8_t mlxi_create_flow_group_rsvd5[4]; 2120 uint32be_t mlxi_create_flow_group_end_flow_index; 2121 uint8_t mlxi_create_flow_group_rsvd6[23]; 2122 uint8_t mlxi_create_flow_group_match_criteria_en; 2123 mlxcx_flow_match_t mlxi_create_flow_group_match_criteria; 2124 uint8_t mlxi_create_flow_group_rsvd7[448]; 2125 } mlxcx_cmd_create_flow_group_in_t; 2126 2127 typedef struct { 2128 mlxcx_cmd_out_t mlxo_create_flow_group_head; 2129 uint8_t mlxo_create_flow_group_rsvd; 2130 uint24be_t mlxo_create_flow_group_group_id; 2131 uint8_t mlxo_create_flow_group_rsvd2[4]; 2132 } mlxcx_cmd_create_flow_group_out_t; 2133 2134 typedef struct { 2135 mlxcx_cmd_in_t mlxi_destroy_flow_group_head; 2136 uint8_t mlxi_destroy_flow_group_other_vport; 2137 uint8_t mlxi_destroy_flow_group_rsvd; 2138 uint16be_t mlxi_destroy_flow_group_vport_number; 2139 uint8_t mlxi_destroy_flow_group_rsvd2[4]; 2140 uint8_t mlxi_destroy_flow_group_table_type; 2141 uint8_t mlxi_destroy_flow_group_rsvd3[4]; 2142 uint24be_t mlxi_destroy_flow_group_table_id; 2143 uint32be_t mlxi_destroy_flow_group_group_id; 2144 uint8_t mlxi_destroy_flow_group_rsvd4[36]; 2145 } mlxcx_cmd_destroy_flow_group_in_t; 2146 2147 typedef struct { 2148 mlxcx_cmd_out_t mlxo_destroy_flow_group_head; 2149 uint8_t mlxo_destroy_flow_group_rsvd[8]; 2150 } mlxcx_cmd_destroy_flow_group_out_t; 2151 2152 typedef enum { 2153 MLXCX_CMD_FLOW_ENTRY_SET_NEW = 0, 2154 MLXCX_CMD_FLOW_ENTRY_MODIFY = 1, 2155 } mlxcx_cmd_set_flow_table_entry_opmod_t; 2156 2157 typedef enum { 2158 MLXCX_CMD_FLOW_ENTRY_SET_ACTION = 1 << 0, 2159 MLXCX_CMD_FLOW_ENTRY_SET_FLOW_TAG = 1 << 1, 2160 MLXCX_CMD_FLOW_ENTRY_SET_DESTINATION = 1 << 2, 2161 MLXCX_CMD_FLOW_ENTRY_SET_COUNTERS = 1 << 3, 2162 MLXCX_CMD_FLOW_ENTRY_SET_ENCAP = 1 << 4 2163 } mlxcx_cmd_set_flow_table_entry_bitmask_t; 2164 2165 typedef struct { 2166 mlxcx_cmd_in_t mlxi_set_flow_table_entry_head; 2167 uint8_t mlxi_set_flow_table_entry_other_vport; 2168 uint8_t mlxi_set_flow_table_entry_rsvd; 2169 uint16be_t mlxi_set_flow_table_entry_vport_number; 2170 uint8_t mlxi_set_flow_table_entry_rsvd2[4]; 2171 uint8_t mlxi_set_flow_table_entry_table_type; 2172 uint8_t mlxi_set_flow_table_entry_rsvd3[4]; 2173 uint24be_t mlxi_set_flow_table_entry_table_id; 2174 uint8_t mlxi_set_flow_table_entry_rsvd4[3]; 2175 bits8_t mlxi_set_flow_table_entry_modify_bitmask; 2176 uint8_t mlxi_set_flow_table_entry_rsvd5[4]; 2177 uint32be_t mlxi_set_flow_table_entry_flow_index; 2178 uint8_t mlxi_set_flow_table_entry_rsvd6[28]; 2179 mlxcx_flow_entry_ctx_t mlxi_set_flow_table_entry_context; 2180 } mlxcx_cmd_set_flow_table_entry_in_t; 2181 2182 typedef struct { 2183 mlxcx_cmd_out_t mlxo_set_flow_table_entry_head; 2184 uint8_t mlxo_set_flow_table_entry_rsvd[8]; 2185 } mlxcx_cmd_set_flow_table_entry_out_t; 2186 2187 typedef struct { 2188 mlxcx_cmd_in_t mlxi_delete_flow_table_entry_head; 2189 uint8_t mlxi_delete_flow_table_entry_other_vport; 2190 uint8_t mlxi_delete_flow_table_entry_rsvd; 2191 uint16be_t mlxi_delete_flow_table_entry_vport_number; 2192 uint8_t mlxi_delete_flow_table_entry_rsvd2[4]; 2193 uint8_t mlxi_delete_flow_table_entry_table_type; 2194 uint8_t mlxi_delete_flow_table_entry_rsvd3[4]; 2195 uint24be_t mlxi_delete_flow_table_entry_table_id; 2196 uint8_t mlxi_delete_flow_table_entry_rsvd4[8]; 2197 uint32be_t mlxi_delete_flow_table_entry_flow_index; 2198 uint8_t mlxi_delete_flow_table_entry_rsvd5[28]; 2199 } mlxcx_cmd_delete_flow_table_entry_in_t; 2200 2201 typedef struct { 2202 mlxcx_cmd_out_t mlxo_delete_flow_table_entry_head; 2203 uint8_t mlxo_delete_flow_table_entry_rsvd[8]; 2204 } mlxcx_cmd_delete_flow_table_entry_out_t; 2205 2206 typedef enum { 2207 MLXCX_CMD_CONFIG_INT_MOD_READ = 1, 2208 MLXCX_CMD_CONFIG_INT_MOD_WRITE = 0 2209 } mlxcx_cmd_config_int_mod_opmod_t; 2210 2211 typedef struct { 2212 mlxcx_cmd_in_t mlxi_config_int_mod_head; 2213 uint16be_t mlxi_config_int_mod_min_delay; 2214 uint16be_t mlxi_config_int_mod_int_vector; 2215 uint8_t mlxi_config_int_mod_rsvd[4]; 2216 } mlxcx_cmd_config_int_mod_in_t; 2217 2218 typedef struct { 2219 mlxcx_cmd_out_t mlxo_config_int_mod_head; 2220 uint16be_t mlxo_config_int_mod_min_delay; 2221 uint16be_t mlxo_config_int_mod_int_vector; 2222 uint8_t mlxo_config_int_mod_rsvd[4]; 2223 } mlxcx_cmd_config_int_mod_out_t; 2224 2225 typedef struct { 2226 uint8_t mlrd_pmtu_rsvd; 2227 uint8_t mlrd_pmtu_local_port; 2228 uint8_t mlrd_pmtu_rsvd2[2]; 2229 2230 uint16be_t mlrd_pmtu_max_mtu; 2231 uint8_t mlrd_pmtu_rsvd3[2]; 2232 2233 uint16be_t mlrd_pmtu_admin_mtu; 2234 uint8_t mlrd_pmtu_rsvd4[2]; 2235 2236 uint16be_t mlrd_pmtu_oper_mtu; 2237 uint8_t mlrd_pmtu_rsvd5[2]; 2238 } mlxcx_reg_pmtu_t; 2239 2240 typedef enum { 2241 MLXCX_PORT_STATUS_UP = 1, 2242 MLXCX_PORT_STATUS_DOWN = 2, 2243 MLXCX_PORT_STATUS_UP_ONCE = 3, 2244 MLXCX_PORT_STATUS_DISABLED = 4, 2245 } mlxcx_port_status_t; 2246 2247 typedef enum { 2248 MLXCX_PAOS_ADMIN_ST_EN = 1UL << 31, 2249 } mlxcx_paos_flags_t; 2250 2251 typedef struct { 2252 uint8_t mlrd_paos_swid; 2253 uint8_t mlrd_paos_local_port; 2254 uint8_t mlrd_paos_admin_status; 2255 uint8_t mlrd_paos_oper_status; 2256 bits32_t mlrd_paos_flags; 2257 uint8_t mlrd_paos_rsvd[8]; 2258 } mlxcx_reg_paos_t; 2259 2260 typedef enum { 2261 MLXCX_PROTO_NONE = 0, 2262 MLXCX_PROTO_SGMII = 1 << 0, 2263 MLXCX_PROTO_1000BASE_KX = 1 << 1, 2264 MLXCX_PROTO_10GBASE_CX4 = 1 << 2, 2265 MLXCX_PROTO_10GBASE_KX4 = 1 << 3, 2266 MLXCX_PROTO_10GBASE_KR = 1 << 4, 2267 MLXCX_PROTO_UNKNOWN_1 = 1 << 5, 2268 MLXCX_PROTO_40GBASE_CR4 = 1 << 6, 2269 MLXCX_PROTO_40GBASE_KR4 = 1 << 7, 2270 MLXCX_PROTO_UNKNOWN_2 = 1 << 8, 2271 MLXCX_PROTO_SGMII_100BASE = 1 << 9, 2272 MLXCX_PROTO_UNKNOWN_3 = 1 << 10, 2273 MLXCX_PROTO_UNKNOWN_4 = 1 << 11, 2274 MLXCX_PROTO_10GBASE_CR = 1 << 12, 2275 MLXCX_PROTO_10GBASE_SR = 1 << 13, 2276 MLXCX_PROTO_10GBASE_ER_LR = 1 << 14, 2277 MLXCX_PROTO_40GBASE_SR4 = 1 << 15, 2278 MLXCX_PROTO_40GBASE_LR4_ER4 = 1 << 16, 2279 MLXCX_PROTO_UNKNOWN_5 = 1 << 17, 2280 MLXCX_PROTO_50GBASE_SR2 = 1 << 18, 2281 MLXCX_PROTO_UNKNOWN_6 = 1 << 19, 2282 MLXCX_PROTO_100GBASE_CR4 = 1 << 20, 2283 MLXCX_PROTO_100GBASE_SR4 = 1 << 21, 2284 MLXCX_PROTO_100GBASE_KR4 = 1 << 22, 2285 MLXCX_PROTO_100GBASE_LR4_ER4 = 1 << 23, 2286 MLXCX_PROTO_100BASE_TX = 1 << 24, 2287 MLXCX_PROTO_1000BASE_T = 1 << 25, 2288 MLXCX_PROTO_10GBASE_T = 1 << 26, 2289 MLXCX_PROTO_25GBASE_CR = 1 << 27, 2290 MLXCX_PROTO_25GBASE_KR = 1 << 28, 2291 MLXCX_PROTO_25GBASE_SR = 1 << 29, 2292 MLXCX_PROTO_50GBASE_CR2 = 1 << 30, 2293 MLXCX_PROTO_50GBASE_KR2 = 1UL << 31, 2294 } mlxcx_eth_proto_t; 2295 2296 /* Extended proto values introduced with ConnectX-6. */ 2297 typedef enum { 2298 MLXCX_EXTPROTO_NONE = 0, 2299 MLXCX_EXTPROTO_SGMII_100BASE = 1 << 0, 2300 MLXCX_EXTPROTO_1000BASE_X_SGMII = 1 << 1, 2301 /* 1 << 2 */ 2302 MLXCX_EXTPROTO_5GBASE_R = 1 << 3, 2303 MLXCX_EXTPROTO_10GBASE_XFI_XAUI_1 = 1 << 4, 2304 MLXCX_EXTPROTO_40GBASE_XLAUI_4_XLPPI_4 = 1 << 5, 2305 MLXCX_EXTPROTO_25GAUI_1_25GBASE_CR_KR = 1 << 6, 2306 MLXCX_EXTPROTO_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 = 1 << 7, 2307 MLXCX_EXTPROTO_50GAUI_1_LAUI_1_50GBASE_CR_KR = 1 << 8, 2308 MLXCX_EXTPROTO_CAUI_4_100GBASE_CR4_KR4 = 1 << 9, 2309 MLXCX_EXTPROTO_100GAUI_2_100GBASE_CR2_KR2 = 1 << 10, 2310 MLXCX_EXTPROTO_100GAUI_1_100GBASE_CR_KR = 1 << 11, 2311 MLXCX_EXTPROTO_200GAUI_4_200GBASE_CR4_KR4 = 1 << 12, 2312 MLXCX_EXTPROTO_200GAUI_2_200GBASE_CR2_KR2 = 1 << 13, 2313 /* 1 << 14 */ 2314 MLXCX_EXTPROTO_400GAUI_8_400GBASE_CR8 = 1 << 15, 2315 MLXCX_EXTPROTO_400GAUI_4_400GBASE_CR4 = 1 << 16, 2316 /* 1UL << [17-30] */ 2317 MLXCX_EXTPROTO_SGMII = 1UL << 31, 2318 } mlxcx_ext_eth_proto_t; 2319 2320 #define MLXCX_PROTO_100M (MLXCX_PROTO_SGMII_100BASE | \ 2321 MLXCX_PROTO_100BASE_TX) 2322 #define MLXCX_EXTPROTO_100M MLXCX_EXTPROTO_SGMII_100BASE 2323 2324 #define MLXCX_PROTO_1G (MLXCX_PROTO_1000BASE_KX | MLXCX_PROTO_SGMII | \ 2325 MLXCX_PROTO_1000BASE_T) 2326 #define MLXCX_EXTPROTO_1G (MLXCX_EXTPROTO_1000BASE_X_SGMII) 2327 2328 #define MLXCX_EXTPROTO_5G MLXCX_EXTPROTO_5GBASE_R 2329 2330 #define MLXCX_PROTO_10G (MLXCX_PROTO_10GBASE_CX4 | \ 2331 MLXCX_PROTO_10GBASE_KX4 | MLXCX_PROTO_10GBASE_KR | \ 2332 MLXCX_PROTO_10GBASE_CR | MLXCX_PROTO_10GBASE_SR | \ 2333 MLXCX_PROTO_10GBASE_ER_LR | MLXCX_PROTO_10GBASE_T) 2334 #define MLXCX_EXTPROTO_10G MLXCX_EXTPROTO_10GBASE_XFI_XAUI_1 2335 2336 #define MLXCX_PROTO_25G (MLXCX_PROTO_25GBASE_CR | \ 2337 MLXCX_PROTO_25GBASE_KR | MLXCX_PROTO_25GBASE_SR) 2338 #define MLXCX_EXTPROTO_25G MLXCX_EXTPROTO_25GAUI_1_25GBASE_CR_KR 2339 2340 #define MLXCX_PROTO_40G (MLXCX_PROTO_40GBASE_SR4 | \ 2341 MLXCX_PROTO_40GBASE_LR4_ER4 | MLXCX_PROTO_40GBASE_CR4 | \ 2342 MLXCX_PROTO_40GBASE_KR4) 2343 #define MLXCX_EXTPROTO_40G MLXCX_EXTPROTO_40GBASE_XLAUI_4_XLPPI_4 2344 2345 #define MLXCX_PROTO_50G (MLXCX_PROTO_50GBASE_CR2 | \ 2346 MLXCX_PROTO_50GBASE_KR2 | MLXCX_PROTO_50GBASE_SR2) 2347 #define MLXCX_EXTPROTO_50G (MLXCX_EXTPROTO_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 | \ 2348 MLXCX_EXTPROTO_50GAUI_1_LAUI_1_50GBASE_CR_KR) 2349 2350 #define MLXCX_PROTO_100G (MLXCX_PROTO_100GBASE_CR4 | \ 2351 MLXCX_PROTO_100GBASE_SR4 | MLXCX_PROTO_100GBASE_KR4 | \ 2352 MLXCX_PROTO_100GBASE_LR4_ER4) 2353 #define MLXCX_EXTPROTO_100G (MLXCX_EXTPROTO_CAUI_4_100GBASE_CR4_KR4 | \ 2354 MLXCX_EXTPROTO_100GAUI_2_100GBASE_CR2_KR2 | \ 2355 MLXCX_EXTPROTO_100GAUI_1_100GBASE_CR_KR) 2356 2357 /* 200G and higher only are in the extended protocol bits. */ 2358 #define MLXCX_EXTPROTO_200G (MLXCX_EXTPROTO_200GAUI_4_200GBASE_CR4_KR4 | \ 2359 MLXCX_EXTPROTO_200GAUI_2_200GBASE_CR2_KR2) 2360 2361 #define MLXCX_EXTPROTO_400G (MLXCX_EXTPROTO_400GAUI_8_400GBASE_CR8 | \ 2362 MLXCX_EXTPROTO_400GAUI_4_400GBASE_CR4) 2363 2364 2365 typedef enum { 2366 MLXCX_AUTONEG_DISABLE_CAP = 1 << 5, 2367 MLXCX_AUTONEG_DISABLE = 1 << 6 2368 } mlxcx_autoneg_flags_t; 2369 2370 typedef enum { 2371 MLXCX_PTYS_PROTO_MASK_IB = 1 << 0, 2372 MLXCX_PTYS_PROTO_MASK_ETH = 1 << 2, 2373 } mlxcx_reg_ptys_proto_mask_t; 2374 2375 typedef struct { 2376 bits8_t mlrd_ptys_autoneg_flags; 2377 uint8_t mlrd_ptys_local_port; 2378 uint8_t mlrd_ptys_rsvd; 2379 bits8_t mlrd_ptys_proto_mask; 2380 2381 bits8_t mlrd_ptys_autoneg_status; 2382 uint8_t mlrd_ptys_rsvd2; 2383 uint16be_t mlrd_ptys_data_rate_oper; 2384 2385 bits32_t mlrd_ptys_ext_proto_cap; 2386 bits32_t mlrd_ptys_proto_cap; 2387 uint8_t mlrd_ptys_rsvd4[4]; 2388 bits32_t mlrd_ptys_ext_proto_admin; 2389 bits32_t mlrd_ptys_proto_admin; 2390 uint8_t mlrd_ptys_rsvd5[4]; 2391 bits32_t mlrd_ptys_ext_proto_oper; 2392 bits32_t mlrd_ptys_proto_oper; 2393 uint8_t mlrd_ptys_rsvd6[8]; 2394 bits32_t mlrd_ptys_proto_partner_advert; 2395 uint8_t mlrd_ptys_rsvd7[12]; 2396 } mlxcx_reg_ptys_t; 2397 2398 typedef enum { 2399 MLXCX_PCAM_LOW_FFLAGS_PTYS_EXTENDED = (1 << 13), 2400 } mlxcx_pcam_low_feature_flags_t; 2401 2402 typedef struct { 2403 uint8_t mlrd_pcam_rsvd1; 2404 uint8_t mlrd_pcam_feature_group; 2405 uint8_t mlrd_pcam_rsvd2; 2406 uint8_t mlrd_pcam_access_reg_group; 2407 uint8_t mlrd_pcam_rsvd3[4]; 2408 bits64_t mlrd_pcam_port_access_reg_cap_mask_high; /* Bits 127 -> 64 */ 2409 bits64_t mlrd_pcam_port_access_reg_cap_mask_low; /* Bits 63 -> 0 */ 2410 uint8_t mlrd_pcam_rsvd4[16]; 2411 bits64_t mlrd_pcam_feature_cap_mask_high; /* Bits 127 -> 64 */ 2412 bits64_t mlrd_pcam_feature_cap_mask_low; /* Bits 63 -> 0 */ 2413 uint8_t mlrd_pcam_rsvd5[24]; 2414 } mlxcx_reg_pcam_t; 2415 2416 typedef enum { 2417 MLXCX_LED_TYPE_BOTH = 0x0, 2418 MLXCX_LED_TYPE_UID = 0x1, 2419 MLXCX_LED_TYPE_PORT = 0x2, 2420 } mlxcx_led_type_t; 2421 2422 #define MLXCX_MLCR_INDIVIDUAL_ONLY (1 << 4) 2423 /* CSTYLED */ 2424 #define MLXCX_MLCR_LED_TYPE (bitdef_t){ 0, 0x0F } 2425 2426 typedef struct { 2427 uint8_t mlrd_mlcr_rsvd; 2428 uint8_t mlrd_mlcr_local_port; 2429 uint8_t mlrd_mlcr_rsvd2; 2430 bits8_t mlrd_mlcr_flags; 2431 uint8_t mlrd_mlcr_rsvd3[2]; 2432 uint16be_t mlrd_mlcr_beacon_duration; 2433 uint8_t mlrd_mlcr_rsvd4[2]; 2434 uint16be_t mlrd_mlcr_beacon_remain; 2435 } mlxcx_reg_mlcr_t; 2436 2437 typedef struct { 2438 uint8_t mlrd_pmaos_rsvd; 2439 uint8_t mlrd_pmaos_module; 2440 uint8_t mlrd_pmaos_admin_status; 2441 uint8_t mlrd_pmaos_oper_status; 2442 bits8_t mlrd_pmaos_flags; 2443 uint8_t mlrd_pmaos_rsvd2; 2444 uint8_t mlrd_pmaos_error_type; 2445 uint8_t mlrd_pmaos_event_en; 2446 uint8_t mlrd_pmaos_rsvd3[8]; 2447 } mlxcx_reg_pmaos_t; 2448 2449 typedef enum { 2450 MLXCX_MCIA_STATUS_OK = 0x0, 2451 MLXCX_MCIA_STATUS_NO_EEPROM = 0x1, 2452 MLXCX_MCIA_STATUS_NOT_SUPPORTED = 0x2, 2453 MLXCX_MCIA_STATUS_NOT_CONNECTED = 0x3, 2454 MLXCX_MCIA_STATUS_I2C_ERROR = 0x9, 2455 MLXCX_MCIA_STATUS_DISABLED = 0x10 2456 } mlxcx_mcia_status_t; 2457 2458 typedef struct { 2459 bits8_t mlrd_mcia_flags; 2460 uint8_t mlrd_mcia_module; 2461 uint8_t mlrd_mcia_rsvd; 2462 uint8_t mlrd_mcia_status; 2463 uint8_t mlrd_mcia_i2c_device_addr; 2464 uint8_t mlrd_mcia_page_number; 2465 uint16be_t mlrd_mcia_device_addr; 2466 uint8_t mlrd_mcia_rsvd2[2]; 2467 uint16be_t mlrd_mcia_size; 2468 uint8_t mlrd_mcia_rsvd3[4]; 2469 uint8_t mlrd_mcia_data[48]; 2470 } mlxcx_reg_mcia_t; 2471 2472 typedef struct { 2473 uint64be_t mlppc_ieee_802_3_frames_tx; 2474 uint64be_t mlppc_ieee_802_3_frames_rx; 2475 uint64be_t mlppc_ieee_802_3_fcs_err; 2476 uint64be_t mlppc_ieee_802_3_align_err; 2477 uint64be_t mlppc_ieee_802_3_bytes_tx; 2478 uint64be_t mlppc_ieee_802_3_bytes_rx; 2479 uint64be_t mlppc_ieee_802_3_mcast_tx; 2480 uint64be_t mlppc_ieee_802_3_bcast_tx; 2481 uint64be_t mlppc_ieee_802_3_mcast_rx; 2482 uint64be_t mlppc_ieee_802_3_bcast_rx; 2483 uint64be_t mlppc_ieee_802_3_in_range_len_err; 2484 uint64be_t mlppc_ieee_802_3_out_of_range_len_err; 2485 uint64be_t mlppc_ieee_802_3_frame_too_long_err; 2486 uint64be_t mlppc_ieee_802_3_symbol_err; 2487 uint64be_t mlppc_ieee_802_3_mac_ctrl_tx; 2488 uint64be_t mlppc_ieee_802_3_mac_ctrl_rx; 2489 uint64be_t mlppc_ieee_802_3_unsup_opcodes_rx; 2490 uint64be_t mlppc_ieee_802_3_pause_rx; 2491 uint64be_t mlppc_ieee_802_3_pause_tx; 2492 } mlxcx_ppcnt_ieee_802_3_t; 2493 2494 typedef struct { 2495 uint64be_t mlppc_rfc_2863_in_octets; 2496 uint64be_t mlppc_rfc_2863_in_ucast_pkts; 2497 uint64be_t mlppc_rfc_2863_in_discards; 2498 uint64be_t mlppc_rfc_2863_in_errors; 2499 uint64be_t mlppc_rfc_2863_in_unknown_protos; 2500 uint64be_t mlppc_rfc_2863_out_octets; 2501 uint64be_t mlppc_rfc_2863_out_ucast_pkts; 2502 uint64be_t mlppc_rfc_2863_out_discards; 2503 uint64be_t mlppc_rfc_2863_out_errors; 2504 uint64be_t mlppc_rfc_2863_in_mcast_pkts; 2505 uint64be_t mlppc_rfc_2863_in_bcast_pkts; 2506 uint64be_t mlppc_rfc_2863_out_mcast_pkts; 2507 uint64be_t mlppc_rfc_2863_out_bcast_pkts; 2508 } mlxcx_ppcnt_rfc_2863_t; 2509 2510 typedef struct { 2511 uint64be_t mlppc_phy_stats_time_since_last_clear; 2512 uint64be_t mlppc_phy_stats_rx_bits; 2513 uint64be_t mlppc_phy_stats_symbol_errs; 2514 uint64be_t mlppc_phy_stats_corrected_bits; 2515 uint8_t mlppc_phy_stats_rsvd[2]; 2516 uint8_t mlppc_phy_stats_raw_ber_mag; 2517 uint8_t mlppc_phy_stats_raw_ber_coef; 2518 uint8_t mlppc_phy_stats_rsvd2[2]; 2519 uint8_t mlppc_phy_stats_eff_ber_mag; 2520 uint8_t mlppc_phy_stats_eff_ber_coef; 2521 } mlxcx_ppcnt_phy_stats_t; 2522 2523 typedef enum { 2524 MLXCX_PPCNT_GRP_IEEE_802_3 = 0x0, 2525 MLXCX_PPCNT_GRP_RFC_2863 = 0x1, 2526 MLXCX_PPCNT_GRP_RFC_2819 = 0x2, 2527 MLXCX_PPCNT_GRP_RFC_3635 = 0x3, 2528 MLXCX_PPCNT_GRP_ETH_EXTD = 0x5, 2529 MLXCX_PPCNT_GRP_ETH_DISCARD = 0x6, 2530 MLXCX_PPCNT_GRP_PER_PRIO = 0x10, 2531 MLXCX_PPCNT_GRP_PER_TC = 0x11, 2532 MLXCX_PPCNT_GRP_PER_TC_CONGEST = 0x13, 2533 MLXCX_PPCNT_GRP_PHY_STATS = 0x16 2534 } mlxcx_ppcnt_grp_t; 2535 2536 typedef enum { 2537 MLXCX_PPCNT_CLEAR = (1 << 7), 2538 MLXCX_PPCNT_NO_CLEAR = 0 2539 } mlxcx_ppcnt_clear_t; 2540 2541 typedef struct { 2542 uint8_t mlrd_ppcnt_swid; 2543 uint8_t mlrd_ppcnt_local_port; 2544 uint8_t mlrd_ppcnt_pnat; 2545 uint8_t mlrd_ppcnt_grp; 2546 uint8_t mlrd_ppcnt_clear; 2547 uint8_t mlrd_ppcnt_rsvd[2]; 2548 uint8_t mlrd_ppcnt_prio_tc; 2549 union { 2550 uint8_t mlrd_ppcnt_data[248]; 2551 mlxcx_ppcnt_ieee_802_3_t mlrd_ppcnt_ieee_802_3; 2552 mlxcx_ppcnt_rfc_2863_t mlrd_ppcnt_rfc_2863; 2553 mlxcx_ppcnt_phy_stats_t mlrd_ppcnt_phy_stats; 2554 }; 2555 } mlxcx_reg_ppcnt_t; 2556 2557 typedef enum { 2558 MLXCX_PPLM_FEC_CAP_AUTO = 0, 2559 MLXCX_PPLM_FEC_CAP_NONE = (1 << 0), 2560 MLXCX_PPLM_FEC_CAP_FIRECODE = (1 << 1), 2561 MLXCX_PPLM_FEC_CAP_RS = (1 << 2), 2562 } mlxcx_pplm_fec_caps_t; 2563 2564 typedef enum { 2565 MLXCX_PPLM_FEC_ACTIVE_NONE = (1 << 0), 2566 MLXCX_PPLM_FEC_ACTIVE_FIRECODE = (1 << 1), 2567 MLXCX_PPLM_FEC_ACTIVE_RS528 = (1 << 2), 2568 MLXCX_PPLM_FEC_ACTIVE_RS271 = (1 << 3), 2569 MLXCX_PPLM_FEC_ACTIVE_RS544 = (1 << 7), 2570 MLXCX_PPLM_FEC_ACTIVE_RS272 = (1 << 9), 2571 } mlxcx_pplm_fec_active_t; 2572 2573 /* CSTYLED */ 2574 #define MLXCX_PPLM_CAP_56G (bitdef_t){ 16, 0x000f0000 } 2575 /* CSTYLED */ 2576 #define MLXCX_PPLM_CAP_100G (bitdef_t){ 12, 0x0000f000 } 2577 /* CSTYLED */ 2578 #define MLXCX_PPLM_CAP_50G (bitdef_t){ 8, 0x00000f00 } 2579 /* CSTYLED */ 2580 #define MLXCX_PPLM_CAP_25G (bitdef_t){ 4, 0x000000f0 } 2581 /* CSTYLED */ 2582 #define MLXCX_PPLM_CAP_10_40G (bitdef_t){ 0, 0x0000000f } 2583 2584 typedef struct { 2585 uint8_t mlrd_pplm_rsvd; 2586 uint8_t mlrd_pplm_local_port; 2587 uint8_t mlrd_pplm_rsvd1[11]; 2588 uint24be_t mlrd_pplm_fec_mode_active; 2589 bits32_t mlrd_pplm_fec_override_cap; 2590 bits32_t mlrd_pplm_fec_override_admin; 2591 uint16be_t mlrd_pplm_fec_override_cap_400g_8x; 2592 uint16be_t mlrd_pplm_fec_override_cap_200g_4x; 2593 uint16be_t mlrd_pplm_fec_override_cap_100g_2x; 2594 uint16be_t mlrd_pplm_fec_override_cap_50g_1x; 2595 uint16be_t mlrd_pplm_fec_override_admin_400g_8x; 2596 uint16be_t mlrd_pplm_fec_override_admin_200g_4x; 2597 uint16be_t mlrd_pplm_fec_override_admin_100g_2x; 2598 uint16be_t mlrd_pplm_fec_override_admin_50g_1x; 2599 uint8_t mlrd_pplm_rsvd2[8]; 2600 uint16be_t mlrd_pplm_fec_override_cap_hdr; 2601 uint16be_t mlrd_pplm_fec_override_cap_edr; 2602 uint16be_t mlrd_pplm_fec_override_cap_fdr; 2603 uint16be_t mlrd_pplm_fec_override_cap_fdr10; 2604 uint16be_t mlrd_pplm_fec_override_admin_hdr; 2605 uint16be_t mlrd_pplm_fec_override_admin_edr; 2606 uint16be_t mlrd_pplm_fec_override_admin_fdr; 2607 uint16be_t mlrd_pplm_fec_override_admin_fdr10; 2608 } mlxcx_reg_pplm_t; 2609 2610 typedef struct { 2611 uint8_t mlrd_mtcap_rsvd[3]; 2612 uint8_t mlrd_mtcap_sensor_count; 2613 uint8_t mlrd_mtcap_rsvd1[4]; 2614 uint64be_t mlrd_mtcap_sensor_map; 2615 } mlxcx_reg_mtcap_t; 2616 2617 #define MLXCX_MTMP_NAMELEN 8 2618 2619 typedef struct { 2620 uint8_t mlrd_mtmp_rsvd[2]; 2621 uint16be_t mlrd_mtmp_sensor_index; 2622 uint8_t mlrd_mtmp_rsvd1[2]; 2623 uint16be_t mlrd_mtmp_temperature; 2624 bits16_t mlrd_mtmp_max_flags; 2625 uint16be_t mlrd_mtmp_max_temperature; 2626 bits16_t mlrd_mtmp_tee; 2627 uint16be_t mlrd_mtmp_temp_thresh_hi; 2628 uint8_t mlrd_mtmp_rsvd2[2]; 2629 uint16be_t mlrd_mtmp_temp_thresh_lo; 2630 uint8_t mlrd_mtmp_rsvd3[4]; 2631 uint8_t mlrd_mtmp_name[MLXCX_MTMP_NAMELEN]; 2632 } mlxcx_reg_mtmp_t; 2633 2634 typedef enum { 2635 MLXCX_REG_PMTU = 0x5003, 2636 MLXCX_REG_PTYS = 0x5004, 2637 MLXCX_REG_PAOS = 0x5006, 2638 MLXCX_REG_PMAOS = 0x5012, 2639 MLXCX_REG_MSGI = 0x9021, 2640 MLXCX_REG_MLCR = 0x902B, 2641 MLXCX_REG_MCIA = 0x9014, 2642 MLXCX_REG_PPCNT = 0x5008, 2643 MLXCX_REG_PPLM = 0x5023, 2644 MLXCX_REG_PCAM = 0x507f, 2645 MLXCX_REG_MTCAP = 0x9009, 2646 MLXCX_REG_MTMP = 0x900A 2647 } mlxcx_register_id_t; 2648 2649 typedef union { 2650 mlxcx_reg_pmtu_t mlrd_pmtu; 2651 mlxcx_reg_paos_t mlrd_paos; 2652 mlxcx_reg_pcam_t mlrd_pcam; 2653 mlxcx_reg_ptys_t mlrd_ptys; 2654 mlxcx_reg_mlcr_t mlrd_mlcr; 2655 mlxcx_reg_pmaos_t mlrd_pmaos; 2656 mlxcx_reg_mcia_t mlrd_mcia; 2657 mlxcx_reg_ppcnt_t mlrd_ppcnt; 2658 mlxcx_reg_pplm_t mlrd_pplm; 2659 mlxcx_reg_mtcap_t mlrd_mtcap; 2660 mlxcx_reg_mtmp_t mlrd_mtmp; 2661 } mlxcx_register_data_t; 2662 2663 typedef enum { 2664 MLXCX_CMD_ACCESS_REGISTER_READ = 1, 2665 MLXCX_CMD_ACCESS_REGISTER_WRITE = 0 2666 } mlxcx_cmd_reg_opmod_t; 2667 2668 typedef struct { 2669 mlxcx_cmd_in_t mlxi_access_register_head; 2670 uint8_t mlxi_access_register_rsvd[2]; 2671 uint16be_t mlxi_access_register_register_id; 2672 uint32be_t mlxi_access_register_argument; 2673 mlxcx_register_data_t mlxi_access_register_data; 2674 } mlxcx_cmd_access_register_in_t; 2675 2676 typedef struct { 2677 mlxcx_cmd_out_t mlxo_access_register_head; 2678 uint8_t mlxo_access_register_rsvd[8]; 2679 mlxcx_register_data_t mlxo_access_register_data; 2680 } mlxcx_cmd_access_register_out_t; 2681 2682 #pragma pack() 2683 2684 CTASSERT(MLXCX_SQE_MAX_PTRS > 0); 2685 2686 #ifdef __cplusplus 2687 } 2688 #endif 2689 2690 #endif /* _MLXCX_REG_H */ 2691