Searched refs:AVIVO_D1CRTC_CONTROL (Results 1 – 5 of 5) sorted by relevance
280 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; in rv515_mc_stop()283 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_stop()288 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()301 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_stop()303 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()422 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_resume()424 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_resume()
98 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) in avivo_wait_for_vblank()333 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_prepare()335 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in rs600_pm_prepare()351 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_finish()353 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in rs600_pm_finish()
348 #define AVIVO_D1CRTC_CONTROL 0x6080 macro
689 reg = RREG32(AVIVO_D1CRTC_CONTROL) | in radeon_card_posted()
1593 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { in r600_is_display_hung()