Searched refs:CLK_TYPE_DIV6_RO (Results 1 – 2 of 2) sorted by relevance
37 CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */ enumerator56 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
354 case CLK_TYPE_DIV6_RO: in cpg_mssr_register_core_clk()364 if (core->type == CLK_TYPE_DIV6_RO) in cpg_mssr_register_core_clk()