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Searched refs:CP_HQD_WG_STATE_OFFSET__OFFSET_MASK (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h4149 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x1fffffc macro
H A Dgfx_8_1_sh_mask.h4671 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x1fffffc macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h13143 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK … macro
H A Dgc_9_2_1_sh_mask.h14308 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK … macro
H A Dgc_9_1_sh_mask.h14443 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK … macro
H A Dgc_9_4_3_sh_mask.h16675 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK … macro
H A Dgc_9_4_2_sh_mask.h4241 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK … macro
H A Dgc_11_5_0_sh_mask.h14380 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK … macro
H A Dgc_11_0_0_sh_mask.h17686 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK … macro
H A Dgc_11_0_3_sh_mask.h19931 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK … macro
H A Dgc_10_1_0_sh_mask.h20566 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK … macro
H A Dgc_10_3_0_sh_mask.h18719 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK … macro