Searched refs:DBC (Results 1 – 5 of 5) sorted by relevance
242 (DBC for short) is solely for the use of that workload and is not shared with245 Each DBC is a pair of FIFOs that manage data in and out of the workload. One248 Each DBC contains 4 registers in hardware:263 DBC registers are exposed to the host via the second BAR. Each DBC consumes269 memory must be provided per DBC, which hosts both FIFOs. The request FIFO will409 response FIFO of a DBC. The DMA Bridge hardware has an IRQ storm mitigation450 used by the DBC.488 channel. This notification identifies the workload by it's assigned DBC. A490 DBC/NSPs into a working state.
53 interrupt handlers for every DBC and MHI wake up for every interrupt that54 arrives; however, the DBC threaded irq handlers only are started when work to be57 If the DBC is configured to force MSI interrupts, this can circumvent the124 DMA Bridge, and as such, locks the BO to a specific DBC.172 workload should be allowed to interface with the DBC.
216 if (PSP_FEATURE(psp, DBC) || in psp_init()
453 DBC = 0x38, enumerator
982 AMD CRYPTOGRAPHIC COPROCESSOR (CCP) DRIVER - DBC SUPPORT