| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_util_32.h | 338 bool DCCEnable[],
436 bool DCCEnable,
511 bool DCCEnable,
791 bool DCCEnable,
901 bool DCCEnable[],
952 bool DCCEnable[],
1039 bool DCCEnable[],
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| H A D | display_mode_vba_util_32.c | 1770 bool DCCEnable[], in dml32_CalculateSurfaceSizeInMall() argument
2018 myPipe[k].DCCEnable, in dml32_CalculateVMRowAndSwath()
2092 myPipe[k].DCCEnable, in dml32_CalculateVMRowAndSwath()
2221 myPipe[k].DCCEnable, in dml32_CalculateVMRowAndSwath()
2260 bool DCCEnable, in dml32_CalculateVMAndRowBytes() argument
2368 if (DCCEnable != true) { in dml32_CalculateVMAndRowBytes()
2667 bool DCCEnable, in dml32_CalculateRowBandwidth() argument
4134 bool DCCEnable, in dml32_CalculateFlipSchedule() argument
4881 bool DCCEnable[], in dml32_CalculateMetaAndPTETimes() argument
5152 bool DCCEnable[], in dml32_CalculateVMGroupAndRequestTimes() argument
[all …]
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| H A D | display_mode_vba_32.c | 390 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
574 if (mode_lib->vba.DCCEnable[k]) in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1056 mode_lib->vba.DCCEnable[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1298 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1349 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1392 mode_lib->vba.DCCEnable[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1556 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1620 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2654 mode_lib->vba.DCCEnable, in dml32_ModeSupportAndSystemConfigurationFull()
3284 …mmy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.DCCEnable = mode_lib->vba.DCCEnable[k]; in dml32_ModeSupportAndSystemConfigurationFull()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_mode_vba_30.c | 183 bool DCCEnable,
227 bool DCCEnable,
260 bool DCCEnable,
318 bool DCCEnable[],
1659 bool DCCEnable, in CalculateVMAndRowBytes() argument
2446 myPipe.DCCEnable = v->DCCEnable[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2765 v->DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2868 v->DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2917 v->DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3040 v->DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_mode_vba_21.c | 104 bool DCCEnable,
172 bool DCCEnable,
235 bool DCCEnable,
267 bool DCCEnable,
311 bool DCCEnable[],
657 bool DCCEnable, in CalculatePrefetchSchedule() argument
1260 bool DCCEnable, in CalculateVMAndRowBytes() argument
3129 bool DCCEnable, in CalculateActiveRowBandwidth() argument
3183 bool DCCEnable, in CalculateFlipSchedule() argument
5268 bool DCCEnable[], in CalculateWatermarksAndDRAMSpeedChangeSupport()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_mode_vba_31.c | 200 bool DCCEnable,
240 bool DCCEnable,
410 bool DCCEnable[],
459 bool DCCEnable[],
518 bool DCCEnable[],
1793 bool DCCEnable, argument
2623 myPipe.DCCEnable = v->DCCEnable[k];
3029 v->DCCEnable,
3078 v->DCCEnable,
3261 v->DCCEnable,
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_mode_vba_314.c | 212 bool DCCEnable,
252 bool DCCEnable,
422 bool DCCEnable[],
471 bool DCCEnable[],
530 bool DCCEnable[],
1813 bool DCCEnable, argument
2645 myPipe.DCCEnable = v->DCCEnable[k];
3051 v->DCCEnable,
3100 v->DCCEnable,
3283 v->DCCEnable,
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | display_mode_vba_20.c | 83 bool DCCEnable,
134 bool DCCEnable,
183 bool DCCEnable,
212 bool DCCEnable,
466 bool DCCEnable, in CalculatePrefetchSchedule()
589 } else if (DCCEnable) in CalculatePrefetchSchedule()
710 || DCCEnable) ? in CalculatePrefetchSchedule()
861 bool DCCEnable, in CalculateVMAndRowBytes() argument
898 if (DCCEnable == true) { in CalculateVMAndRowBytes()
3042 bool DCCEnable, in CalculateActiveRowBandwidth() argument
[all …]
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| H A D | display_mode_vba_20v2.c | 108 bool DCCEnable,
158 bool DCCEnable,
207 bool DCCEnable,
236 bool DCCEnable,
558 bool DCCEnable, in CalculatePrefetchSchedule() argument
649 } else if (DCCEnable) in CalculatePrefetchSchedule()
770 || DCCEnable) ? in CalculatePrefetchSchedule()
921 bool DCCEnable, in CalculateVMAndRowBytes() argument
958 if (DCCEnable == true) { in CalculateVMAndRowBytes()
3115 bool DCCEnable, in CalculateActiveRowBandwidth() argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | display_mode_core.c | 233 dml_bool_t DCCEnable,
294 dml_bool_t DCCEnable,
327 dml_bool_t DCCEnable,
503 dml_bool_t DCCEnable[],
554 dml_bool_t DCCEnable[],
668 dml_bool_t DCCEnable[],
1908 dml_bool_t DCCEnable, in CalculateRowBandwidth() argument
1964 dml_bool_t DCCEnable, in CalculateFlipSchedule() argument
2448 dml_bool_t DCCEnable, in CalculateVMAndRowBytes() argument
6376 myPipe->DCCEnable = mode_lib->ms.cache_display_cfg.surface.DCCEnable[k]; in dml_prefetch_check()
[all …]
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| H A D | dml2_utils.c | 106 dml_surface_array->DCCEnable[dst_index] = dml_surface_array->DCCEnable[src_index]; in dml2_util_copy_dml_surface()
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| H A D | display_mode_core_structs.h | 416 dml_bool_t DCCEnable; member
534 dml_bool_t DCCEnable[__DML_NUM_PLANES__]; member
1509 dml_bool_t *DCCEnable; member
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| H A D | dml2_translation_helper.c | 743 out->DCCEnable[location] = false; in populate_dummy_dml_surface_cfg()
762 out->DCCEnable[location] = in->dcc.enable; in populate_dml_surface_cfg_from_plane_state()
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| H A D | display_mode_util.c | 600 dml_print("DML: surface_cfg: plane=%d, DCCEnable = %d\n", i, surface->DCCEnable[i]); in dml_print_dml_display_cfg_surface()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 117 bool DCCEnable; member
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| H A D | display_mode_vba.h | 478 bool DCCEnable[DC__NUM_DPP__MAX]; member
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| H A D | display_mode_vba.c | 609 mode_lib->vba.DCCEnable[mode_lib->vba.NumberOfActivePlanes] = in fetch_pipe_params()
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