| /linux/Documentation/driver-api/media/drivers/ |
| H A D | pxa_camera.rst | 46 | | DMA: stop | | DMA: stop | |
56 | | DMA: stop | / | DMA: run | | |
66 | DMA: run | | DMA: run | |
75 | DMA: run | | DMA: stop |
84 - "DMA: stop" means all 3 DMA channels are stopped
85 - "DMA: run" means at least 1 DMA channel is still running
87 DMA usage
90 a) DMA flow
94 starts the DMA chain.
148 As DMA chaining is done while DMA _is_ running, the linking may be done
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| /linux/Documentation/translations/zh_CN/PCI/ |
| H A D | pci.rst | 55 - 设置DMA掩码大小（对于流式和一致的DMA）
183 - 设置DMA掩码大小（对于流式和一致的DMA）
250 设置DMA掩码大小
254 驱动程序需要说明设备的DMA功能，并不是DMA接口的权威来源。
274 用设备的动态DMA映射，了解DMA API的完整描述。本节只是提醒大家，需要在设备上启
275 用DMA之前完成。
318 2) MSI避免了DMA/IRQ竞争条件。到主机内存的DMA被保证在MSI交付时对主机CPU是可
364 在试图取消分配DMA控制数据之前，停止所有的DMA操作是非常重要的。如果不这样做，
367 在停止IRQ后停止DMA可以避免IRQ处理程序可能重新启动DMA引擎的竞争。
373 释放DMA缓冲区
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| /linux/drivers/dma/ |
| H A D | Kconfig | 3 # DMA engine configuration
7 bool "DMA Engine support"
18 bool "DMA Engine debugging"
35 comment "DMA Devices"
406 DMA controller is having single DMA channel which can be
506 Support the MXS DMA engine. This engine including APBH-DMA
613 The DMA controller has multiple DMA channels which can be configured
624 DMA controller is having multiple DMA channel which can be
637 controller driver. The DMA controller has multiple DMA channels
705 tristate "Xilinx DMA/Bridge Subsystem DMA Engine"
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| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | dma.txt | 1 * Freescale DMA Controllers
3 ** Freescale Elo DMA Controller
13 DMA channels and the address space of the DMA controller
17 - DMA channel nodes:
68 ** Freescale EloPlus DMA Controller
81 DMA channels and the address space of the DMA controller
83 - DMA channel nodes:
128 ** Freescale Elo3 DMA Controller
140 DMA channels and the address space of the DMA controller
142 - DMA channel nodes:
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| /linux/Documentation/devicetree/bindings/dma/ |
| H A D | ti-dma-crossbar.txt | 1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
18 when mapping xbar input to DMA request, they are either
24 the DMA event number as crossbar ID (input to the DMA crossbar).
33 /* DMA controller */
46 /* DMA crossbar */
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| H A D | sprd,sc9860-dma.yaml | 7 title: Spreadtrum SC9860 DMA controller
10 There are three DMA controllers: AP DMA, AON DMA and AGCP DMA. For AGCP
11 DMA controller, it can or do not request the IRQ, which will save
12 system power without resuming system by DMA interrupts if AGCP DMA
33 - description: DMA enable clock
34 - description: optional ashb_eb clock, only for the AGCP DMA controller
71 /* AP DMA controller */
82 /* AGCP DMA controller */
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| H A D | mpc512x-dma.txt | 1 * Freescale MPC512x and MPC8308 DMA Controller
3 The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
7 Refer to "Generic DMA Controller and DMA request bindings" in
12 - reg: should contain the DMA controller registers location and length;
13 - interrupt for the DMA controller: syntax of interrupt client node
15 - #dma-cells: the length of the DMA specifier, must be <1>.
16 Each channel of this DMA controller has a peripheral request line,
29 DMA clients must use the format described in dma/dma.txt file.
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| H A D | intel,ldma.yaml | 7 title: Lightning Mountain centralized DMA controllers.
34 The first cell is the peripheral's DMA request line.
61 DMA descriptor polling counter is used to control the poling mechanism
67 DMA byte enable is only valid for DMA write(RX).
68 Byte enable(1) means DMA write will be based on the number of dwords
74 DMA descriptor read back to make sure data and desc synchronization.
79 Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst;
80 if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16.
81 It only applies to RX DMA and memcopy DMA.
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| H A D | dma-common.yaml | 7 title: DMA Engine Common Properties
13 Generic binding to provide a way for a driver using DMA Engine to
14 retrieve the DMA request or channel information that goes from a
15 hardware device to a DMA controller.
25 Used to provide DMA controller specific information.
29 Bitmask of available DMA channels in ascending order that are
43 Number of DMA channels supported by the controller.
48 Number of DMA request signals supported by the controller.
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| H A D | dma-router.yaml | 7 title: DMA Router Common Properties
16 DMA routers are transparent IP blocks used to route DMA request
17 lines from devices to the DMA controller. Some SoCs (like TI DRA7x)
18 have more peripherals integrated with DMA requests than what the DMA
30 Array of phandles to the DMA controllers the router can direct
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| /linux/Documentation/devicetree/bindings/soc/ti/ |
| H A D | keystone-navigator-dma.txt | 1 Keystone Navigator DMA Controller
9 an internal packet DMA module which is used as an infrastructure DMA
12 Navigator DMA cloud layout:
17 |-> DMA instance #0
19 |-> DMA instance #1
23 |-> DMA instance #n
25 Navigator DMA properties:
34 into DMA and the DMA uses it as the physical addresses to reach queue
40 DMA instance properties:
94 Navigator DMA client:
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| /linux/Documentation/core-api/ |
| H A D | dma-isa-lpc.rst | 2 DMA with ISA and LPC devices
7 This document describes how to do DMA transfers using the old ISA DMA
9 uses the same DMA system so it will be around for quite some time.
14 To do ISA style DMA you need to include two headers::
87 Now for the good stuff, the actual DMA transfer. :)
89 Before you use any ISA DMA routines you need to claim the DMA lock
94 The first time you use the DMA controller you should call
95 clear_dma_ff(). This clears an internal register in the DMA
109 The final step is enabling the DMA channel and releasing the DMA
140 printk(KERN_ERR "driver: Incomplete DMA transfer!"
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| H A D | dma-api-howto.rst | 2 Dynamic DMA mapping Guide
13 CPU and DMA addresses
109 everywhere you hold a DMA address returned from the DMA mapping functions.
111 What memory is DMA'able?
125 returned from vmalloc() for DMA. It is possible to DMA to the
147 for you to DMA from/to.
296 Types of DMA mappings
345 - Streaming DMA mappings which are usually mapped for one DMA
391 return > 32-bit addresses for DMA if the consistent DMA mask has been
459 DMA Direction
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| /linux/Documentation/arch/arm/stm32/ |
| H A D | stm32-dma-mdma-chaining.rst | 4 STM32 DMA-MDMA chaining
15 direct memory access controllers (DMA).
17 STM32MP1 SoCs embed both STM32 DMA and STM32 MDMA controllers. STM32 DMA
23 STM32 DMAMUX routes any DMA request from a given peripheral to any STM32 DMA
26 **STM32 DMA**
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
54 the STM32 DMA transfer.
72 | STM32 DMAMUX | STM32 DMA | STM32 DMA | STM32 MDMA |
112 Due to STM32 DMA legacy (within microcontrollers), STM32 DMA performances are
156 If the SRAM period is greater than the expected DMA transfer, then STM32 DMA
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| /linux/drivers/dma/sh/ |
| H A D | Kconfig | 3 # DMA engine configuration for sh
11 # DMA Engine Helpers
15 bool "Renesas SuperH DMA Engine support"
22 Enable support for the Renesas SuperH DMA controllers.
25 # DMA Controllers
32 Enable support for the Renesas SuperH DMA controllers.
35 tristate "Renesas R-Car Gen{2,3} and RZ/G{1,2} DMA Controller"
39 This driver supports the general purpose DMA controller found in the
43 tristate "Renesas USB-DMA Controller"
48 This driver supports the USB-DMA controller found in the Renesas
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| /linux/Documentation/driver-api/dmaengine/ |
| H A D | client.rst | 2 DMA Engine API Guide
12 DMA Engine. This is applicable only for slave DMA usage only.
14 DMA usage
17 The slave DMA usage consists of following steps:
19 - Allocate a DMA slave channel
31 1. Allocate a DMA slave channel
56 DMA direction, DMA addresses, bus widths, DMA burst lengths etc
79 DMA-engine are:
150 case for slave/cyclic DMA.
158 DMA via dmaengine_terminate_async().
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| /linux/Documentation/misc-devices/ |
| H A D | mrvl_cn10k_dpi.rst | 4 Marvell CN10K DMA packet interface (DPI) driver
10 DPI is a DMA packet interface hardware block in Marvell's CN10K silicon.
12 mailbox logic, and a set of DMA engines & DMA command queues.
15 requests from its VF functions and provisions DMA engine resources to
20 the DMA engines and VF device's DMA command queues. Also, driver creates
21 /dev/mrvl-cn10k-dpi node to set DMA engine and PEM (PCIe interface) port
26 DMA operations. Only VF devices are provisioned with DMA capabilities.
38 a pem port to which DMA engines are wired.
42 ioctl that sets DMA engine's fifo sizes & max outstanding load request
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| /linux/Documentation/devicetree/bindings/dma/stm32/ |
| H A D | st,stm32-dma.yaml | 7 title: STMicroelectronics STM32 DMA Controller
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
17 3. A 32bit mask specifying the DMA channel configuration which are device
34 -bit 0-1: DMA FIFO threshold selection
39 -bit 2: DMA direct mode
41 0x1: Direct mode: each DMA request immediately initiates a transfer
43 -bit 4: alternative DMA request/acknowledge protocol
73 description: Should contain all of the per-channel DMA
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| /linux/drivers/dma/stm32/ |
| H A D | Kconfig | 3 # STM32 DMA controllers drivers
8 bool "STMicroelectronics STM32 DMA support"
12 Enable support for the on-chip DMA controller on STMicroelectronics
14 If you have a board based on STM32 SoC with such DMA controller
15 and want to use DMA say Y here.
18 bool "STMicroelectronics STM32 DMA multiplexer support"
21 Enable support for the on-chip DMA multiplexer on STMicroelectronics
23 If you have a board based on STM32 SoC with such DMA multiplexer
27 bool "STMicroelectronics STM32 master DMA support"
34 If you have a board based on STM32 SoC with such DMA controller
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| /linux/Documentation/driver-api/ |
| H A D | dma-buf.rst | 33 Shared DMA Buffers
128 DMA-BUF statistics
133 DMA Buffer ioctls
165 DMA Fences
183 DMA Fence Deadline Hints
198 DMA Fence Array
207 DMA Fence Chain
216 DMA Fence unwrap
222 DMA Fence Sync File
237 Indefinite DMA Fences
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| /linux/Documentation/driver-api/usb/ |
| H A D | dma.rst | 1 USB DMA
5 over how DMA may be used to perform I/O operations. The APIs are detailed
11 The big picture is that USB drivers can continue to ignore most DMA issues,
12 though they still must provide DMA-ready buffers (see
14 the 2.4 (and earlier) kernels, or they can now be DMA-aware.
16 DMA-aware usb drivers:
18 - New calls enable DMA-aware drivers, letting them allocate dma buffers and
25 - "usbcore" will map this DMA address, if a DMA-aware driver didn't do
41 IOMMU to manage the DMA mappings. It can cost MUCH more to set up and
64 "streaming" DMA mappings.)
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| /linux/Documentation/i2c/ |
| H A D | dma-considerations.rst | 2 Linux I2C and DMA
6 transferred are small, it is not considered a prime user of DMA access. At this
7 time of writing, only 10% of I2C bus master drivers have DMA support
9 DMA for it will likely add more overhead than a plain PIO transfer.
11 Therefore, it is *not* mandatory that the buffer of an I2C message is DMA safe.
13 rarely used. However, it is recommended to use a DMA-safe buffer if your
14 message size is likely applicable for DMA. Most drivers have this threshold
18 I2C bus master driver is using USB as a bridge, then you need to have DMA
24 For clients, if you use a DMA safe buffer in i2c_msg, set the I2C_M_DMA_SAFE
34 of i2c_master_send() and i2c_master_recv() functions can now use DMA safe
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| /linux/drivers/dma/ti/ |
| H A D | Kconfig | 3 # Texas Instruments DMA drivers
7 tristate "Texas Instruments CPPI 4.1 DMA support"
11 The Communications Port Programming Interface (CPPI) 4.1 DMA engine
22 Enable support for the TI EDMA (Enhanced DMA) controller. This DMA
34 Enable support for the TI sDMA (System DMA or DMA4) controller. This
35 DMA engine is found on OMAP and DRA7xx parts.
47 Enable support for the TI UDMA (Unified DMA) controller. This
48 DMA engine is used in AM65x and j721e.
55 Say y here to support the K3 NAVSS DMA glue interface
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| /linux/Documentation/devicetree/bindings/powerpc/4xx/ |
| H A D | ppc440spe-adma.txt | 1 PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
4 are specified hereby. These are I2O/DMA, DMA and XOR nodes
5 for DMA engines and Memory Queue Module node. The latter is used
9 DMA devices.
28 ii) The DMA node
33 - cell-index : 1 cell, hardware index of the DMA engine
39 and DMA Error IRQ (on UIC1). The latter is common
40 for both DMA engines>.
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| /linux/drivers/dma/qcom/ |
| H A D | Kconfig | 8 Enable support for the Qualcomm Application Data Mover (ADM) DMA
10 This controller provides DMA capabilities for both general purpose
14 tristate "QCOM BAM DMA support"
19 Enable support for the QCOM BAM DMA controller. This controller
20 provides DMA capabilities for a variety of on-chip devices.
23 tristate "Qualcomm Technologies GPI DMA support"
28 Enable support for the QCOM GPI DMA controller. This controller
29 provides DMA capabilities for a variety of peripheral buses such
40 Each DMA device requires one management interface driver
55 purpose slave DMA.
|