/linux/Documentation/devicetree/bindings/memory-controllers/ |
H A D | rockchip,rk3399-dmc.yaml | 130 When the DRAM type is DDR3, this parameter defines the ODT disable 132 the ODT on the DRAM side and controller side are both disabled. 138 When the DRAM type is DDR3, this parameter defines the DRAM side drive 146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT 180 ODT on the DRAM side and controller side are both disabled. 186 When the DRAM type is LPDDR3, this parameter defines the DRAM side drive 194 When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT 227 the ODT on the DRAM side and controller side are both disabled. 233 When the DRAM type is LPDDR4, this parameter defines the DRAM side drive 241 When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on [all …]
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H A D | samsung,exynos5422-dmc.yaml | 17 DRAM memory chips are connected. The driver is to monitor the controller in 55 phandle of the connected DRAM memory device. For more information please
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H A D | calxeda-ddr-ctrlr.yaml | 12 purposes and to learn about the DRAM topology.
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/linux/Documentation/hid/ |
H A D | amd-sfh-hid.rst | 60 on that allocates the DRAM address for each and every sensor and passes it to MP2-PCIe driver. On 72 2. Data transfer via DRAM. 77 the PCI layer. MP2 firmware writes the command output to the access DRAM memory which the client 78 layer has allocated. Firmware always writes minimum of 32 bytes into DRAM. So as a protocol driver 79 shall allocate minimum of 32 bytes DRAM space. 103 | | | Allocate the DRAM | Enable | 136 | | | Read the DRAM data for| | |
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/linux/drivers/memory/tegra/ |
H A D | Kconfig | 22 Tegra20 chips. The EMC controls the external DRAM on the board. 34 Tegra30 chips. The EMC controls the external DRAM on the board. 46 Tegra124 chips. The EMC controls the external DRAM on the board. 60 Tegra210 chips. The EMC controls the external DRAM on the board.
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/linux/Documentation/devicetree/bindings/clock/ |
H A D | allwinner,sun4i-a10-pll5-clk.yaml | 7 title: Allwinner A10 DRAM PLL 19 The first output is the DRAM clock output, the second is meant
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/linux/sound/isa/gus/ |
H A D | gus_dram.c | 28 outsb(GUSP(gus, DRAM), buffer, size1); in snd_gus_dram_poke() 64 insb(GUSP(gus, DRAM), buffer, size1); in snd_gus_dram_peek()
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/linux/drivers/memory/samsung/ |
H A D | Kconfig | 19 Frequency Scaling in DMC and DRAM. It also supports changing timings 20 of DRAM running with different frequency. The timings are calculated
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/linux/Documentation/devicetree/bindings/firmware/ |
H A D | nvidia,tegra210-bpmp.txt | 6 (suspend to ram), and also offloading DRAM memory clock scaling on 23 - #clock-cells : Should be 1 for platforms where DRAM clock control is
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/linux/Documentation/devicetree/bindings/arm/sunxi/ |
H A D | allwinner,sun4i-a10-mbus.yaml | 51 - description: DRAM controller/PHY registers 63 - description: DRAM controller/PHY module clock 64 - description: Register bus clock, shared by MBUS and DRAM
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/linux/arch/arm/configs/ |
H A D | dram_0x00000000.config | 1 # Help: DRAM base at 0x00000000
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H A D | dram_0xc0000000.config | 1 # Help: DRAM base at 0xc0000000
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H A D | dram_0xd0000000.config | 1 # Help: DRAM base at 0xd0000000
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/linux/Documentation/driver-api/ |
H A D | edac.rst | 18 The individual DRAM chips on a memory stick. These devices commonly 69 This is the name of the DRAM signal used to select the DRAM ranks to be 112 communication lanes. It uses vertically stacked memory chips (DRAM dies) 202 of 4096-bits of DRAM data bus. 204 While the UMC is interfacing a 16GB (8high X 2GB DRAM) HBM stack, each UMC 205 channel is interfacing 2GB of DRAM (represented as rank).
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/linux/arch/arm/ |
H A D | Kconfig-nommu | 14 hex '(S)DRAM Base Address' if SET_MEM_PARAM 18 hex '(S)DRAM SIZE' if SET_MEM_PARAM
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/linux/Documentation/admin-guide/perf/ |
H A D | meson-ddr-pmu.rst | 7 The Amlogic Meson G12 SoC contains a bandwidth monitor inside DRAM controller. 9 DRAM. The channel can count up to 3 AXI port simultaneously. It can be helpful
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/linux/Documentation/translations/zh_CN/mm/damon/ |
H A D | index.rst | 19 - *准确度* (监测输出对DRAM级别的内存管理足够有用;但可能不适合CPU Cache级别),
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/linux/Documentation/hwmon/ |
H A D | asus_wmi_sensors.rst | 37 * DRAM Voltage, 48 * DRAM Voltage,
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/linux/Documentation/devicetree/bindings/media/ |
H A D | allwinner,sun4i-a10-csi.yaml | 39 - description: The CSI DRAM clock 44 - description: The CSI DRAM clock
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/linux/arch/arm64/boot/dts/broadcom/stingray/ |
H A D | stingray-board-base.dtsi | 22 &memory { /* Default DRAM banks */
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/linux/drivers/ras/amd/atl/ |
H A D | Kconfig | 20 Enable this option if using DRAM ECC on Zen-based systems
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/linux/arch/arm/mach-lpc32xx/ |
H A D | suspend.S | 51 @ This guarantees a small windows where DRAM isn't busy
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/linux/arch/arm64/boot/dts/nuvoton/ |
H A D | ma35d1-iot-512m.dts | 25 reg = <0x00000000 0x80000000 0 0x20000000>; /* 512M DRAM */
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H A D | ma35d1-som-256m.dts | 25 reg = <0x00000000 0x80000000 0 0x10000000>; /* 256M DRAM */
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/linux/Documentation/arch/arm/sa1100/ |
H A D | lart.rst | 6 applications. It has 32 MB DRAM, 4MB Flash ROM, double RS232 and all
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