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Searched refs:DWB_ENABLE_CLK_CTRL (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
H A Ddcn30_dwb.c97 REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, 1); in dwb3_enable()
127 REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, 0); in dwb3_disable()
199 REG_GET(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, &dwb_enabled); in dwb3_is_enabled()
H A Ddcn30_dwb.h31 SR(DWB_ENABLE_CLK_CTRL),\
141 SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DWB_ENABLE, mask_sh),\
142 SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DISPCLK_R_DWB_GATE_DIS, mask_sh),\
143 SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DISPCLK_G_DWB_GATE_DIS, mask_sh),\
144 SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DWB_TEST_CLK_SEL, mask_sh),\
720 uint32_t DWB_ENABLE_CLK_CTRL; member
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn35/
H A Ddcn35_dwb.h36 SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DWB_FGCG_REP_DIS, mask_sh)
H A Ddcn35_dwb.c56 REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_FGCG_REP_DIS, !enable); in dcn35_dwbc_set_fgcg()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h571 SR_ARR(DWB_ENABLE_CLK_CTRL, id), SR_ARR(DWB_MEM_PWR_CTRL, id), \