xref: /linux/include/uapi/drm/exynos_drm.h (revision c0bf499f)
1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
2 /* exynos_drm.h
3  *
4  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5  * Authors:
6  *	Inki Dae <inki.dae@samsung.com>
7  *	Joonyoung Shim <jy0922.shim@samsung.com>
8  *	Seung-Woo Kim <sw0312.kim@samsung.com>
9  *
10  * This program is free software; you can redistribute  it and/or modify it
11  * under  the terms of  the GNU General  Public License as published by the
12  * Free Software Foundation;  either version 2 of the  License, or (at your
13  * option) any later version.
14  */
15 
16 #ifndef _UAPI_EXYNOS_DRM_H_
17 #define _UAPI_EXYNOS_DRM_H_
18 
19 #include "drm.h"
20 
21 #if defined(__cplusplus)
22 extern "C" {
23 #endif
24 
25 /**
26  * User-desired buffer creation information structure.
27  *
28  * @size: user-desired memory allocation size.
29  *	- this size value would be page-aligned internally.
30  * @flags: user request for setting memory type or cache attributes.
31  * @handle: returned a handle to created gem object.
32  *	- this handle will be set by gem module of kernel side.
33  */
34 struct drm_exynos_gem_create {
35 	__u64 size;
36 	__u32 flags;
37 	__u32 handle;
38 };
39 
40 /**
41  * A structure for getting a fake-offset that can be used with mmap.
42  *
43  * @handle: handle of gem object.
44  * @reserved: just padding to be 64-bit aligned.
45  * @offset: a fake-offset of gem object.
46  */
47 struct drm_exynos_gem_map {
48 	__u32 handle;
49 	__u32 reserved;
50 	__u64 offset;
51 };
52 
53 /**
54  * A structure to gem information.
55  *
56  * @handle: a handle to gem object created.
57  * @flags: flag value including memory type and cache attribute and
58  *	this value would be set by driver.
59  * @size: size to memory region allocated by gem and this size would
60  *	be set by driver.
61  */
62 struct drm_exynos_gem_info {
63 	__u32 handle;
64 	__u32 flags;
65 	__u64 size;
66 };
67 
68 /**
69  * A structure for user connection request of virtual display.
70  *
71  * @connection: indicate whether doing connection or not by user.
72  * @extensions: if this value is 1 then the vidi driver would need additional
73  *	128bytes edid data.
74  * @edid: the edid data pointer from user side.
75  */
76 struct drm_exynos_vidi_connection {
77 	__u32 connection;
78 	__u32 extensions;
79 	__u64 edid;
80 };
81 
82 /* memory type definitions. */
83 enum e_drm_exynos_gem_mem_type {
84 	/* Physically Continuous memory and used as default. */
85 	EXYNOS_BO_CONTIG	= 0 << 0,
86 	/* Physically Non-Continuous memory. */
87 	EXYNOS_BO_NONCONTIG	= 1 << 0,
88 	/* non-cachable mapping and used as default. */
89 	EXYNOS_BO_NONCACHABLE	= 0 << 1,
90 	/* cachable mapping. */
91 	EXYNOS_BO_CACHABLE	= 1 << 1,
92 	/* write-combine mapping. */
93 	EXYNOS_BO_WC		= 1 << 2,
94 	EXYNOS_BO_MASK		= EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
95 					EXYNOS_BO_WC
96 };
97 
98 struct drm_exynos_g2d_get_ver {
99 	__u32	major;
100 	__u32	minor;
101 };
102 
103 struct drm_exynos_g2d_cmd {
104 	__u32	offset;
105 	__u32	data;
106 };
107 
108 enum drm_exynos_g2d_buf_type {
109 	G2D_BUF_USERPTR = 1 << 31,
110 };
111 
112 enum drm_exynos_g2d_event_type {
113 	G2D_EVENT_NOT,
114 	G2D_EVENT_NONSTOP,
115 	G2D_EVENT_STOP,		/* not yet */
116 };
117 
118 struct drm_exynos_g2d_userptr {
119 	unsigned long userptr;
120 	unsigned long size;
121 };
122 
123 struct drm_exynos_g2d_set_cmdlist {
124 	__u64					cmd;
125 	__u64					cmd_buf;
126 	__u32					cmd_nr;
127 	__u32					cmd_buf_nr;
128 
129 	/* for g2d event */
130 	__u64					event_type;
131 	__u64					user_data;
132 };
133 
134 struct drm_exynos_g2d_exec {
135 	__u64					async;
136 };
137 
138 /* Exynos DRM IPP v2 API */
139 
140 /**
141  * Enumerate available IPP hardware modules.
142  *
143  * @count_ipps: size of ipp_id array / number of ipp modules (set by driver)
144  * @reserved: padding
145  * @ipp_id_ptr: pointer to ipp_id array or NULL
146  */
147 struct drm_exynos_ioctl_ipp_get_res {
148 	__u32 count_ipps;
149 	__u32 reserved;
150 	__u64 ipp_id_ptr;
151 };
152 
153 enum drm_exynos_ipp_format_type {
154 	DRM_EXYNOS_IPP_FORMAT_SOURCE		= 0x01,
155 	DRM_EXYNOS_IPP_FORMAT_DESTINATION	= 0x02,
156 };
157 
158 struct drm_exynos_ipp_format {
159 	__u32 fourcc;
160 	__u32 type;
161 	__u64 modifier;
162 };
163 
164 enum drm_exynos_ipp_capability {
165 	DRM_EXYNOS_IPP_CAP_CROP		= 0x01,
166 	DRM_EXYNOS_IPP_CAP_ROTATE	= 0x02,
167 	DRM_EXYNOS_IPP_CAP_SCALE	= 0x04,
168 	DRM_EXYNOS_IPP_CAP_CONVERT	= 0x08,
169 };
170 
171 /**
172  * Get IPP hardware capabilities and supported image formats.
173  *
174  * @ipp_id: id of IPP module to query
175  * @capabilities: bitmask of drm_exynos_ipp_capability (set by driver)
176  * @reserved: padding
177  * @formats_count: size of formats array (in entries) / number of filled
178  *		   formats (set by driver)
179  * @formats_ptr: pointer to formats array or NULL
180  */
181 struct drm_exynos_ioctl_ipp_get_caps {
182 	__u32 ipp_id;
183 	__u32 capabilities;
184 	__u32 reserved;
185 	__u32 formats_count;
186 	__u64 formats_ptr;
187 };
188 
189 enum drm_exynos_ipp_limit_type {
190 	/* size (horizontal/vertial) limits, in pixels (min, max, alignment) */
191 	DRM_EXYNOS_IPP_LIMIT_TYPE_SIZE		= 0x0001,
192 	/* scale ratio (horizonta/vertial), 16.16 fixed point (min, max) */
193 	DRM_EXYNOS_IPP_LIMIT_TYPE_SCALE		= 0x0002,
194 
195 	/* image buffer area */
196 	DRM_EXYNOS_IPP_LIMIT_SIZE_BUFFER	= 0x0001 << 16,
197 	/* src/dst rectangle area */
198 	DRM_EXYNOS_IPP_LIMIT_SIZE_AREA		= 0x0002 << 16,
199 	/* src/dst rectangle area when rotation enabled */
200 	DRM_EXYNOS_IPP_LIMIT_SIZE_ROTATED	= 0x0003 << 16,
201 
202 	DRM_EXYNOS_IPP_LIMIT_TYPE_MASK		= 0x000f,
203 	DRM_EXYNOS_IPP_LIMIT_SIZE_MASK		= 0x000f << 16,
204 };
205 
206 struct drm_exynos_ipp_limit_val {
207 	__u32 min;
208 	__u32 max;
209 	__u32 align;
210 	__u32 reserved;
211 };
212 
213 /**
214  * IPP module limitation.
215  *
216  * @type: limit type (see drm_exynos_ipp_limit_type enum)
217  * @reserved: padding
218  * @h: horizontal limits
219  * @v: vertical limits
220  */
221 struct drm_exynos_ipp_limit {
222 	__u32 type;
223 	__u32 reserved;
224 	struct drm_exynos_ipp_limit_val h;
225 	struct drm_exynos_ipp_limit_val v;
226 };
227 
228 /**
229  * Get IPP limits for given image format.
230  *
231  * @ipp_id: id of IPP module to query
232  * @fourcc: image format code (see DRM_FORMAT_* in drm_fourcc.h)
233  * @modifier: image format modifier (see DRM_FORMAT_MOD_* in drm_fourcc.h)
234  * @type: source/destination identifier (drm_exynos_ipp_format_flag enum)
235  * @limits_count: size of limits array (in entries) / number of filled entries
236  *		 (set by driver)
237  * @limits_ptr: pointer to limits array or NULL
238  */
239 struct drm_exynos_ioctl_ipp_get_limits {
240 	__u32 ipp_id;
241 	__u32 fourcc;
242 	__u64 modifier;
243 	__u32 type;
244 	__u32 limits_count;
245 	__u64 limits_ptr;
246 };
247 
248 enum drm_exynos_ipp_task_id {
249 	/* buffer described by struct drm_exynos_ipp_task_buffer */
250 	DRM_EXYNOS_IPP_TASK_BUFFER		= 0x0001,
251 	/* rectangle described by struct drm_exynos_ipp_task_rect */
252 	DRM_EXYNOS_IPP_TASK_RECTANGLE		= 0x0002,
253 	/* transformation described by struct drm_exynos_ipp_task_transform */
254 	DRM_EXYNOS_IPP_TASK_TRANSFORM		= 0x0003,
255 	/* alpha configuration described by struct drm_exynos_ipp_task_alpha */
256 	DRM_EXYNOS_IPP_TASK_ALPHA		= 0x0004,
257 
258 	/* source image data (for buffer and rectangle chunks) */
259 	DRM_EXYNOS_IPP_TASK_TYPE_SOURCE		= 0x0001 << 16,
260 	/* destination image data (for buffer and rectangle chunks) */
261 	DRM_EXYNOS_IPP_TASK_TYPE_DESTINATION	= 0x0002 << 16,
262 };
263 
264 /**
265  * Memory buffer with image data.
266  *
267  * @id: must be DRM_EXYNOS_IPP_TASK_BUFFER
268  * other parameters are same as for AddFB2 generic DRM ioctl
269  */
270 struct drm_exynos_ipp_task_buffer {
271 	__u32	id;
272 	__u32	fourcc;
273 	__u32	width, height;
274 	__u32	gem_id[4];
275 	__u32	offset[4];
276 	__u32	pitch[4];
277 	__u64	modifier;
278 };
279 
280 /**
281  * Rectangle for processing.
282  *
283  * @id: must be DRM_EXYNOS_IPP_TASK_RECTANGLE
284  * @reserved: padding
285  * @x,@y: left corner in pixels
286  * @w,@h: width/height in pixels
287  */
288 struct drm_exynos_ipp_task_rect {
289 	__u32	id;
290 	__u32	reserved;
291 	__u32	x;
292 	__u32	y;
293 	__u32	w;
294 	__u32	h;
295 };
296 
297 /**
298  * Image tranformation description.
299  *
300  * @id: must be DRM_EXYNOS_IPP_TASK_TRANSFORM
301  * @rotation: DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* values
302  */
303 struct drm_exynos_ipp_task_transform {
304 	__u32	id;
305 	__u32	rotation;
306 };
307 
308 /**
309  * Image global alpha configuration for formats without alpha values.
310  *
311  * @id: must be DRM_EXYNOS_IPP_TASK_ALPHA
312  * @value: global alpha value (0-255)
313  */
314 struct drm_exynos_ipp_task_alpha {
315 	__u32	id;
316 	__u32	value;
317 };
318 
319 enum drm_exynos_ipp_flag {
320 	/* generate DRM event after processing */
321 	DRM_EXYNOS_IPP_FLAG_EVENT	= 0x01,
322 	/* dry run, only check task parameters */
323 	DRM_EXYNOS_IPP_FLAG_TEST_ONLY	= 0x02,
324 	/* non-blocking processing */
325 	DRM_EXYNOS_IPP_FLAG_NONBLOCK	= 0x04,
326 };
327 
328 #define DRM_EXYNOS_IPP_FLAGS (DRM_EXYNOS_IPP_FLAG_EVENT |\
329 		DRM_EXYNOS_IPP_FLAG_TEST_ONLY | DRM_EXYNOS_IPP_FLAG_NONBLOCK)
330 
331 /**
332  * Perform image processing described by array of drm_exynos_ipp_task_*
333  * structures (parameters array).
334  *
335  * @ipp_id: id of IPP module to run the task
336  * @flags: bitmask of drm_exynos_ipp_flag values
337  * @reserved: padding
338  * @params_size: size of parameters array (in bytes)
339  * @params_ptr: pointer to parameters array or NULL
340  * @user_data: (optional) data for drm event
341  */
342 struct drm_exynos_ioctl_ipp_commit {
343 	__u32 ipp_id;
344 	__u32 flags;
345 	__u32 reserved;
346 	__u32 params_size;
347 	__u64 params_ptr;
348 	__u64 user_data;
349 };
350 
351 #define DRM_EXYNOS_GEM_CREATE		0x00
352 #define DRM_EXYNOS_GEM_MAP		0x01
353 /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
354 #define DRM_EXYNOS_GEM_GET		0x04
355 #define DRM_EXYNOS_VIDI_CONNECTION	0x07
356 
357 /* G2D */
358 #define DRM_EXYNOS_G2D_GET_VER		0x20
359 #define DRM_EXYNOS_G2D_SET_CMDLIST	0x21
360 #define DRM_EXYNOS_G2D_EXEC		0x22
361 
362 /* Reserved 0x30 ~ 0x33 for obsolete Exynos IPP ioctls */
363 /* IPP - Image Post Processing */
364 #define DRM_EXYNOS_IPP_GET_RESOURCES	0x40
365 #define DRM_EXYNOS_IPP_GET_CAPS		0x41
366 #define DRM_EXYNOS_IPP_GET_LIMITS	0x42
367 #define DRM_EXYNOS_IPP_COMMIT		0x43
368 
369 #define DRM_IOCTL_EXYNOS_GEM_CREATE		DRM_IOWR(DRM_COMMAND_BASE + \
370 		DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
371 #define DRM_IOCTL_EXYNOS_GEM_MAP		DRM_IOWR(DRM_COMMAND_BASE + \
372 		DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map)
373 #define DRM_IOCTL_EXYNOS_GEM_GET	DRM_IOWR(DRM_COMMAND_BASE + \
374 		DRM_EXYNOS_GEM_GET,	struct drm_exynos_gem_info)
375 
376 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION	DRM_IOWR(DRM_COMMAND_BASE + \
377 		DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
378 
379 #define DRM_IOCTL_EXYNOS_G2D_GET_VER		DRM_IOWR(DRM_COMMAND_BASE + \
380 		DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
381 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST	DRM_IOWR(DRM_COMMAND_BASE + \
382 		DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
383 #define DRM_IOCTL_EXYNOS_G2D_EXEC		DRM_IOWR(DRM_COMMAND_BASE + \
384 		DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
385 
386 #define DRM_IOCTL_EXYNOS_IPP_GET_RESOURCES	DRM_IOWR(DRM_COMMAND_BASE + \
387 		DRM_EXYNOS_IPP_GET_RESOURCES, \
388 		struct drm_exynos_ioctl_ipp_get_res)
389 #define DRM_IOCTL_EXYNOS_IPP_GET_CAPS		DRM_IOWR(DRM_COMMAND_BASE + \
390 		DRM_EXYNOS_IPP_GET_CAPS, struct drm_exynos_ioctl_ipp_get_caps)
391 #define DRM_IOCTL_EXYNOS_IPP_GET_LIMITS		DRM_IOWR(DRM_COMMAND_BASE + \
392 		DRM_EXYNOS_IPP_GET_LIMITS, \
393 		struct drm_exynos_ioctl_ipp_get_limits)
394 #define DRM_IOCTL_EXYNOS_IPP_COMMIT		DRM_IOWR(DRM_COMMAND_BASE + \
395 		DRM_EXYNOS_IPP_COMMIT, struct drm_exynos_ioctl_ipp_commit)
396 
397 /* Exynos specific events */
398 #define DRM_EXYNOS_G2D_EVENT		0x80000000
399 #define DRM_EXYNOS_IPP_EVENT		0x80000002
400 
401 struct drm_exynos_g2d_event {
402 	struct drm_event	base;
403 	__u64			user_data;
404 	__u32			tv_sec;
405 	__u32			tv_usec;
406 	__u32			cmdlist_no;
407 	__u32			reserved;
408 };
409 
410 struct drm_exynos_ipp_event {
411 	struct drm_event	base;
412 	__u64			user_data;
413 	__u32			tv_sec;
414 	__u32			tv_usec;
415 	__u32			ipp_id;
416 	__u32			sequence;
417 	__u64			reserved;
418 };
419 
420 #if defined(__cplusplus)
421 }
422 #endif
423 
424 #endif /* _UAPI_EXYNOS_DRM_H_ */
425