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Searched refs:PIPE_CONTROL0_HDC_PIPELINE_FLUSH (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/xe/regs/
H A Dxe_gpu_commands.h44 #define PIPE_CONTROL0_HDC_PIPELINE_FLUSH BIT(9) /* gen12 */ macro
/linux/drivers/gpu/drm/i915/gt/
H A Dgen8_engine_cs.c262 bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH; in gen12_emit_flush_rcs()
842 cs = gen12_emit_pipe_control(cs, PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags, 0); in gen12_emit_fini_breadcrumb_rcs()
H A Dintel_gpu_commands.h309 #define PIPE_CONTROL0_HDC_PIPELINE_FLUSH REG_BIT(9) /* gen12 */ macro
/linux/drivers/gpu/drm/xe/
H A Dxe_ring_ops.c195 return emit_pipe_control(dw, i, PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags, 0, 0); in emit_render_cache_flush()