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Searched refs:RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c2347 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2373 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2374 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2539 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) in gfx_v9_4_3_get_clockgating_state()
H A Dgfx_v9_0.c4707 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; in gfx_v9_0_update_medium_grain_clock_gating()
4736 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { in gfx_v9_0_update_medium_grain_clock_gating()
4737 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; in gfx_v9_0_update_medium_grain_clock_gating()
5053 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) in gfx_v9_0_get_clockgating_state()
H A Dgfx_v7_0.c3617 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { in gfx_v7_0_enable_mgcg()
3618 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; in gfx_v7_0_enable_mgcg()
H A Dgfx_v8_0.c5469 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) in gfx_v8_0_get_clockgating_state()
5688 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { in gfx_v8_0_update_medium_grain_clock_gating()
5689 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; in gfx_v8_0_update_medium_grain_clock_gating()
H A Dgfx_v10_0.c7713 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; in gfx_v10_0_update_medium_grain_clock_gating()
7746 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { in gfx_v10_0_update_medium_grain_clock_gating()
7747 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; in gfx_v10_0_update_medium_grain_clock_gating()
8269 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) in gfx_v10_0_get_clockgating_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7200 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L macro
H A Dgfx_7_2_sh_mask.h7729 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1 macro
H A Dgfx_8_0_sh_mask.h8543 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1 macro
H A Dgfx_8_1_sh_mask.h9095 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h22776 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK … macro
H A Dgc_9_2_1_sh_mask.h24066 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK … macro
H A Dgc_9_1_sh_mask.h24063 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK … macro
H A Dgc_9_4_3_sh_mask.h26325 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK … macro
H A Dgc_9_4_2_sh_mask.h21540 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK … macro
H A Dgc_11_5_0_sh_mask.h31399 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK … macro
H A Dgc_11_0_0_sh_mask.h35841 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK … macro
H A Dgc_11_0_3_sh_mask.h39171 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK … macro
H A Dgc_10_1_0_sh_mask.h33246 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK … macro
H A Dgc_10_3_0_sh_mask.h32167 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK … macro