1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_MAC_H__
6 #define __RTW89_MAC_H__
7
8 #include "core.h"
9 #include "reg.h"
10
11 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000
12 #define ADDR_CAM_ENT_SIZE 0x40
13 #define ADDR_CAM_ENT_SHORT_SIZE 0x20
14 #define BSSID_CAM_ENT_SIZE 0x08
15 #define HFC_PAGE_UNIT 64
16 #define RPWM_TRY_CNT 3
17
18 enum rtw89_mac_hwmod_sel {
19 RTW89_DMAC_SEL = 0,
20 RTW89_CMAC_SEL = 1,
21
22 RTW89_MAC_INVALID,
23 };
24
25 enum rtw89_mac_fwd_target {
26 RTW89_FWD_DONT_CARE = 0,
27 RTW89_FWD_TO_HOST = 1,
28 RTW89_FWD_TO_WLAN_CPU = 2
29 };
30
31 enum rtw89_mac_wd_dma_intvl {
32 RTW89_MAC_WD_DMA_INTVL_0S,
33 RTW89_MAC_WD_DMA_INTVL_256NS,
34 RTW89_MAC_WD_DMA_INTVL_512NS,
35 RTW89_MAC_WD_DMA_INTVL_768NS,
36 RTW89_MAC_WD_DMA_INTVL_1US,
37 RTW89_MAC_WD_DMA_INTVL_1_5US,
38 RTW89_MAC_WD_DMA_INTVL_2US,
39 RTW89_MAC_WD_DMA_INTVL_4US,
40 RTW89_MAC_WD_DMA_INTVL_8US,
41 RTW89_MAC_WD_DMA_INTVL_16US,
42 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
43 };
44
45 enum rtw89_mac_multi_tag_num {
46 RTW89_MAC_TAG_NUM_1,
47 RTW89_MAC_TAG_NUM_2,
48 RTW89_MAC_TAG_NUM_3,
49 RTW89_MAC_TAG_NUM_4,
50 RTW89_MAC_TAG_NUM_5,
51 RTW89_MAC_TAG_NUM_6,
52 RTW89_MAC_TAG_NUM_7,
53 RTW89_MAC_TAG_NUM_8,
54 RTW89_MAC_TAG_NUM_DEF = 0xFE
55 };
56
57 enum rtw89_mac_lbc_tmr {
58 RTW89_MAC_LBC_TMR_8US = 0,
59 RTW89_MAC_LBC_TMR_16US,
60 RTW89_MAC_LBC_TMR_32US,
61 RTW89_MAC_LBC_TMR_64US,
62 RTW89_MAC_LBC_TMR_128US,
63 RTW89_MAC_LBC_TMR_256US,
64 RTW89_MAC_LBC_TMR_512US,
65 RTW89_MAC_LBC_TMR_1MS,
66 RTW89_MAC_LBC_TMR_2MS,
67 RTW89_MAC_LBC_TMR_4MS,
68 RTW89_MAC_LBC_TMR_8MS,
69 RTW89_MAC_LBC_TMR_DEF = 0xFE
70 };
71
72 enum rtw89_mac_cpuio_op_cmd_type {
73 CPUIO_OP_CMD_GET_1ST_PID = 0,
74 CPUIO_OP_CMD_GET_NEXT_PID = 1,
75 CPUIO_OP_CMD_ENQ_TO_TAIL = 4,
76 CPUIO_OP_CMD_ENQ_TO_HEAD = 5,
77 CPUIO_OP_CMD_DEQ = 8,
78 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9,
79 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12
80 };
81
82 enum rtw89_mac_wde_dle_port_id {
83 WDE_DLE_PORT_ID_DISPATCH = 0,
84 WDE_DLE_PORT_ID_PKTIN = 1,
85 WDE_DLE_PORT_ID_CMAC0 = 3,
86 WDE_DLE_PORT_ID_CMAC1 = 4,
87 WDE_DLE_PORT_ID_CPU_IO = 6,
88 WDE_DLE_PORT_ID_WDRLS = 7,
89 WDE_DLE_PORT_ID_END = 8
90 };
91
92 enum rtw89_mac_wde_dle_queid_wdrls {
93 WDE_DLE_QUEID_TXOK = 0,
94 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1,
95 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2,
96 WDE_DLE_QUEID_DROP_MACID_DROP = 3,
97 WDE_DLE_QUEID_NO_REPORT = 4
98 };
99
100 enum rtw89_mac_ple_dle_port_id {
101 PLE_DLE_PORT_ID_DISPATCH = 0,
102 PLE_DLE_PORT_ID_MPDU = 1,
103 PLE_DLE_PORT_ID_SEC = 2,
104 PLE_DLE_PORT_ID_CMAC0 = 3,
105 PLE_DLE_PORT_ID_CMAC1 = 4,
106 PLE_DLE_PORT_ID_WDRLS = 5,
107 PLE_DLE_PORT_ID_CPU_IO = 6,
108 PLE_DLE_PORT_ID_PLRLS = 7,
109 PLE_DLE_PORT_ID_END = 8
110 };
111
112 enum rtw89_mac_ple_dle_queid_plrls {
113 PLE_DLE_QUEID_NO_REPORT = 0x0
114 };
115
116 enum rtw89_machdr_frame_type {
117 RTW89_MGNT = 0,
118 RTW89_CTRL = 1,
119 RTW89_DATA = 2,
120 };
121
122 enum rtw89_mac_dle_dfi_type {
123 DLE_DFI_TYPE_FREEPG = 0,
124 DLE_DFI_TYPE_QUOTA = 1,
125 DLE_DFI_TYPE_PAGELLT = 2,
126 DLE_DFI_TYPE_PKTINFO = 3,
127 DLE_DFI_TYPE_PREPKTLLT = 4,
128 DLE_DFI_TYPE_NXTPKTLLT = 5,
129 DLE_DFI_TYPE_QLNKTBL = 6,
130 DLE_DFI_TYPE_QEMPTY = 7,
131 };
132
133 enum rtw89_mac_dle_wde_quota_id {
134 WDE_QTAID_HOST_IF = 0,
135 WDE_QTAID_WLAN_CPU = 1,
136 WDE_QTAID_DATA_CPU = 2,
137 WDE_QTAID_PKTIN = 3,
138 WDE_QTAID_CPUIO = 4,
139 };
140
141 enum rtw89_mac_dle_ple_quota_id {
142 PLE_QTAID_B0_TXPL = 0,
143 PLE_QTAID_B1_TXPL = 1,
144 PLE_QTAID_C2H = 2,
145 PLE_QTAID_H2C = 3,
146 PLE_QTAID_WLAN_CPU = 4,
147 PLE_QTAID_MPDU = 5,
148 PLE_QTAID_CMAC0_RX = 6,
149 PLE_QTAID_CMAC1_RX = 7,
150 PLE_QTAID_CMAC1_BBRPT = 8,
151 PLE_QTAID_WDRLS = 9,
152 PLE_QTAID_CPUIO = 10,
153 };
154
155 enum rtw89_mac_dle_ctrl_type {
156 DLE_CTRL_TYPE_WDE = 0,
157 DLE_CTRL_TYPE_PLE = 1,
158 DLE_CTRL_TYPE_NUM = 2,
159 };
160
161 enum rtw89_mac_ax_l0_to_l1_event {
162 MAC_AX_L0_TO_L1_CHIF_IDLE = 0,
163 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1,
164 MAC_AX_L0_TO_L1_RLS_PKID = 2,
165 MAC_AX_L0_TO_L1_PTCL_IDLE = 3,
166 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4,
167 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5,
168 MAC_AX_L0_TO_L1_PCIE_STUCK = 6,
169 MAC_AX_L0_TO_L1_EVENT_MAX = 15,
170 };
171
172 enum rtw89_mac_wow_fw_status {
173 WOWLAN_NOT_READY = 0x00,
174 WOWLAN_SLEEP_READY = 0x01,
175 WOWLAN_RESUME_READY = 0x02,
176 };
177
178 #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32)
179
180 enum rtw89_mac_dbg_port_sel {
181 /* CMAC 0 related */
182 RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
183 RTW89_DBG_PORT_SEL_SCH_C0,
184 RTW89_DBG_PORT_SEL_TMAC_C0,
185 RTW89_DBG_PORT_SEL_RMAC_C0,
186 RTW89_DBG_PORT_SEL_RMACST_C0,
187 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0,
188 RTW89_DBG_PORT_SEL_TRXPTCL_C0,
189 RTW89_DBG_PORT_SEL_TX_INFOL_C0,
190 RTW89_DBG_PORT_SEL_TX_INFOH_C0,
191 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0,
192 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0,
193 /* CMAC 1 related */
194 RTW89_DBG_PORT_SEL_PTCL_C1,
195 RTW89_DBG_PORT_SEL_SCH_C1,
196 RTW89_DBG_PORT_SEL_TMAC_C1,
197 RTW89_DBG_PORT_SEL_RMAC_C1,
198 RTW89_DBG_PORT_SEL_RMACST_C1,
199 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1,
200 RTW89_DBG_PORT_SEL_TRXPTCL_C1,
201 RTW89_DBG_PORT_SEL_TX_INFOL_C1,
202 RTW89_DBG_PORT_SEL_TX_INFOH_C1,
203 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1,
204 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1,
205 /* DLE related */
206 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG,
207 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA,
208 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT,
209 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO,
210 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT,
211 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT,
212 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL,
213 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY,
214 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG,
215 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA,
216 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT,
217 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO,
218 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT,
219 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT,
220 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL,
221 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY,
222 RTW89_DBG_PORT_SEL_PKTINFO,
223 /* DISPATCHER related */
224 RTW89_DBG_PORT_SEL_DSPT_HDT_TX0,
225 RTW89_DBG_PORT_SEL_DSPT_HDT_TX1,
226 RTW89_DBG_PORT_SEL_DSPT_HDT_TX2,
227 RTW89_DBG_PORT_SEL_DSPT_HDT_TX3,
228 RTW89_DBG_PORT_SEL_DSPT_HDT_TX4,
229 RTW89_DBG_PORT_SEL_DSPT_HDT_TX5,
230 RTW89_DBG_PORT_SEL_DSPT_HDT_TX6,
231 RTW89_DBG_PORT_SEL_DSPT_HDT_TX7,
232 RTW89_DBG_PORT_SEL_DSPT_HDT_TX8,
233 RTW89_DBG_PORT_SEL_DSPT_HDT_TX9,
234 RTW89_DBG_PORT_SEL_DSPT_HDT_TXA,
235 RTW89_DBG_PORT_SEL_DSPT_HDT_TXB,
236 RTW89_DBG_PORT_SEL_DSPT_HDT_TXC,
237 RTW89_DBG_PORT_SEL_DSPT_HDT_TXD,
238 RTW89_DBG_PORT_SEL_DSPT_HDT_TXE,
239 RTW89_DBG_PORT_SEL_DSPT_HDT_TXF,
240 RTW89_DBG_PORT_SEL_DSPT_CDT_TX0,
241 RTW89_DBG_PORT_SEL_DSPT_CDT_TX1,
242 RTW89_DBG_PORT_SEL_DSPT_CDT_TX3,
243 RTW89_DBG_PORT_SEL_DSPT_CDT_TX4,
244 RTW89_DBG_PORT_SEL_DSPT_CDT_TX5,
245 RTW89_DBG_PORT_SEL_DSPT_CDT_TX6,
246 RTW89_DBG_PORT_SEL_DSPT_CDT_TX7,
247 RTW89_DBG_PORT_SEL_DSPT_CDT_TX8,
248 RTW89_DBG_PORT_SEL_DSPT_CDT_TX9,
249 RTW89_DBG_PORT_SEL_DSPT_CDT_TXA,
250 RTW89_DBG_PORT_SEL_DSPT_CDT_TXB,
251 RTW89_DBG_PORT_SEL_DSPT_CDT_TXC,
252 RTW89_DBG_PORT_SEL_DSPT_HDT_RX0,
253 RTW89_DBG_PORT_SEL_DSPT_HDT_RX1,
254 RTW89_DBG_PORT_SEL_DSPT_HDT_RX2,
255 RTW89_DBG_PORT_SEL_DSPT_HDT_RX3,
256 RTW89_DBG_PORT_SEL_DSPT_HDT_RX4,
257 RTW89_DBG_PORT_SEL_DSPT_HDT_RX5,
258 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0,
259 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0,
260 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1,
261 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2,
262 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1,
263 RTW89_DBG_PORT_SEL_DSPT_STF_CTRL,
264 RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL,
265 RTW89_DBG_PORT_SEL_DSPT_WDE_INTF,
266 RTW89_DBG_PORT_SEL_DSPT_PLE_INTF,
267 RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL,
268 /* PCIE related */
269 RTW89_DBG_PORT_SEL_PCIE_TXDMA,
270 RTW89_DBG_PORT_SEL_PCIE_RXDMA,
271 RTW89_DBG_PORT_SEL_PCIE_CVT,
272 RTW89_DBG_PORT_SEL_PCIE_CXPL,
273 RTW89_DBG_PORT_SEL_PCIE_IO,
274 RTW89_DBG_PORT_SEL_PCIE_MISC,
275 RTW89_DBG_PORT_SEL_PCIE_MISC2,
276
277 /* keep last */
278 RTW89_DBG_PORT_SEL_LAST,
279 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST,
280 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST,
281 };
282
283 /* SRAM mem dump */
284 #define R_AX_INDIR_ACCESS_ENTRY 0x40000
285 #define R_BE_INDIR_ACCESS_ENTRY 0x80000
286
287 #define AXIDMA_BASE_ADDR 0x18006000
288 #define STA_SCHED_BASE_ADDR 0x18808000
289 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000
290 #define SECURITY_CAM_BASE_ADDR 0x18814000
291 #define WOW_CAM_BASE_ADDR 0x18815000
292 #define CMAC_TBL_BASE_ADDR 0x18840000
293 #define ADDR_CAM_BASE_ADDR 0x18850000
294 #define BSSID_CAM_BASE_ADDR 0x18853000
295 #define BA_CAM_BASE_ADDR 0x18854000
296 #define BCN_IE_CAM0_BASE_ADDR 0x18855000
297 #define SHARED_BUF_BASE_ADDR 0x18700000
298 #define DMAC_TBL_BASE_ADDR 0x18800000
299 #define SHCUT_MACHDR_BASE_ADDR 0x18800800
300 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000
301 #define TXD_FIFO_0_BASE_ADDR 0x18856200
302 #define TXD_FIFO_1_BASE_ADDR 0x188A1080
303 #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */
304 #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */
305 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000
306 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
307 #define CPU_LOCAL_BASE_ADDR 0x18003000
308
309 #define WD_PAGE_BASE_ADDR_BE 0x0
310 #define CPU_LOCAL_BASE_ADDR_BE 0x18003000
311 #define AXIDMA_BASE_ADDR_BE 0x18006000
312 #define SHARED_BUF_BASE_ADDR_BE 0x18700000
313 #define DMAC_TBL_BASE_ADDR_BE 0x18800000
314 #define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800
315 #define STA_SCHED_BASE_ADDR_BE 0x18818000
316 #define NAT25_CAM_BASE_ADDR_BE 0x18820000
317 #define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000
318 #define SEC_CAM_BASE_ADDR_BE 0x18824000
319 #define WOW_CAM_BASE_ADDR_BE 0x18828000
320 #define MLD_TBL_BASE_ADDR_BE 0x18829000
321 #define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000
322 #define CMAC_TBL_BASE_ADDR_BE 0x18840000
323 #define ADDR_CAM_BASE_ADDR_BE 0x18850000
324 #define BSSID_CAM_BASE_ADDR_BE 0x18858000
325 #define BA_CAM_BASE_ADDR_BE 0x18859000
326 #define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000
327 #define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000
328 #define TXD_FIFO_0_BASE_ADDR_BE 0x18862000
329 #define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000
330 #define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000
331 #define TXD_FIFO_1_BASE_ADDR_BE 0x18881800
332 #define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000
333
334 #define CCTL_INFO_SIZE 32
335
336 enum rtw89_mac_mem_sel {
337 RTW89_MAC_MEM_AXIDMA,
338 RTW89_MAC_MEM_SHARED_BUF,
339 RTW89_MAC_MEM_DMAC_TBL,
340 RTW89_MAC_MEM_SHCUT_MACHDR,
341 RTW89_MAC_MEM_STA_SCHED,
342 RTW89_MAC_MEM_RXPLD_FLTR_CAM,
343 RTW89_MAC_MEM_SECURITY_CAM,
344 RTW89_MAC_MEM_WOW_CAM,
345 RTW89_MAC_MEM_CMAC_TBL,
346 RTW89_MAC_MEM_ADDR_CAM,
347 RTW89_MAC_MEM_BA_CAM,
348 RTW89_MAC_MEM_BCN_IE_CAM0,
349 RTW89_MAC_MEM_BCN_IE_CAM1,
350 RTW89_MAC_MEM_TXD_FIFO_0,
351 RTW89_MAC_MEM_TXD_FIFO_1,
352 RTW89_MAC_MEM_TXDATA_FIFO_0,
353 RTW89_MAC_MEM_TXDATA_FIFO_1,
354 RTW89_MAC_MEM_CPU_LOCAL,
355 RTW89_MAC_MEM_BSSID_CAM,
356 RTW89_MAC_MEM_TXD_FIFO_0_V1,
357 RTW89_MAC_MEM_TXD_FIFO_1_V1,
358 RTW89_MAC_MEM_WD_PAGE,
359
360 /* keep last */
361 RTW89_MAC_MEM_NUM,
362 };
363
364 enum rtw89_rpwm_req_pwr_state {
365 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0,
366 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1,
367 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2,
368 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3,
369 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4,
370 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5,
371 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6,
372 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7,
373 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX,
374 };
375
376 struct rtw89_pwr_cfg {
377 u16 addr;
378 u8 cv_msk;
379 u8 intf_msk;
380 u8 base:4;
381 u8 cmd:4;
382 u8 msk;
383 u8 val;
384 };
385
386 enum rtw89_mac_c2h_ofld_func {
387 RTW89_MAC_C2H_FUNC_EFUSE_DUMP,
388 RTW89_MAC_C2H_FUNC_READ_RSP,
389 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP,
390 RTW89_MAC_C2H_FUNC_BCN_RESEND,
391 RTW89_MAC_C2H_FUNC_MACID_PAUSE,
392 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6,
393 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9,
394 RTW89_MAC_C2H_FUNC_BCNFLTR_RPT = 0xd,
395 RTW89_MAC_C2H_FUNC_OFLD_MAX,
396 };
397
398 enum rtw89_mac_c2h_info_func {
399 RTW89_MAC_C2H_FUNC_REC_ACK,
400 RTW89_MAC_C2H_FUNC_DONE_ACK,
401 RTW89_MAC_C2H_FUNC_C2H_LOG,
402 RTW89_MAC_C2H_FUNC_BCN_CNT,
403 RTW89_MAC_C2H_FUNC_INFO_MAX,
404 };
405
406 enum rtw89_mac_c2h_mcc_func {
407 RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0,
408 RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1,
409 RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2,
410 RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3,
411
412 NUM_OF_RTW89_MAC_C2H_FUNC_MCC,
413 };
414
415 enum rtw89_mac_c2h_mrc_func {
416 RTW89_MAC_C2H_FUNC_MRC_TSF_RPT = 0,
417 RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT = 1,
418
419 NUM_OF_RTW89_MAC_C2H_FUNC_MRC,
420 };
421
422 enum rtw89_mac_c2h_wow_func {
423 RTW89_MAC_C2H_FUNC_AOAC_REPORT,
424 RTW89_MAC_C2H_FUNC_READ_WOW_CAM,
425
426 NUM_OF_RTW89_MAC_C2H_FUNC_WOW,
427 };
428
429 enum rtw89_mac_c2h_class {
430 RTW89_MAC_C2H_CLASS_INFO = 0x0,
431 RTW89_MAC_C2H_CLASS_OFLD = 0x1,
432 RTW89_MAC_C2H_CLASS_TWT = 0x2,
433 RTW89_MAC_C2H_CLASS_WOW = 0x3,
434 RTW89_MAC_C2H_CLASS_MCC = 0x4,
435 RTW89_MAC_C2H_CLASS_FWDBG = 0x5,
436 RTW89_MAC_C2H_CLASS_MRC = 0xe,
437 RTW89_MAC_C2H_CLASS_MAX,
438 };
439
440 enum rtw89_mac_mcc_status {
441 RTW89_MAC_MCC_ADD_ROLE_OK = 0,
442 RTW89_MAC_MCC_START_GROUP_OK = 1,
443 RTW89_MAC_MCC_STOP_GROUP_OK = 2,
444 RTW89_MAC_MCC_DEL_GROUP_OK = 3,
445 RTW89_MAC_MCC_RESET_GROUP_OK = 4,
446 RTW89_MAC_MCC_SWITCH_CH_OK = 5,
447 RTW89_MAC_MCC_TXNULL0_OK = 6,
448 RTW89_MAC_MCC_TXNULL1_OK = 7,
449
450 RTW89_MAC_MCC_SWITCH_EARLY = 10,
451 RTW89_MAC_MCC_TBTT = 11,
452 RTW89_MAC_MCC_DURATION_START = 12,
453 RTW89_MAC_MCC_DURATION_END = 13,
454
455 RTW89_MAC_MCC_ADD_ROLE_FAIL = 20,
456 RTW89_MAC_MCC_START_GROUP_FAIL = 21,
457 RTW89_MAC_MCC_STOP_GROUP_FAIL = 22,
458 RTW89_MAC_MCC_DEL_GROUP_FAIL = 23,
459 RTW89_MAC_MCC_RESET_GROUP_FAIL = 24,
460 RTW89_MAC_MCC_SWITCH_CH_FAIL = 25,
461 RTW89_MAC_MCC_TXNULL0_FAIL = 26,
462 RTW89_MAC_MCC_TXNULL1_FAIL = 27,
463 };
464
465 enum rtw89_mac_mrc_status {
466 RTW89_MAC_MRC_START_SCH_OK = 0,
467 RTW89_MAC_MRC_STOP_SCH_OK = 1,
468 RTW89_MAC_MRC_DEL_SCH_OK = 2,
469 };
470
471 struct rtw89_mac_ax_coex {
472 #define RTW89_MAC_AX_COEX_RTK_MODE 0
473 #define RTW89_MAC_AX_COEX_CSR_MODE 1
474 u8 pta_mode;
475 #define RTW89_MAC_AX_COEX_INNER 0
476 #define RTW89_MAC_AX_COEX_OUTPUT 1
477 #define RTW89_MAC_AX_COEX_INPUT 2
478 u8 direction;
479 };
480
481 struct rtw89_mac_ax_plt {
482 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0)
483 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1)
484 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2)
485 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3)
486 u8 band;
487 u8 tx;
488 u8 rx;
489 };
490
491 enum rtw89_mac_bf_rrsc_rate {
492 RTW89_MAC_BF_RRSC_6M = 0,
493 RTW89_MAC_BF_RRSC_9M = 1,
494 RTW89_MAC_BF_RRSC_12M,
495 RTW89_MAC_BF_RRSC_18M,
496 RTW89_MAC_BF_RRSC_24M,
497 RTW89_MAC_BF_RRSC_36M,
498 RTW89_MAC_BF_RRSC_48M,
499 RTW89_MAC_BF_RRSC_54M,
500 RTW89_MAC_BF_RRSC_HT_MSC0,
501 RTW89_MAC_BF_RRSC_HT_MSC1,
502 RTW89_MAC_BF_RRSC_HT_MSC2,
503 RTW89_MAC_BF_RRSC_HT_MSC3,
504 RTW89_MAC_BF_RRSC_HT_MSC4,
505 RTW89_MAC_BF_RRSC_HT_MSC5,
506 RTW89_MAC_BF_RRSC_HT_MSC6,
507 RTW89_MAC_BF_RRSC_HT_MSC7,
508 RTW89_MAC_BF_RRSC_VHT_MSC0,
509 RTW89_MAC_BF_RRSC_VHT_MSC1,
510 RTW89_MAC_BF_RRSC_VHT_MSC2,
511 RTW89_MAC_BF_RRSC_VHT_MSC3,
512 RTW89_MAC_BF_RRSC_VHT_MSC4,
513 RTW89_MAC_BF_RRSC_VHT_MSC5,
514 RTW89_MAC_BF_RRSC_VHT_MSC6,
515 RTW89_MAC_BF_RRSC_VHT_MSC7,
516 RTW89_MAC_BF_RRSC_HE_MSC0,
517 RTW89_MAC_BF_RRSC_HE_MSC1,
518 RTW89_MAC_BF_RRSC_HE_MSC2,
519 RTW89_MAC_BF_RRSC_HE_MSC3,
520 RTW89_MAC_BF_RRSC_HE_MSC4,
521 RTW89_MAC_BF_RRSC_HE_MSC5,
522 RTW89_MAC_BF_RRSC_HE_MSC6,
523 RTW89_MAC_BF_RRSC_HE_MSC7 = 31,
524 RTW89_MAC_BF_RRSC_MAX = 32
525 };
526
527 #define RTW89_R32_EA 0xEAEAEAEA
528 #define RTW89_R32_DEAD 0xDEADBEEF
529 #define MAC_REG_POOL_COUNT 10
530 #define ACCESS_CMAC(_addr) \
531 ({typeof(_addr) __addr = (_addr); \
532 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; })
533 #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000
534 #define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000
535
536 #define PTCL_IDLE_POLL_CNT 10000
537 #define SW_CVR_DUR_US 8
538 #define SW_CVR_CNT 8
539
540 #define DLE_BOUND_UNIT (8 * 1024)
541 #define DLE_WAIT_CNT 2000
542 #define TRXCFG_WAIT_CNT 2000
543
544 #define RTW89_WDE_PG_64 64
545 #define RTW89_WDE_PG_128 128
546 #define RTW89_WDE_PG_256 256
547
548 #define S_AX_WDE_PAGE_SEL_64 0
549 #define S_AX_WDE_PAGE_SEL_128 1
550 #define S_AX_WDE_PAGE_SEL_256 2
551
552 #define RTW89_PLE_PG_64 64
553 #define RTW89_PLE_PG_128 128
554 #define RTW89_PLE_PG_256 256
555
556 #define S_AX_PLE_PAGE_SEL_64 0
557 #define S_AX_PLE_PAGE_SEL_128 1
558 #define S_AX_PLE_PAGE_SEL_256 2
559
560 #define B_CMAC0_MGQ_NORMAL BIT(2)
561 #define B_CMAC0_MGQ_NO_PWRSAV BIT(3)
562 #define B_CMAC0_CPUMGQ BIT(4)
563 #define B_CMAC1_MGQ_NORMAL BIT(10)
564 #define B_CMAC1_MGQ_NO_PWRSAV BIT(11)
565 #define B_CMAC1_CPUMGQ BIT(12)
566
567 #define B_CMAC0_MGQ_NORMAL_BE BIT(2)
568 #define B_CMAC1_MGQ_NORMAL_BE BIT(30)
569
570 #define QEMP_ACQ_GRP_MACID_NUM 8
571 #define QEMP_ACQ_GRP_QSEL_SH 4
572 #define QEMP_ACQ_GRP_QSEL_MASK 0xF
573
574 #define SDIO_LOCAL_BASE_ADDR 0x80000000
575
576 #define PWR_CMD_WRITE 0
577 #define PWR_CMD_POLL 1
578 #define PWR_CMD_DELAY 2
579 #define PWR_CMD_END 3
580
581 #define PWR_INTF_MSK_SDIO BIT(0)
582 #define PWR_INTF_MSK_USB BIT(1)
583 #define PWR_INTF_MSK_PCIE BIT(2)
584 #define PWR_INTF_MSK_ALL 0x7
585
586 #define PWR_BASE_MAC 0
587 #define PWR_BASE_USB 1
588 #define PWR_BASE_PCIE 2
589 #define PWR_BASE_SDIO 3
590
591 #define PWR_CV_MSK_A BIT(0)
592 #define PWR_CV_MSK_B BIT(1)
593 #define PWR_CV_MSK_C BIT(2)
594 #define PWR_CV_MSK_D BIT(3)
595 #define PWR_CV_MSK_E BIT(4)
596 #define PWR_CV_MSK_F BIT(5)
597 #define PWR_CV_MSK_G BIT(6)
598 #define PWR_CV_MSK_TEST BIT(7)
599 #define PWR_CV_MSK_ALL 0xFF
600
601 #define PWR_DELAY_US 0
602 #define PWR_DELAY_MS 1
603
604 /* STA scheduler */
605 #define SS_MACID_SH 8
606 #define SS_TX_LEN_MSK 0x1FFFFF
607 #define SS_CTRL1_R_TX_LEN 5
608 #define SS_CTRL1_R_NEXT_LINK 20
609 #define SS_LINK_SIZE 256
610
611 /* MAC debug port */
612 #define TMAC_DBG_SEL_C0 0xA5
613 #define RMAC_DBG_SEL_C0 0xA6
614 #define TRXPTCL_DBG_SEL_C0 0xA7
615 #define TMAC_DBG_SEL_C1 0xB5
616 #define RMAC_DBG_SEL_C1 0xB6
617 #define TRXPTCL_DBG_SEL_C1 0xB7
618 #define FW_PROG_CNTR_DBG_SEL 0xF2
619 #define PCIE_TXDMA_DBG_SEL 0x30
620 #define PCIE_RXDMA_DBG_SEL 0x31
621 #define PCIE_CVT_DBG_SEL 0x32
622 #define PCIE_CXPL_DBG_SEL 0x33
623 #define PCIE_IO_DBG_SEL 0x37
624 #define PCIE_MISC_DBG_SEL 0x38
625 #define PCIE_MISC2_DBG_SEL 0x00
626 #define MAC_DBG_SEL 1
627 #define RMAC_CMAC_DBG_SEL 1
628
629 /* TRXPTCL dbg port sel */
630 #define TRXPTRL_DBG_SEL_TMAC 0
631 #define TRXPTRL_DBG_SEL_RMAC 1
632
633 struct rtw89_cpuio_ctrl {
634 u16 pkt_num;
635 u16 start_pktid;
636 u16 end_pktid;
637 u8 cmd_type;
638 u8 macid;
639 u8 src_pid;
640 u8 src_qid;
641 u8 dst_pid;
642 u8 dst_qid;
643 u16 pktid;
644 };
645
646 struct rtw89_mac_dbg_port_info {
647 u32 sel_addr;
648 u8 sel_byte;
649 u32 sel_msk;
650 u32 srt;
651 u32 end;
652 u32 rd_addr;
653 u8 rd_byte;
654 u32 rd_msk;
655 };
656
657 #define QLNKTBL_ADDR_INFO_SEL BIT(0)
658 #define QLNKTBL_ADDR_INFO_SEL_0 0
659 #define QLNKTBL_ADDR_INFO_SEL_1 1
660 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1)
661 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0)
662
663 struct rtw89_mac_dle_dfi_ctrl {
664 enum rtw89_mac_dle_ctrl_type type;
665 u32 target;
666 u32 addr;
667 u32 out_data;
668 };
669
670 struct rtw89_mac_dle_dfi_quota {
671 enum rtw89_mac_dle_ctrl_type dle_type;
672 u32 qtaid;
673 u16 rsv_pgnum;
674 u16 use_pgnum;
675 };
676
677 struct rtw89_mac_dle_dfi_qempty {
678 enum rtw89_mac_dle_ctrl_type dle_type;
679 u32 grpsel;
680 u32 qempty;
681 };
682
683 enum rtw89_mac_dle_rsvd_qt_type {
684 DLE_RSVD_QT_MPDU_INFO,
685 DLE_RSVD_QT_B0_CSI,
686 DLE_RSVD_QT_B1_CSI,
687 DLE_RSVD_QT_B0_LMR,
688 DLE_RSVD_QT_B1_LMR,
689 DLE_RSVD_QT_B0_FTM,
690 DLE_RSVD_QT_B1_FTM,
691 };
692
693 struct rtw89_mac_dle_rsvd_qt_cfg {
694 u16 pktid;
695 u16 pg_num;
696 u32 size;
697 };
698
699 enum rtw89_mac_error_scenario {
700 RTW89_RXI300_ERROR = 1,
701 RTW89_WCPU_CPU_EXCEPTION = 2,
702 RTW89_WCPU_ASSERTION = 3,
703 };
704
705 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28)
706
707 /* Define DBG and recovery enum */
708 enum mac_ax_err_info {
709 /* Get error info */
710
711 /* L0 */
712 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,
713 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,
714 MAC_AX_ERR_L0_RESET_DONE = 0x0003,
715 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
716
717 /* L1 */
718 MAC_AX_ERR_L1_PREERR_DMAC = 0x999,
719 MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
720 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
721 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
722 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,
723 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,
724
725 /* L2 */
726 /* address hole (master) */
727 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,
728 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,
729 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,
730 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,
731 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,
732 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,
733 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,
734 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,
735
736 /* AHB bridge timeout (master) */
737 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,
738 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,
739 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,
740 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,
741 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,
742 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,
743 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,
744 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,
745
746 /* APB_SA bridge timeout (master + slave) */
747 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,
748 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,
749 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,
750 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,
751 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,
752 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,
753 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,
754 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,
755 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,
756 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,
757 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,
758 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,
759 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,
760 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,
761 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,
762 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,
763 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,
764 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,
765 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,
766 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,
767 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,
768 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,
769 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,
770 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,
771 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,
772 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,
773 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,
774 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,
775 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,
776 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,
777 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,
778 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,
779 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,
780 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,
781 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,
782 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,
783 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,
784 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,
785 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,
786 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,
787 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,
788 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,
789 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,
790 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,
791 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,
792 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,
793 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,
794 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,
795 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,
796 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,
797 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,
798 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,
799 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,
800 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,
801 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,
802 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,
803 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,
804 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,
805 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,
806 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,
807 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,
808 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,
809 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,
810 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,
811 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,
812 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,
813 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,
814 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,
815 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,
816 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,
817 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,
818 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,
819 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,
820 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,
821 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,
822 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,
823 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,
824 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,
825 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,
826 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,
827 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,
828 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,
829 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,
830 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,
831 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,
832 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,
833 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,
834
835 /* APB_BBRF bridge timeout (master) */
836 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,
837 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,
838 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,
839 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,
840 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,
841 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,
842 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
843 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
844 MAC_AX_ERR_L2_RESET_DONE = 0x2400,
845 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599,
846 MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
847 MAC_AX_ERR_ASSERTION = 0x4000,
848 MAC_AX_ERR_RXI300 = 0x5000,
849 MAC_AX_GET_ERR_MAX,
850 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,
851
852 /* set error info */
853 MAC_AX_ERR_L1_DISABLE_EN = 0x0001,
854 MAC_AX_ERR_L1_RCVY_EN = 0x0002,
855 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
856 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
857 MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A,
858 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
859 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
860 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
861 MAC_AX_ERR_L0_RCVY_EN = 0x0013,
862 MAC_AX_SET_ERR_MAX,
863 };
864
865 struct rtw89_mac_size_set {
866 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie;
867 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c0;
868 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c2;
869 const struct rtw89_dle_size wde_size0;
870 const struct rtw89_dle_size wde_size0_v1;
871 const struct rtw89_dle_size wde_size4;
872 const struct rtw89_dle_size wde_size4_v1;
873 const struct rtw89_dle_size wde_size6;
874 const struct rtw89_dle_size wde_size7;
875 const struct rtw89_dle_size wde_size9;
876 const struct rtw89_dle_size wde_size18;
877 const struct rtw89_dle_size wde_size19;
878 const struct rtw89_dle_size ple_size0;
879 const struct rtw89_dle_size ple_size0_v1;
880 const struct rtw89_dle_size ple_size3_v1;
881 const struct rtw89_dle_size ple_size4;
882 const struct rtw89_dle_size ple_size6;
883 const struct rtw89_dle_size ple_size8;
884 const struct rtw89_dle_size ple_size18;
885 const struct rtw89_dle_size ple_size19;
886 const struct rtw89_wde_quota wde_qt0;
887 const struct rtw89_wde_quota wde_qt0_v1;
888 const struct rtw89_wde_quota wde_qt4;
889 const struct rtw89_wde_quota wde_qt6;
890 const struct rtw89_wde_quota wde_qt7;
891 const struct rtw89_wde_quota wde_qt17;
892 const struct rtw89_wde_quota wde_qt18;
893 const struct rtw89_ple_quota ple_qt0;
894 const struct rtw89_ple_quota ple_qt1;
895 const struct rtw89_ple_quota ple_qt4;
896 const struct rtw89_ple_quota ple_qt5;
897 const struct rtw89_ple_quota ple_qt9;
898 const struct rtw89_ple_quota ple_qt13;
899 const struct rtw89_ple_quota ple_qt18;
900 const struct rtw89_ple_quota ple_qt44;
901 const struct rtw89_ple_quota ple_qt45;
902 const struct rtw89_ple_quota ple_qt46;
903 const struct rtw89_ple_quota ple_qt47;
904 const struct rtw89_ple_quota ple_qt58;
905 const struct rtw89_ple_quota ple_qt_52a_wow;
906 const struct rtw89_ple_quota ple_qt_52b_wow;
907 const struct rtw89_ple_quota ple_qt_51b_wow;
908 const struct rtw89_rsvd_quota ple_rsvd_qt0;
909 const struct rtw89_rsvd_quota ple_rsvd_qt1;
910 const struct rtw89_dle_rsvd_size rsvd0_size0;
911 const struct rtw89_dle_rsvd_size rsvd1_size0;
912 };
913
914 extern const struct rtw89_mac_size_set rtw89_mac_size;
915
916 struct rtw89_mac_gen_def {
917 u32 band1_offset;
918 u32 filter_model_addr;
919 u32 indir_access_addr;
920 const u32 *mem_base_addrs;
921 u32 rx_fltr;
922 const struct rtw89_port_reg *port_base;
923 u32 agg_len_ht;
924 u32 ps_status;
925
926 struct rtw89_reg_def muedca_ctrl;
927 struct rtw89_reg_def bfee_ctrl;
928 struct rtw89_reg_def narrow_bw_ru_dis;
929 struct rtw89_reg_def wow_ctrl;
930
931 int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band,
932 enum rtw89_mac_hwmod_sel sel);
933 int (*sys_init)(struct rtw89_dev *rtwdev);
934 int (*trx_init)(struct rtw89_dev *rtwdev);
935 void (*hci_func_en)(struct rtw89_dev *rtwdev);
936 void (*dmac_func_pre_en)(struct rtw89_dev *rtwdev);
937 void (*dle_func_en)(struct rtw89_dev *rtwdev, bool enable);
938 void (*dle_clk_en)(struct rtw89_dev *rtwdev, bool enable);
939 void (*bf_assoc)(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
940 struct ieee80211_sta *sta);
941
942 int (*typ_fltr_opt)(struct rtw89_dev *rtwdev,
943 enum rtw89_machdr_frame_type type,
944 enum rtw89_mac_fwd_target fwd_target,
945 u8 mac_idx);
946 int (*cfg_ppdu_status)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
947
948 int (*dle_mix_cfg)(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg);
949 int (*chk_dle_rdy)(struct rtw89_dev *rtwdev, bool wde_or_ple);
950 int (*dle_buf_req)(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id);
951 void (*hfc_func_en)(struct rtw89_dev *rtwdev, bool en, bool h2c_en);
952 void (*hfc_h2c_cfg)(struct rtw89_dev *rtwdev);
953 void (*hfc_mix_cfg)(struct rtw89_dev *rtwdev);
954 void (*hfc_get_mix_info)(struct rtw89_dev *rtwdev);
955 void (*wde_quota_cfg)(struct rtw89_dev *rtwdev,
956 const struct rtw89_wde_quota *min_cfg,
957 const struct rtw89_wde_quota *max_cfg,
958 u16 ext_wde_min_qt_wcpu);
959 void (*ple_quota_cfg)(struct rtw89_dev *rtwdev,
960 const struct rtw89_ple_quota *min_cfg,
961 const struct rtw89_ple_quota *max_cfg);
962 int (*set_cpuio)(struct rtw89_dev *rtwdev,
963 struct rtw89_cpuio_ctrl *ctrl_para, bool wd);
964 int (*dle_quota_change)(struct rtw89_dev *rtwdev, bool band1_en);
965
966 void (*disable_cpu)(struct rtw89_dev *rtwdev);
967 int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason,
968 bool dlfw, bool include_bb);
969 u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
970 int (*fwdl_check_path_ready)(struct rtw89_dev *rtwdev, bool h2c_or_fwdl);
971 int (*parse_efuse_map)(struct rtw89_dev *rtwdev);
972 int (*parse_phycap_map)(struct rtw89_dev *rtwdev);
973 int (*cnv_efuse_state)(struct rtw89_dev *rtwdev, bool idle);
974
975 int (*cfg_plt)(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt);
976 u16 (*get_plt_cnt)(struct rtw89_dev *rtwdev, u8 band);
977
978 bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev,
979 enum rtw89_phy_idx phy_idx,
980 u32 reg_base, u32 *cr);
981
982 int (*write_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask);
983 int (*read_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 *val);
984
985 void (*dump_qta_lost)(struct rtw89_dev *rtwdev);
986 void (*dump_err_status)(struct rtw89_dev *rtwdev,
987 enum mac_ax_err_info err);
988
989 bool (*is_txq_empty)(struct rtw89_dev *rtwdev);
990
991 int (*add_chan_list)(struct rtw89_dev *rtwdev,
992 struct rtw89_vif *rtwvif, bool connected);
993 int (*scan_offload)(struct rtw89_dev *rtwdev,
994 struct rtw89_scan_option *option,
995 struct rtw89_vif *rtwvif);
996
997 int (*wow_config_mac)(struct rtw89_dev *rtwdev, bool enable_wow);
998 };
999
1000 extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax;
1001 extern const struct rtw89_mac_gen_def rtw89_mac_gen_be;
1002
1003 static inline
rtw89_mac_reg_by_idx(struct rtw89_dev * rtwdev,u32 reg_base,u8 band)1004 u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band)
1005 {
1006 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1007
1008 return band == 0 ? reg_base : (reg_base + mac->band1_offset);
1009 }
1010
1011 static inline
rtw89_mac_reg_by_port(struct rtw89_dev * rtwdev,u32 base,u8 port,u8 mac_idx)1012 u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx)
1013 {
1014 return rtw89_mac_reg_by_idx(rtwdev, base + port * 0x40, mac_idx);
1015 }
1016
1017 static inline u32
rtw89_read32_port(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base)1018 rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base)
1019 {
1020 u32 reg;
1021
1022 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1023 return rtw89_read32(rtwdev, reg);
1024 }
1025
1026 static inline u32
rtw89_read32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask)1027 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1028 u32 base, u32 mask)
1029 {
1030 u32 reg;
1031
1032 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1033 return rtw89_read32_mask(rtwdev, reg, mask);
1034 }
1035
1036 static inline void
rtw89_write32_port(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 data)1037 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base,
1038 u32 data)
1039 {
1040 u32 reg;
1041
1042 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1043 rtw89_write32(rtwdev, reg, data);
1044 }
1045
1046 static inline void
rtw89_write32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask,u32 data)1047 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1048 u32 base, u32 mask, u32 data)
1049 {
1050 u32 reg;
1051
1052 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1053 rtw89_write32_mask(rtwdev, reg, mask, data);
1054 }
1055
1056 static inline void
rtw89_write16_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask,u16 data)1057 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1058 u32 base, u32 mask, u16 data)
1059 {
1060 u32 reg;
1061
1062 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1063 rtw89_write16_mask(rtwdev, reg, mask, data);
1064 }
1065
1066 static inline void
rtw89_write32_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 bit)1067 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1068 u32 base, u32 bit)
1069 {
1070 u32 reg;
1071
1072 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1073 rtw89_write32_clr(rtwdev, reg, bit);
1074 }
1075
1076 static inline void
rtw89_write16_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u16 bit)1077 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1078 u32 base, u16 bit)
1079 {
1080 u32 reg;
1081
1082 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1083 rtw89_write16_clr(rtwdev, reg, bit);
1084 }
1085
1086 static inline void
rtw89_write32_port_set(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 bit)1087 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1088 u32 base, u32 bit)
1089 {
1090 u32 reg;
1091
1092 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1093 rtw89_write32_set(rtwdev, reg, bit);
1094 }
1095
1096 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev);
1097 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb);
1098 int rtw89_mac_init(struct rtw89_dev *rtwdev);
1099 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1100 enum rtw89_qta_mode ext_mode);
1101 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en);
1102 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
1103 enum rtw89_qta_mode mode);
1104 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode);
1105 static inline
rtw89_mac_check_mac_en(struct rtw89_dev * rtwdev,u8 band,enum rtw89_mac_hwmod_sel sel)1106 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band,
1107 enum rtw89_mac_hwmod_sel sel)
1108 {
1109 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1110
1111 return mac->check_mac_en(rtwdev, band, sel);
1112 }
1113
1114 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val);
1115 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val);
1116 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl);
1117 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev,
1118 struct rtw89_mac_dle_dfi_quota *quota);
1119 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev);
1120 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev,
1121 struct rtw89_mac_dle_dfi_qempty *qempty);
1122 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev,
1123 enum mac_ax_err_info err);
1124 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
1125 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1126 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev,
1127 struct rtw89_vif *rtwvif,
1128 struct rtw89_vif *rtwvif_src,
1129 u16 offset_tu);
1130 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1131 u64 *tsf);
1132 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev,
1133 struct rtw89_vif *rtwvif, bool en);
1134 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
1135 struct ieee80211_vif *vif);
1136 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1137 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en);
1138 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
1139 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
1140 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
1141
rtw89_chip_enable_bb_rf(struct rtw89_dev * rtwdev)1142 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev)
1143 {
1144 const struct rtw89_chip_info *chip = rtwdev->chip;
1145
1146 return chip->ops->enable_bb_rf(rtwdev);
1147 }
1148
rtw89_chip_disable_bb_rf(struct rtw89_dev * rtwdev)1149 static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)
1150 {
1151 const struct rtw89_chip_info *chip = rtwdev->chip;
1152
1153 return chip->ops->disable_bb_rf(rtwdev);
1154 }
1155
rtw89_chip_reset_bb_rf(struct rtw89_dev * rtwdev)1156 static inline int rtw89_chip_reset_bb_rf(struct rtw89_dev *rtwdev)
1157 {
1158 int ret;
1159
1160 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
1161 return 0;
1162
1163 ret = rtw89_chip_disable_bb_rf(rtwdev);
1164 if (ret)
1165 return ret;
1166 ret = rtw89_chip_enable_bb_rf(rtwdev);
1167 if (ret)
1168 return ret;
1169
1170 return 0;
1171 }
1172
1173 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
1174 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err);
1175 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
1176 u8 class, u8 func);
1177 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1178 u32 len, u8 class, u8 func);
1179 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev);
1180 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
1181 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1182 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
1183 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1184 int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx,
1185 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1186 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1187 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1188 int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1189
1190 static inline
rtw89_mac_cfg_ppdu_status(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)1191 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
1192 {
1193 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1194
1195 return mac->cfg_ppdu_status(rtwdev, mac_idx, enable);
1196 }
1197
1198 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx);
1199 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
1200 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex);
1201 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
1202 const struct rtw89_mac_ax_coex *coex);
1203 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
1204 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1205 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
1206 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1207 int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev,
1208 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1209
1210 static inline
rtw89_mac_cfg_plt(struct rtw89_dev * rtwdev,struct rtw89_mac_ax_plt * plt)1211 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)
1212 {
1213 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1214
1215 return mac->cfg_plt(rtwdev, plt);
1216 }
1217
1218 static inline
rtw89_mac_get_plt_cnt(struct rtw89_dev * rtwdev,u8 band)1219 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band)
1220 {
1221 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1222
1223 return mac->get_plt_cnt(rtwdev, band);
1224 }
1225
1226 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val);
1227 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev);
1228 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev);
1229 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl);
1230 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl);
1231 int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl);
1232 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter);
1233 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev);
1234
1235 static inline
rtw89_mac_bf_assoc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1236 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1237 struct ieee80211_sta *sta)
1238 {
1239 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1240
1241 if (mac->bf_assoc)
1242 mac->bf_assoc(rtwdev, vif, sta);
1243 }
1244
1245 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1246 struct ieee80211_sta *sta);
1247 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1248 struct ieee80211_bss_conf *conf);
1249 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
1250 struct ieee80211_sta *sta, bool disconnect);
1251 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev);
1252 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en);
1253 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1254 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1255 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
1256 struct rtw89_vif *rtwvif, bool en);
1257 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause);
1258
rtw89_mac_bf_monitor_track(struct rtw89_dev * rtwdev)1259 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
1260 {
1261 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
1262 return;
1263
1264 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags))
1265 return;
1266
1267 _rtw89_mac_bf_monitor_track(rtwdev);
1268 }
1269
rtw89_mac_txpwr_read32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * val)1270 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev,
1271 enum rtw89_phy_idx phy_idx,
1272 u32 reg_base, u32 *val)
1273 {
1274 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1275 u32 cr;
1276
1277 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1278 return -EINVAL;
1279
1280 *val = rtw89_read32(rtwdev, cr);
1281 return 0;
1282 }
1283
rtw89_mac_txpwr_write32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 val)1284 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev,
1285 enum rtw89_phy_idx phy_idx,
1286 u32 reg_base, u32 val)
1287 {
1288 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1289 u32 cr;
1290
1291 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1292 return -EINVAL;
1293
1294 rtw89_write32(rtwdev, cr, val);
1295 return 0;
1296 }
1297
rtw89_mac_txpwr_write32_mask(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 mask,u32 val)1298 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev,
1299 enum rtw89_phy_idx phy_idx,
1300 u32 reg_base, u32 mask, u32 val)
1301 {
1302 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1303 u32 cr;
1304
1305 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1306 return -EINVAL;
1307
1308 rtw89_write32_mask(rtwdev, cr, mask, val);
1309 return 0;
1310 }
1311
rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev * rtwdev,bool enable)1312 static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev,
1313 bool enable)
1314 {
1315 const struct rtw89_chip_info *chip = rtwdev->chip;
1316
1317 if (enable)
1318 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1319 B_AX_HCI_TXDMA_EN);
1320 else
1321 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1322 B_AX_HCI_TXDMA_EN);
1323 }
1324
rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev * rtwdev,bool enable)1325 static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev,
1326 bool enable)
1327 {
1328 const struct rtw89_chip_info *chip = rtwdev->chip;
1329
1330 if (enable)
1331 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1332 B_AX_HCI_RXDMA_EN);
1333 else
1334 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1335 B_AX_HCI_RXDMA_EN);
1336 }
1337
rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev * rtwdev,bool enable)1338 static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev,
1339 bool enable)
1340 {
1341 const struct rtw89_chip_info *chip = rtwdev->chip;
1342
1343 if (enable)
1344 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1345 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
1346 else
1347 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1348 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
1349 }
1350
rtw89_mac_get_power_state(struct rtw89_dev * rtwdev)1351 static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev)
1352 {
1353 u32 val;
1354
1355 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE,
1356 B_AX_WLMAC_PWR_STE_MASK);
1357
1358 return !!val;
1359 }
1360
1361 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
1362 bool resume, u32 tx_time);
1363 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
1364 u32 *tx_time);
1365 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
1366 struct rtw89_sta *rtwsta,
1367 bool resume, u8 tx_retry);
1368 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
1369 struct rtw89_sta *rtwsta, u8 *tx_retry);
1370
1371 enum rtw89_mac_xtal_si_offset {
1372 XTAL0 = 0x0,
1373 XTAL3 = 0x3,
1374 XTAL_SI_XTAL_SC_XI = 0x04,
1375 #define XTAL_SC_XI_MASK GENMASK(7, 0)
1376 XTAL_SI_XTAL_SC_XO = 0x05,
1377 #define XTAL_SC_XO_MASK GENMASK(7, 0)
1378 XTAL_SI_XREF_MODE = 0x0B,
1379 XTAL_SI_PWR_CUT = 0x10,
1380 #define XTAL_SI_SMALL_PWR_CUT BIT(0)
1381 #define XTAL_SI_BIG_PWR_CUT BIT(1)
1382 XTAL_SI_XTAL_DRV = 0x15,
1383 #define XTAL_SI_DRV_LATCH BIT(4)
1384 XTAL_SI_XTAL_PLL = 0x16,
1385 XTAL_SI_XTAL_XMD_2 = 0x24,
1386 #define XTAL_SI_LDO_LPS GENMASK(6, 4)
1387 XTAL_SI_XTAL_XMD_4 = 0x26,
1388 #define XTAL_SI_LPS_CAP GENMASK(3, 0)
1389 XTAL_SI_XREF_RF1 = 0x2D,
1390 XTAL_SI_XREF_RF2 = 0x2E,
1391 XTAL_SI_CV = 0x41,
1392 #define XTAL_SI_ACV_MASK GENMASK(3, 0)
1393 XTAL_SI_LOW_ADDR = 0x62,
1394 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0)
1395 XTAL_SI_CTRL = 0x63,
1396 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6)
1397 #define XTAL_SI_RDY BIT(5)
1398 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0)
1399 XTAL_SI_READ_VAL = 0x7A,
1400 XTAL_SI_WL_RFC_S0 = 0x80,
1401 #define XTAL_SI_RF00S_EN GENMASK(2, 0)
1402 #define XTAL_SI_RF00 BIT(0)
1403 XTAL_SI_WL_RFC_S1 = 0x81,
1404 #define XTAL_SI_RF10S_EN GENMASK(2, 0)
1405 #define XTAL_SI_RF10 BIT(0)
1406 XTAL_SI_ANAPAR_WL = 0x90,
1407 #define XTAL_SI_SRAM2RFC BIT(7)
1408 #define XTAL_SI_GND_SHDN_WL BIT(6)
1409 #define XTAL_SI_SHDN_WL BIT(5)
1410 #define XTAL_SI_RFC2RF BIT(4)
1411 #define XTAL_SI_OFF_EI BIT(3)
1412 #define XTAL_SI_OFF_WEI BIT(2)
1413 #define XTAL_SI_PON_EI BIT(1)
1414 #define XTAL_SI_PON_WEI BIT(0)
1415 XTAL_SI_SRAM_CTRL = 0xA1,
1416 #define XTAL_SI_SRAM_DIS BIT(1)
1417 #define FULL_BIT_MASK GENMASK(7, 0)
1418 XTAL_SI_APBT = 0xD1,
1419 XTAL_SI_PLL = 0xE0,
1420 XTAL_SI_PLL_1 = 0xE1,
1421 };
1422
1423 static inline
rtw89_mac_write_xtal_si(struct rtw89_dev * rtwdev,u8 offset,u8 val,u8 mask)1424 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
1425 {
1426 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1427
1428 return mac->write_xtal_si(rtwdev, offset, val, mask);
1429 }
1430
1431 static inline
rtw89_mac_read_xtal_si(struct rtw89_dev * rtwdev,u8 offset,u8 * val)1432 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
1433 {
1434 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1435
1436 return mac->read_xtal_si(rtwdev, offset, val);
1437 }
1438
1439 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1440 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow);
1441 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
1442 enum rtw89_mac_idx band);
1443 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow);
1444 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1445 bool band1_en);
1446 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev,
1447 enum rtw89_mac_dle_rsvd_qt_type type,
1448 struct rtw89_mac_dle_rsvd_qt_cfg *cfg);
1449
1450 #endif
1451