xref: /linux/arch/x86/include/asm/processor.h (revision 6c09e3b4)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PROCESSOR_H
3 #define _ASM_X86_PROCESSOR_H
4 
5 #include <asm/processor-flags.h>
6 
7 /* Forward declaration, a strange C thing */
8 struct task_struct;
9 struct mm_struct;
10 struct io_bitmap;
11 struct vm86;
12 
13 #include <asm/math_emu.h>
14 #include <asm/segment.h>
15 #include <asm/types.h>
16 #include <uapi/asm/sigcontext.h>
17 #include <asm/current.h>
18 #include <asm/cpufeatures.h>
19 #include <asm/cpuid.h>
20 #include <asm/page.h>
21 #include <asm/pgtable_types.h>
22 #include <asm/percpu.h>
23 #include <asm/desc_defs.h>
24 #include <asm/nops.h>
25 #include <asm/special_insns.h>
26 #include <asm/fpu/types.h>
27 #include <asm/unwind_hints.h>
28 #include <asm/vmxfeatures.h>
29 #include <asm/vdso/processor.h>
30 #include <asm/shstk.h>
31 
32 #include <linux/personality.h>
33 #include <linux/cache.h>
34 #include <linux/threads.h>
35 #include <linux/math64.h>
36 #include <linux/err.h>
37 #include <linux/irqflags.h>
38 #include <linux/mem_encrypt.h>
39 
40 /*
41  * We handle most unaligned accesses in hardware.  On the other hand
42  * unaligned DMA can be quite expensive on some Nehalem processors.
43  *
44  * Based on this we disable the IP header alignment in network drivers.
45  */
46 #define NET_IP_ALIGN	0
47 
48 #define HBP_NUM 4
49 
50 /*
51  * These alignment constraints are for performance in the vSMP case,
52  * but in the task_struct case we must also meet hardware imposed
53  * alignment requirements of the FPU state:
54  */
55 #ifdef CONFIG_X86_VSMP
56 # define ARCH_MIN_TASKALIGN		(1 << INTERNODE_CACHE_SHIFT)
57 # define ARCH_MIN_MMSTRUCT_ALIGN	(1 << INTERNODE_CACHE_SHIFT)
58 #else
59 # define ARCH_MIN_TASKALIGN		__alignof__(union fpregs_state)
60 # define ARCH_MIN_MMSTRUCT_ALIGN	0
61 #endif
62 
63 enum tlb_infos {
64 	ENTRIES,
65 	NR_INFO
66 };
67 
68 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
69 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
70 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
71 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
72 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
73 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
74 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
75 
76 /*
77  * CPU type and hardware bug flags. Kept separately for each CPU.
78  */
79 
80 struct cpuinfo_topology {
81 	// Real APIC ID read from the local APIC
82 	u32			apicid;
83 	// The initial APIC ID provided by CPUID
84 	u32			initial_apicid;
85 
86 	// Physical package ID
87 	u32			pkg_id;
88 
89 	// Physical die ID on AMD, Relative on Intel
90 	u32			die_id;
91 
92 	// Compute unit ID - AMD specific
93 	u32			cu_id;
94 
95 	// Core ID relative to the package
96 	u32			core_id;
97 
98 	// Logical ID mappings
99 	u32			logical_pkg_id;
100 	u32			logical_die_id;
101 
102 	// AMD Node ID and Nodes per Package info
103 	u32			amd_node_id;
104 
105 	// Cache level topology IDs
106 	u32			llc_id;
107 	u32			l2c_id;
108 };
109 
110 struct cpuinfo_x86 {
111 	union {
112 		/*
113 		 * The particular ordering (low-to-high) of (vendor,
114 		 * family, model) is done in case range of models, like
115 		 * it is usually done on AMD, need to be compared.
116 		 */
117 		struct {
118 			__u8	x86_model;
119 			/* CPU family */
120 			__u8	x86;
121 			/* CPU vendor */
122 			__u8	x86_vendor;
123 			__u8	x86_reserved;
124 		};
125 		/* combined vendor, family, model */
126 		__u32		x86_vfm;
127 	};
128 	__u8			x86_stepping;
129 #ifdef CONFIG_X86_64
130 	/* Number of 4K pages in DTLB/ITLB combined(in pages): */
131 	int			x86_tlbsize;
132 #endif
133 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
134 	__u32			vmx_capability[NVMXINTS];
135 #endif
136 	__u8			x86_virt_bits;
137 	__u8			x86_phys_bits;
138 	/* Max extended CPUID function supported: */
139 	__u32			extended_cpuid_level;
140 	/* Maximum supported CPUID level, -1=no CPUID: */
141 	int			cpuid_level;
142 	/*
143 	 * Align to size of unsigned long because the x86_capability array
144 	 * is passed to bitops which require the alignment. Use unnamed
145 	 * union to enforce the array is aligned to size of unsigned long.
146 	 */
147 	union {
148 		__u32		x86_capability[NCAPINTS + NBUGINTS];
149 		unsigned long	x86_capability_alignment;
150 	};
151 	char			x86_vendor_id[16];
152 	char			x86_model_id[64];
153 	struct cpuinfo_topology	topo;
154 	/* in KB - valid for CPUS which support this call: */
155 	unsigned int		x86_cache_size;
156 	int			x86_cache_alignment;	/* In bytes */
157 	/* Cache QoS architectural values, valid only on the BSP: */
158 	int			x86_cache_max_rmid;	/* max index */
159 	int			x86_cache_occ_scale;	/* scale to bytes */
160 	int			x86_cache_mbm_width_offset;
161 	int			x86_power;
162 	unsigned long		loops_per_jiffy;
163 	/* protected processor identification number */
164 	u64			ppin;
165 	u16			x86_clflush_size;
166 	/* number of cores as seen by the OS: */
167 	u16			booted_cores;
168 	/* Index into per_cpu list: */
169 	u16			cpu_index;
170 	/*  Is SMT active on this core? */
171 	bool			smt_active;
172 	u32			microcode;
173 	/* Address space bits used by the cache internally */
174 	u8			x86_cache_bits;
175 	unsigned		initialized : 1;
176 } __randomize_layout;
177 
178 #define X86_VENDOR_INTEL	0
179 #define X86_VENDOR_CYRIX	1
180 #define X86_VENDOR_AMD		2
181 #define X86_VENDOR_UMC		3
182 #define X86_VENDOR_CENTAUR	5
183 #define X86_VENDOR_TRANSMETA	7
184 #define X86_VENDOR_NSC		8
185 #define X86_VENDOR_HYGON	9
186 #define X86_VENDOR_ZHAOXIN	10
187 #define X86_VENDOR_VORTEX	11
188 #define X86_VENDOR_NUM		12
189 
190 #define X86_VENDOR_UNKNOWN	0xff
191 
192 /*
193  * capabilities of CPUs
194  */
195 extern struct cpuinfo_x86	boot_cpu_data;
196 extern struct cpuinfo_x86	new_cpu_data;
197 
198 extern __u32			cpu_caps_cleared[NCAPINTS + NBUGINTS];
199 extern __u32			cpu_caps_set[NCAPINTS + NBUGINTS];
200 
201 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
202 #define cpu_data(cpu)		per_cpu(cpu_info, cpu)
203 
204 extern const struct seq_operations cpuinfo_op;
205 
206 #define cache_line_size()	(boot_cpu_data.x86_cache_alignment)
207 
208 extern void cpu_detect(struct cpuinfo_x86 *c);
209 
l1tf_pfn_limit(void)210 static inline unsigned long long l1tf_pfn_limit(void)
211 {
212 	return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
213 }
214 
215 extern void early_cpu_init(void);
216 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
217 extern void print_cpu_info(struct cpuinfo_x86 *);
218 void print_cpu_msr(struct cpuinfo_x86 *);
219 
220 /*
221  * Friendlier CR3 helpers.
222  */
read_cr3_pa(void)223 static inline unsigned long read_cr3_pa(void)
224 {
225 	return __read_cr3() & CR3_ADDR_MASK;
226 }
227 
native_read_cr3_pa(void)228 static inline unsigned long native_read_cr3_pa(void)
229 {
230 	return __native_read_cr3() & CR3_ADDR_MASK;
231 }
232 
load_cr3(pgd_t * pgdir)233 static inline void load_cr3(pgd_t *pgdir)
234 {
235 	write_cr3(__sme_pa(pgdir));
236 }
237 
238 /*
239  * Note that while the legacy 'TSS' name comes from 'Task State Segment',
240  * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
241  * unrelated to the task-switch mechanism:
242  */
243 #ifdef CONFIG_X86_32
244 /* This is the TSS defined by the hardware. */
245 struct x86_hw_tss {
246 	unsigned short		back_link, __blh;
247 	unsigned long		sp0;
248 	unsigned short		ss0, __ss0h;
249 	unsigned long		sp1;
250 
251 	/*
252 	 * We don't use ring 1, so ss1 is a convenient scratch space in
253 	 * the same cacheline as sp0.  We use ss1 to cache the value in
254 	 * MSR_IA32_SYSENTER_CS.  When we context switch
255 	 * MSR_IA32_SYSENTER_CS, we first check if the new value being
256 	 * written matches ss1, and, if it's not, then we wrmsr the new
257 	 * value and update ss1.
258 	 *
259 	 * The only reason we context switch MSR_IA32_SYSENTER_CS is
260 	 * that we set it to zero in vm86 tasks to avoid corrupting the
261 	 * stack if we were to go through the sysenter path from vm86
262 	 * mode.
263 	 */
264 	unsigned short		ss1;	/* MSR_IA32_SYSENTER_CS */
265 
266 	unsigned short		__ss1h;
267 	unsigned long		sp2;
268 	unsigned short		ss2, __ss2h;
269 	unsigned long		__cr3;
270 	unsigned long		ip;
271 	unsigned long		flags;
272 	unsigned long		ax;
273 	unsigned long		cx;
274 	unsigned long		dx;
275 	unsigned long		bx;
276 	unsigned long		sp;
277 	unsigned long		bp;
278 	unsigned long		si;
279 	unsigned long		di;
280 	unsigned short		es, __esh;
281 	unsigned short		cs, __csh;
282 	unsigned short		ss, __ssh;
283 	unsigned short		ds, __dsh;
284 	unsigned short		fs, __fsh;
285 	unsigned short		gs, __gsh;
286 	unsigned short		ldt, __ldth;
287 	unsigned short		trace;
288 	unsigned short		io_bitmap_base;
289 
290 } __attribute__((packed));
291 #else
292 struct x86_hw_tss {
293 	u32			reserved1;
294 	u64			sp0;
295 	u64			sp1;
296 
297 	/*
298 	 * Since Linux does not use ring 2, the 'sp2' slot is unused by
299 	 * hardware.  entry_SYSCALL_64 uses it as scratch space to stash
300 	 * the user RSP value.
301 	 */
302 	u64			sp2;
303 
304 	u64			reserved2;
305 	u64			ist[7];
306 	u32			reserved3;
307 	u32			reserved4;
308 	u16			reserved5;
309 	u16			io_bitmap_base;
310 
311 } __attribute__((packed));
312 #endif
313 
314 /*
315  * IO-bitmap sizes:
316  */
317 #define IO_BITMAP_BITS			65536
318 #define IO_BITMAP_BYTES			(IO_BITMAP_BITS / BITS_PER_BYTE)
319 #define IO_BITMAP_LONGS			(IO_BITMAP_BYTES / sizeof(long))
320 
321 #define IO_BITMAP_OFFSET_VALID_MAP				\
322 	(offsetof(struct tss_struct, io_bitmap.bitmap) -	\
323 	 offsetof(struct tss_struct, x86_tss))
324 
325 #define IO_BITMAP_OFFSET_VALID_ALL				\
326 	(offsetof(struct tss_struct, io_bitmap.mapall) -	\
327 	 offsetof(struct tss_struct, x86_tss))
328 
329 #ifdef CONFIG_X86_IOPL_IOPERM
330 /*
331  * sizeof(unsigned long) coming from an extra "long" at the end of the
332  * iobitmap. The limit is inclusive, i.e. the last valid byte.
333  */
334 # define __KERNEL_TSS_LIMIT	\
335 	(IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \
336 	 sizeof(unsigned long) - 1)
337 #else
338 # define __KERNEL_TSS_LIMIT	\
339 	(offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1)
340 #endif
341 
342 /* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */
343 #define IO_BITMAP_OFFSET_INVALID	(__KERNEL_TSS_LIMIT + 1)
344 
345 struct entry_stack {
346 	char	stack[PAGE_SIZE];
347 };
348 
349 struct entry_stack_page {
350 	struct entry_stack stack;
351 } __aligned(PAGE_SIZE);
352 
353 /*
354  * All IO bitmap related data stored in the TSS:
355  */
356 struct x86_io_bitmap {
357 	/* The sequence number of the last active bitmap. */
358 	u64			prev_sequence;
359 
360 	/*
361 	 * Store the dirty size of the last io bitmap offender. The next
362 	 * one will have to do the cleanup as the switch out to a non io
363 	 * bitmap user will just set x86_tss.io_bitmap_base to a value
364 	 * outside of the TSS limit. So for sane tasks there is no need to
365 	 * actually touch the io_bitmap at all.
366 	 */
367 	unsigned int		prev_max;
368 
369 	/*
370 	 * The extra 1 is there because the CPU will access an
371 	 * additional byte beyond the end of the IO permission
372 	 * bitmap. The extra byte must be all 1 bits, and must
373 	 * be within the limit.
374 	 */
375 	unsigned long		bitmap[IO_BITMAP_LONGS + 1];
376 
377 	/*
378 	 * Special I/O bitmap to emulate IOPL(3). All bytes zero,
379 	 * except the additional byte at the end.
380 	 */
381 	unsigned long		mapall[IO_BITMAP_LONGS + 1];
382 };
383 
384 struct tss_struct {
385 	/*
386 	 * The fixed hardware portion.  This must not cross a page boundary
387 	 * at risk of violating the SDM's advice and potentially triggering
388 	 * errata.
389 	 */
390 	struct x86_hw_tss	x86_tss;
391 
392 	struct x86_io_bitmap	io_bitmap;
393 } __aligned(PAGE_SIZE);
394 
395 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
396 
397 /* Per CPU interrupt stacks */
398 struct irq_stack {
399 	char		stack[IRQ_STACK_SIZE];
400 } __aligned(IRQ_STACK_SIZE);
401 
402 #ifdef CONFIG_X86_64
403 struct fixed_percpu_data {
404 	/*
405 	 * GCC hardcodes the stack canary as %gs:40.  Since the
406 	 * irq_stack is the object at %gs:0, we reserve the bottom
407 	 * 48 bytes of the irq stack for the canary.
408 	 *
409 	 * Once we are willing to require -mstack-protector-guard-symbol=
410 	 * support for x86_64 stackprotector, we can get rid of this.
411 	 */
412 	char		gs_base[40];
413 	unsigned long	stack_canary;
414 };
415 
416 DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible;
417 DECLARE_INIT_PER_CPU(fixed_percpu_data);
418 
cpu_kernelmode_gs_base(int cpu)419 static inline unsigned long cpu_kernelmode_gs_base(int cpu)
420 {
421 	return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu);
422 }
423 
424 extern asmlinkage void entry_SYSCALL32_ignore(void);
425 
426 /* Save actual FS/GS selectors and bases to current->thread */
427 void current_save_fsgs(void);
428 #else	/* X86_64 */
429 #ifdef CONFIG_STACKPROTECTOR
430 DECLARE_PER_CPU(unsigned long, __stack_chk_guard);
431 #endif
432 #endif	/* !X86_64 */
433 
434 struct perf_event;
435 
436 struct thread_struct {
437 	/* Cached TLS descriptors: */
438 	struct desc_struct	tls_array[GDT_ENTRY_TLS_ENTRIES];
439 #ifdef CONFIG_X86_32
440 	unsigned long		sp0;
441 #endif
442 	unsigned long		sp;
443 #ifdef CONFIG_X86_32
444 	unsigned long		sysenter_cs;
445 #else
446 	unsigned short		es;
447 	unsigned short		ds;
448 	unsigned short		fsindex;
449 	unsigned short		gsindex;
450 #endif
451 
452 #ifdef CONFIG_X86_64
453 	unsigned long		fsbase;
454 	unsigned long		gsbase;
455 #else
456 	/*
457 	 * XXX: this could presumably be unsigned short.  Alternatively,
458 	 * 32-bit kernels could be taught to use fsindex instead.
459 	 */
460 	unsigned long fs;
461 	unsigned long gs;
462 #endif
463 
464 	/* Save middle states of ptrace breakpoints */
465 	struct perf_event	*ptrace_bps[HBP_NUM];
466 	/* Debug status used for traps, single steps, etc... */
467 	unsigned long           virtual_dr6;
468 	/* Keep track of the exact dr7 value set by the user */
469 	unsigned long           ptrace_dr7;
470 	/* Fault info: */
471 	unsigned long		cr2;
472 	unsigned long		trap_nr;
473 	unsigned long		error_code;
474 #ifdef CONFIG_VM86
475 	/* Virtual 86 mode info */
476 	struct vm86		*vm86;
477 #endif
478 	/* IO permissions: */
479 	struct io_bitmap	*io_bitmap;
480 
481 	/*
482 	 * IOPL. Privilege level dependent I/O permission which is
483 	 * emulated via the I/O bitmap to prevent user space from disabling
484 	 * interrupts.
485 	 */
486 	unsigned long		iopl_emul;
487 
488 	unsigned int		iopl_warn:1;
489 
490 	/*
491 	 * Protection Keys Register for Userspace.  Loaded immediately on
492 	 * context switch. Store it in thread_struct to avoid a lookup in
493 	 * the tasks's FPU xstate buffer. This value is only valid when a
494 	 * task is scheduled out. For 'current' the authoritative source of
495 	 * PKRU is the hardware itself.
496 	 */
497 	u32			pkru;
498 
499 #ifdef CONFIG_X86_USER_SHADOW_STACK
500 	unsigned long		features;
501 	unsigned long		features_locked;
502 
503 	struct thread_shstk	shstk;
504 #endif
505 
506 	/* Floating point and extended processor state */
507 	struct fpu		fpu;
508 	/*
509 	 * WARNING: 'fpu' is dynamically-sized.  It *MUST* be at
510 	 * the end.
511 	 */
512 };
513 
514 extern void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size);
515 
arch_thread_struct_whitelist(unsigned long * offset,unsigned long * size)516 static inline void arch_thread_struct_whitelist(unsigned long *offset,
517 						unsigned long *size)
518 {
519 	fpu_thread_struct_whitelist(offset, size);
520 }
521 
522 static inline void
native_load_sp0(unsigned long sp0)523 native_load_sp0(unsigned long sp0)
524 {
525 	this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
526 }
527 
native_swapgs(void)528 static __always_inline void native_swapgs(void)
529 {
530 #ifdef CONFIG_X86_64
531 	asm volatile("swapgs" ::: "memory");
532 #endif
533 }
534 
current_top_of_stack(void)535 static __always_inline unsigned long current_top_of_stack(void)
536 {
537 	/*
538 	 *  We can't read directly from tss.sp0: sp0 on x86_32 is special in
539 	 *  and around vm86 mode and sp0 on x86_64 is special because of the
540 	 *  entry trampoline.
541 	 */
542 	if (IS_ENABLED(CONFIG_USE_X86_SEG_SUPPORT))
543 		return this_cpu_read_const(const_pcpu_hot.top_of_stack);
544 
545 	return this_cpu_read_stable(pcpu_hot.top_of_stack);
546 }
547 
on_thread_stack(void)548 static __always_inline bool on_thread_stack(void)
549 {
550 	return (unsigned long)(current_top_of_stack() -
551 			       current_stack_pointer) < THREAD_SIZE;
552 }
553 
554 #ifdef CONFIG_PARAVIRT_XXL
555 #include <asm/paravirt.h>
556 #else
557 
load_sp0(unsigned long sp0)558 static inline void load_sp0(unsigned long sp0)
559 {
560 	native_load_sp0(sp0);
561 }
562 
563 #endif /* CONFIG_PARAVIRT_XXL */
564 
565 unsigned long __get_wchan(struct task_struct *p);
566 
567 extern void select_idle_routine(void);
568 extern void amd_e400_c1e_apic_setup(void);
569 
570 extern unsigned long		boot_option_idle_override;
571 
572 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
573 			 IDLE_POLL};
574 
575 extern void enable_sep_cpu(void);
576 
577 
578 /* Defined in head.S */
579 extern struct desc_ptr		early_gdt_descr;
580 
581 extern void switch_gdt_and_percpu_base(int);
582 extern void load_direct_gdt(int);
583 extern void load_fixmap_gdt(int);
584 extern void cpu_init(void);
585 extern void cpu_init_exception_handling(bool boot_cpu);
586 extern void cpu_init_replace_early_idt(void);
587 extern void cr4_init(void);
588 
589 extern void set_task_blockstep(struct task_struct *task, bool on);
590 
591 /* Boot loader type from the setup header: */
592 extern int			bootloader_type;
593 extern int			bootloader_version;
594 
595 extern char			ignore_fpu_irq;
596 
597 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
598 #define ARCH_HAS_PREFETCHW
599 
600 #ifdef CONFIG_X86_32
601 # define BASE_PREFETCH		""
602 # define ARCH_HAS_PREFETCH
603 #else
604 # define BASE_PREFETCH		"prefetcht0 %1"
605 #endif
606 
607 /*
608  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
609  *
610  * It's not worth to care about 3dnow prefetches for the K6
611  * because they are microcoded there and very slow.
612  */
prefetch(const void * x)613 static inline void prefetch(const void *x)
614 {
615 	alternative_input(BASE_PREFETCH, "prefetchnta %1",
616 			  X86_FEATURE_XMM,
617 			  "m" (*(const char *)x));
618 }
619 
620 /*
621  * 3dnow prefetch to get an exclusive cache line.
622  * Useful for spinlocks to avoid one state transition in the
623  * cache coherency protocol:
624  */
prefetchw(const void * x)625 static __always_inline void prefetchw(const void *x)
626 {
627 	alternative_input(BASE_PREFETCH, "prefetchw %1",
628 			  X86_FEATURE_3DNOWPREFETCH,
629 			  "m" (*(const char *)x));
630 }
631 
632 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
633 			   TOP_OF_KERNEL_STACK_PADDING)
634 
635 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
636 
637 #define task_pt_regs(task) \
638 ({									\
639 	unsigned long __ptr = (unsigned long)task_stack_page(task);	\
640 	__ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;		\
641 	((struct pt_regs *)__ptr) - 1;					\
642 })
643 
644 #ifdef CONFIG_X86_32
645 #define INIT_THREAD  {							  \
646 	.sp0			= TOP_OF_INIT_STACK,			  \
647 	.sysenter_cs		= __KERNEL_CS,				  \
648 }
649 
650 #define KSTK_ESP(task)		(task_pt_regs(task)->sp)
651 
652 #else
653 extern unsigned long __top_init_kernel_stack[];
654 
655 #define INIT_THREAD {							\
656 	.sp	= (unsigned long)&__top_init_kernel_stack,		\
657 }
658 
659 extern unsigned long KSTK_ESP(struct task_struct *task);
660 
661 #endif /* CONFIG_X86_64 */
662 
663 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
664 					       unsigned long new_sp);
665 
666 /*
667  * This decides where the kernel will search for a free chunk of vm
668  * space during mmap's.
669  */
670 #define __TASK_UNMAPPED_BASE(task_size)	(PAGE_ALIGN(task_size / 3))
671 #define TASK_UNMAPPED_BASE		__TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
672 
673 #define KSTK_EIP(task)		(task_pt_regs(task)->ip)
674 
675 /* Get/set a process' ability to use the timestamp counter instruction */
676 #define GET_TSC_CTL(adr)	get_tsc_mode((adr))
677 #define SET_TSC_CTL(val)	set_tsc_mode((val))
678 
679 extern int get_tsc_mode(unsigned long adr);
680 extern int set_tsc_mode(unsigned int val);
681 
682 DECLARE_PER_CPU(u64, msr_misc_features_shadow);
683 
per_cpu_llc_id(unsigned int cpu)684 static inline u32 per_cpu_llc_id(unsigned int cpu)
685 {
686 	return per_cpu(cpu_info.topo.llc_id, cpu);
687 }
688 
per_cpu_l2c_id(unsigned int cpu)689 static inline u32 per_cpu_l2c_id(unsigned int cpu)
690 {
691 	return per_cpu(cpu_info.topo.l2c_id, cpu);
692 }
693 
694 #ifdef CONFIG_CPU_SUP_AMD
695 /*
696  * Issue a DIV 0/1 insn to clear any division data from previous DIV
697  * operations.
698  */
amd_clear_divider(void)699 static __always_inline void amd_clear_divider(void)
700 {
701 	asm volatile(ALTERNATIVE("", "div %2\n\t", X86_BUG_DIV0)
702 		     :: "a" (0), "d" (0), "r" (1));
703 }
704 
705 extern void amd_check_microcode(void);
706 #else
amd_clear_divider(void)707 static inline void amd_clear_divider(void)		{ }
amd_check_microcode(void)708 static inline void amd_check_microcode(void)		{ }
709 #endif
710 
711 extern unsigned long arch_align_stack(unsigned long sp);
712 void free_init_pages(const char *what, unsigned long begin, unsigned long end);
713 extern void free_kernel_image_pages(const char *what, void *begin, void *end);
714 
715 void default_idle(void);
716 #ifdef	CONFIG_XEN
717 bool xen_set_default_idle(void);
718 #else
719 #define xen_set_default_idle 0
720 #endif
721 
722 void __noreturn stop_this_cpu(void *dummy);
723 void microcode_check(struct cpuinfo_x86 *prev_info);
724 void store_cpu_caps(struct cpuinfo_x86 *info);
725 
726 enum l1tf_mitigations {
727 	L1TF_MITIGATION_OFF,
728 	L1TF_MITIGATION_FLUSH_NOWARN,
729 	L1TF_MITIGATION_FLUSH,
730 	L1TF_MITIGATION_FLUSH_NOSMT,
731 	L1TF_MITIGATION_FULL,
732 	L1TF_MITIGATION_FULL_FORCE
733 };
734 
735 extern enum l1tf_mitigations l1tf_mitigation;
736 
737 enum mds_mitigations {
738 	MDS_MITIGATION_OFF,
739 	MDS_MITIGATION_FULL,
740 	MDS_MITIGATION_VMWERV,
741 };
742 
743 extern bool gds_ucode_mitigated(void);
744 
745 /*
746  * Make previous memory operations globally visible before
747  * a WRMSR.
748  *
749  * MFENCE makes writes visible, but only affects load/store
750  * instructions.  WRMSR is unfortunately not a load/store
751  * instruction and is unaffected by MFENCE.  The LFENCE ensures
752  * that the WRMSR is not reordered.
753  *
754  * Most WRMSRs are full serializing instructions themselves and
755  * do not require this barrier.  This is only required for the
756  * IA32_TSC_DEADLINE and X2APIC MSRs.
757  */
weak_wrmsr_fence(void)758 static inline void weak_wrmsr_fence(void)
759 {
760 	alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE));
761 }
762 
763 #endif /* _ASM_X86_PROCESSOR_H */
764