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Searched refs:clk_regmap (Results 1 – 25 of 171) sorted by relevance

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/linux/drivers/clk/meson/
H A Daxg-audio.c327 static struct clk_regmap ddr_arb =
329 static struct clk_regmap pdm =
331 static struct clk_regmap tdmin_a =
333 static struct clk_regmap tdmin_b =
335 static struct clk_regmap tdmin_c =
345 static struct clk_regmap frddr_a =
347 static struct clk_regmap frddr_b =
349 static struct clk_regmap frddr_c =
633 static struct clk_regmap toram =
637 static struct clk_regmap eqdrc =
[all …]
H A Dc3-peripherals.c168 struct clk_regmap _name = { \
457 static struct clk_regmap gen = {
579 static struct clk_regmap pwm_a =
586 static struct clk_regmap pwm_b =
593 static struct clk_regmap pwm_c =
600 static struct clk_regmap pwm_d =
607 static struct clk_regmap pwm_e =
614 static struct clk_regmap pwm_f =
621 static struct clk_regmap pwm_g =
628 static struct clk_regmap pwm_h =
[all …]
H A Da1-peripherals.c20 static struct clk_regmap xtal_in = {
35 static struct clk_regmap fixpll_in = {
50 static struct clk_regmap usb_phy_in = {
110 static struct clk_regmap dds_in = {
224 static struct clk_regmap rtc = {
281 static struct clk_regmap sys_b = {
329 static struct clk_regmap sys_a = {
345 static struct clk_regmap sys = {
804 static struct clk_regmap gen = {
1262 static struct clk_regmap ts = {
[all …]
H A Ds4-peripherals.c120 static struct clk_regmap s4_rtc_clk = {
189 static struct clk_regmap s4_sysclk_b = {
235 static struct clk_regmap s4_sysclk_a = {
250 static struct clk_regmap s4_sys_clk = {
748 static struct clk_regmap s4_vclk = {
762 static struct clk_regmap s4_vclk2 = {
1225 static struct clk_regmap s4_hdmi = {
1705 static struct clk_regmap s4_vpu_0 = {
1749 static struct clk_regmap s4_vpu_1 = {
1763 static struct clk_regmap s4_vpu = {
[all …]
H A Daxg.c71 static struct clk_regmap axg_fixed_pll = {
130 static struct clk_regmap axg_sys_pll = {
235 static struct clk_regmap axg_gp0_pll = {
522 static struct clk_regmap axg_mpll0 = {
573 static struct clk_regmap axg_mpll1 = {
629 static struct clk_regmap axg_mpll2 = {
680 static struct clk_regmap axg_mpll3 = {
902 static struct clk_regmap axg_clk81 = {
1139 static struct clk_regmap axg_vpu = {
1273 static struct clk_regmap axg_vapb = {
[all …]
H A Dgxbb.c131 static struct clk_regmap gxbb_fixed_pll = {
357 static struct clk_regmap gxl_hdmi_pll = {
775 static struct clk_regmap gxbb_mpll0 = {
827 static struct clk_regmap gxbb_mpll1 = {
870 static struct clk_regmap gxbb_mpll2 = {
932 static struct clk_regmap gxbb_clk81 = {
1130 static struct clk_regmap gxbb_mali = {
1604 static struct clk_regmap gxbb_vpu = {
1761 static struct clk_regmap gxbb_vapb = {
1968 static struct clk_regmap gxbb_vclk = {
[all …]
H A Dvclk.c12 clk_get_meson_vclk_gate_data(struct clk_regmap *clk) in clk_get_meson_vclk_gate_data()
19 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vclk_gate_enable()
33 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vclk_gate_disable()
41 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vclk_gate_is_enabled()
57 clk_get_meson_vclk_div_data(struct clk_regmap *clk) in clk_get_meson_vclk_div_data()
65 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vclk_div_recalc_rate()
75 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vclk_div_determine_rate()
85 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vclk_div_set_rate()
101 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vclk_div_enable()
113 struct clk_regmap *clk = to_clk_regmap(hw); in meson_vclk_div_disable()
[all …]
H A Dclk-phase.c16 meson_clk_phase_data(struct clk_regmap *clk) in meson_clk_phase_data()
39 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_phase_get_phase()
50 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_phase_set_phase()
76 meson_clk_triphase_data(struct clk_regmap *clk) in meson_clk_triphase_data()
83 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_triphase_sync()
97 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_triphase_get_phase()
109 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_triphase_set_phase()
135 meson_sclk_ws_inv_data(struct clk_regmap *clk) in meson_sclk_ws_inv_data()
142 struct clk_regmap *clk = to_clk_regmap(hw); in meson_sclk_ws_inv_sync()
155 struct clk_regmap *clk = to_clk_regmap(hw); in meson_sclk_ws_inv_get_phase()
[all …]
H A Dg12a.c33 static struct clk_regmap g12a_fixed_pll_dco = {
76 static struct clk_regmap g12a_fixed_pll = {
143 static struct clk_regmap g12a_sys_pll = {
202 static struct clk_regmap g12b_sys1_pll = {
703 static struct clk_regmap sm1_gp1_pll;
2803 static struct clk_regmap g12a_vpu = {
3118 static struct clk_regmap g12a_vapb = {
3247 static struct clk_regmap g12a_vclk = {
3893 static struct clk_regmap g12a_hdmi = {
4037 static struct clk_regmap g12a_mali = {
[all …]
H A Dg12a-aoclk.c47 static struct clk_regmap g12a_aoclk_##_name = { \
79 static struct clk_regmap g12a_aoclk_cts_oscin = {
179 static struct clk_regmap g12a_aoclk_32k_by_oscin = {
197 static struct clk_regmap g12a_aoclk_cec_pre = {
212 static struct clk_regmap g12a_aoclk_cec_div = {
251 static struct clk_regmap g12a_aoclk_cec_sel = {
270 static struct clk_regmap g12a_aoclk_cec = {
305 static struct clk_regmap g12a_aoclk_clk81 = {
324 static struct clk_regmap g12a_aoclk_saradc_mux = {
341 static struct clk_regmap g12a_aoclk_saradc_div = {
[all …]
H A Dclk-regmap.h23 struct clk_regmap { struct
29 static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw) in to_clk_regmap() argument
31 return container_of(hw, struct clk_regmap, hw); in to_clk_regmap()
51 clk_get_regmap_gate_data(struct clk_regmap *clk) in clk_get_regmap_gate_data()
79 clk_get_regmap_div_data(struct clk_regmap *clk) in clk_get_regmap_div_data()
109 clk_get_regmap_mux_data(struct clk_regmap *clk) in clk_get_regmap_mux_data()
118 struct clk_regmap _name = { \
H A Dc3-pll.c37 static struct clk_regmap fclk_50m_en = {
78 static struct clk_regmap fclk_div2 = {
134 static struct clk_regmap fclk_div3 = {
162 static struct clk_regmap fclk_div4 = {
190 static struct clk_regmap fclk_div5 = {
218 static struct clk_regmap fclk_div7 = {
303 static struct clk_regmap gp0_pll = {
375 static struct clk_regmap hifi_pll = {
473 static struct clk_regmap mclk_pll = {
544 static struct clk_regmap mclk0 = {
[all …]
H A Dsclk-div.c26 meson_sclk_div_data(struct clk_regmap *clk) in meson_sclk_div_data()
102 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_determine_rate()
112 static void sclk_apply_ratio(struct clk_regmap *clk, in sclk_apply_ratio()
128 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_set_duty_cycle()
142 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_get_duty_cycle()
170 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_set_rate()
185 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_recalc_rate()
193 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_enable()
203 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_disable()
211 struct clk_regmap *clk = to_clk_regmap(hw); in sclk_div_is_enabled()
[all …]
H A Daxg-aoclk.c38 static struct clk_regmap axg_aoclk_##_name = { \
62 static struct clk_regmap axg_aoclk_cts_oscin = {
77 static struct clk_regmap axg_aoclk_32k_pre = {
102 static struct clk_regmap axg_aoclk_32k_div = {
141 static struct clk_regmap axg_aoclk_32k_sel = {
160 static struct clk_regmap axg_aoclk_32k = {
195 static struct clk_regmap axg_aoclk_clk81 = {
214 static struct clk_regmap axg_aoclk_saradc_mux = {
231 static struct clk_regmap axg_aoclk_saradc_div = {
248 static struct clk_regmap axg_aoclk_saradc_gate = {
[all …]
H A Dmeson8b.c104 static struct clk_regmap meson8b_fixed_pll = {
299 static struct clk_regmap meson8b_sys_pll = {
507 static struct clk_regmap meson8b_mpll0 = {
552 static struct clk_regmap meson8b_mpll1 = {
597 static struct clk_regmap meson8b_mpll2 = {
654 static struct clk_regmap meson8b_clk81 = {
775 static struct clk_regmap meson8b_cpu_clk = {
1991 static struct clk_regmap meson8b_mali = {
2151 static struct clk_regmap meson8b_vpu_0 = {
2222 static struct clk_regmap meson8b_vpu_1 = {
[all …]
H A Ds4-pll.c29 static struct clk_regmap s4_fixed_pll_dco = {
72 static struct clk_regmap s4_fixed_pll = {
104 static struct clk_regmap s4_fclk_div2 = {
130 static struct clk_regmap s4_fclk_div3 = {
156 static struct clk_regmap s4_fclk_div4 = {
182 static struct clk_regmap s4_fclk_div5 = {
309 static struct clk_regmap s4_gp0_pll = {
559 static struct clk_regmap s4_mpll0 = {
613 static struct clk_regmap s4_mpll1 = {
667 static struct clk_regmap s4_mpll2 = {
[all …]
H A Dgxbb-aoclk.c27 static struct clk_regmap _name##_ao = { \
50 static struct clk_regmap ao_cts_oscin = {
65 static struct clk_regmap ao_32k_pre = {
88 static struct clk_regmap ao_32k_div = {
125 static struct clk_regmap ao_32k_sel = {
144 static struct clk_regmap ao_32k = {
158 static struct clk_regmap ao_cts_rtc_oscin = {
180 static struct clk_regmap ao_clk81 = {
199 static struct clk_regmap ao_cts_cec = {
240 static struct clk_regmap *gxbb_aoclk[] = {
H A Dclk-regmap.c12 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_endisable()
34 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_gate_is_enabled()
62 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_div_recalc_rate()
81 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_div_determine_rate()
106 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_div_set_rate()
138 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_mux_get_parent()
154 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_mux_set_parent()
166 struct clk_regmap *clk = to_clk_regmap(hw); in clk_regmap_mux_determine_rate()
H A Da1-pll.c19 static struct clk_regmap fixed_pll_dco = {
62 static struct clk_regmap fixed_pll = {
90 static struct clk_regmap hifi_pll = {
154 static struct clk_regmap fclk_div2 = {
192 static struct clk_regmap fclk_div3 = {
225 static struct clk_regmap fclk_div5 = {
258 static struct clk_regmap fclk_div7 = {
288 static struct clk_regmap *const a1_pll_regmaps[] = {
H A Dclk-cpu-dyndiv.c14 meson_clk_cpu_dyndiv_data(struct clk_regmap *clk) in meson_clk_cpu_dyndiv_data()
22 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_cpu_dyndiv_recalc_rate()
33 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_cpu_dyndiv_determine_rate()
42 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_cpu_dyndiv_set_rate()
H A Dclk-mpll.c26 meson_clk_mpll_data(struct clk_regmap *clk) in meson_clk_mpll_data()
78 struct clk_regmap *clk = to_clk_regmap(hw); in mpll_recalc_rate()
92 struct clk_regmap *clk = to_clk_regmap(hw); in mpll_determine_rate()
112 struct clk_regmap *clk = to_clk_regmap(hw); in mpll_set_rate()
140 struct clk_regmap *clk = to_clk_regmap(hw); in mpll_init()
/linux/drivers/clk/qcom/
H A Dclk-regmap.h20 struct clk_regmap { struct
28 static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw) in to_clk_regmap() argument
30 return container_of(hw, struct clk_regmap, hw); in to_clk_regmap()
36 int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk);
H A Dclk-regmap-phy-mux.c18 static inline struct clk_regmap_phy_mux *to_clk_regmap_phy_mux(struct clk_regmap *clkr) in to_clk_regmap_phy_mux()
25 struct clk_regmap *clkr = to_clk_regmap(hw); in phy_mux_is_enabled()
39 struct clk_regmap *clkr = to_clk_regmap(hw); in phy_mux_enable()
49 struct clk_regmap *clkr = to_clk_regmap(hw); in phy_mux_disable()
H A Dclk-regmap.c24 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_is_enabled_regmap()
50 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_enable_regmap()
74 struct clk_regmap *rclk = to_clk_regmap(hw); in clk_disable_regmap()
97 int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk) in devm_clk_register_regmap()
/linux/drivers/clk/nxp/
H A Dclk-lpc32xx.c74 static struct regmap *clk_regmap; variable
393 regmap_read(clk_regmap, clk->reg, &val); in clk_mask_enable()
406 regmap_update_bits(clk_regmap, clk->reg, in clk_mask_disable()
415 regmap_read(clk_regmap, clk->reg, &val); in clk_mask_is_enabled()
457 regmap_read(clk_regmap, clk->reg, &val); in clk_pll_is_enabled()
480 regmap_read(clk_regmap, clk->reg, &val); in clk_pll_recalc_rate()
718 regmap_read(clk_regmap, clk->reg, &val); in clk_ddram_is_enabled()
730 regmap_read(clk_regmap, clk->reg, &val); in clk_ddram_enable()
1479 regmap_read(clk_regmap, reg, &val); in lpc32xx_clk_div_quirk()
1521 if (IS_ERR(clk_regmap)) { in lpc32xx_clk_init()
[all …]

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