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Searched refs:clock_cfg (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dptp.c372 u64 clock_cfg; in ptp_start() local
404 clock_cfg |= PTP_CLOCK_CFG_EXT_CLK_EN; in ptp_start()
408 clock_cfg |= PTP_CLOCK_CFG_TSTMP_EDGE; in ptp_start()
410 clock_cfg &= ~PTP_CLOCK_CFG_TSTMP_IN_MASK; in ptp_start()
411 clock_cfg |= PTP_CLOCK_CFG_TSTMP_EN; in ptp_start()
414 clock_cfg |= PTP_CLOCK_CFG_PTP_EN; in ptp_start()
417 clock_cfg &= ~PTP_CLOCK_CFG_ATOMIC_OP_MASK; in ptp_start()
418 clock_cfg |= (ATOMIC_SET << 26); in ptp_start()
469 u64 clock_cfg; in ptp_pps_on() local
575 u64 clock_cfg; in ptp_remove() local
[all …]
/linux/drivers/net/ethernet/cavium/common/
H A Dcavium_ptp.c226 u64 clock_cfg; in cavium_ptp_probe() local
275 clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
276 clock_cfg |= PTP_CLOCK_CFG_PTP_EN; in cavium_ptp_probe()
277 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
292 clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
293 clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN; in cavium_ptp_probe()
294 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
314 u64 clock_cfg; in cavium_ptp_remove() local
321 clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_remove()
322 clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN; in cavium_ptp_remove()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c452 struct dc_clock_config *clock_cfg) in dcn2_get_clock() argument
456 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dcn2_get_clock()
457 clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz; in dcn2_get_clock()
458 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz; in dcn2_get_clock()
459 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; in dcn2_get_clock()
462 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; in dcn2_get_clock()
463 clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz; in dcn2_get_clock()
464 clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz; in dcn2_get_clock()
465 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; in dcn2_get_clock()
H A Ddcn20_clk_mgr.h51 struct dc_clock_config *clock_cfg);
/linux/drivers/clk/stm32/
H A Dclk-stm32-core.h50 void *clock_cfg; member
167 .clock_cfg = (_struct) {_clk},\
H A Dclk-stm32-core.c632 struct clk_stm32_mux *mux = cfg->clock_cfg; in clk_stm32_mux_register()
653 struct clk_stm32_gate *gate = cfg->clock_cfg; in clk_stm32_gate_register()
674 struct clk_stm32_div *div = cfg->clock_cfg; in clk_stm32_div_register()
695 struct clk_stm32_composite *composite = cfg->clock_cfg; in clk_stm32_composite_register()
/linux/drivers/spi/
H A Dspi-fsi.c369 u64 clock_cfg = 0ULL; in fsi_spi_transfer_init() local
409 rc = fsi_spi_read_reg(ctx, SPI_FSI_CLOCK_CFG, &clock_cfg); in fsi_spi_transfer_init()
413 if ((clock_cfg & (SPI_FSI_CLOCK_CFG_MM_ENABLE | in fsi_spi_transfer_init()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.h188 struct dc_clock_config *clock_cfg);
H A Ddcn10_hwseq.c3914 struct dc_clock_config clock_cfg = {0}; in dcn10_set_clock() local
3921 context, clock_type, &clock_cfg); in dcn10_set_clock()
3923 if (clk_khz > clock_cfg.max_clock_khz) in dcn10_set_clock()
3926 if (clk_khz < clock_cfg.min_clock_khz) in dcn10_set_clock()
3929 if (clk_khz < clock_cfg.bw_requirequired_clock_khz) in dcn10_set_clock()
3949 struct dc_clock_config *clock_cfg) in dcn10_get_clock() argument
3954 dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg); in dcn10_get_clock()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h294 struct dc_clock_config *clock_cfg);
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h327 struct dc_clock_config *clock_cfg);
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h2375 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c5125 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg) in dc_get_clock() argument
5128 dc->hwss.get_clock(dc, clock_type, clock_cfg); in dc_get_clock()