1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #ifndef __DAL_CLK_MGR_INTERNAL_H__
27 #define __DAL_CLK_MGR_INTERNAL_H__
28
29 #include "clk_mgr.h"
30 #include "dc.h"
31
32 /*
33 * only thing needed from here is MEMORY_TYPE_MULTIPLIER_CZ, which is also
34 * used in resource, perhaps this should be defined somewhere more common.
35 */
36 #include "resource.h"
37
38
39 /* Starting DID for each range */
40 enum dentist_base_divider_id {
41 DENTIST_BASE_DID_1 = 0x08,
42 DENTIST_BASE_DID_2 = 0x40,
43 DENTIST_BASE_DID_3 = 0x60,
44 DENTIST_BASE_DID_4 = 0x7e,
45 DENTIST_MAX_DID = 0x7f
46 };
47
48 /* Starting point and step size for each divider range.*/
49 enum dentist_divider_range {
50 DENTIST_DIVIDER_RANGE_1_START = 8, /* 2.00 */
51 DENTIST_DIVIDER_RANGE_1_STEP = 1, /* 0.25 */
52 DENTIST_DIVIDER_RANGE_2_START = 64, /* 16.00 */
53 DENTIST_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */
54 DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */
55 DENTIST_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */
56 DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */
57 DENTIST_DIVIDER_RANGE_4_STEP = 264, /* 66.00 */
58 DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4
59 };
60
61 /*
62 ***************************************************************************************
63 ****************** Clock Manager Private Macros and Defines ***************************
64 ***************************************************************************************
65 */
66
67 /* Macros */
68
69 #define TO_CLK_MGR_INTERNAL(clk_mgr)\
70 container_of(clk_mgr, struct clk_mgr_internal, base)
71
72 #define CTX \
73 clk_mgr->base.ctx
74
75 #define DC_LOGGER \
76 dc->ctx->logger
77
78
79
80
81 #define CLK_BASE(inst) \
82 CLK_BASE_INNER(inst)
83
84 #define CLK_SRI(reg_name, block, inst)\
85 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
86 mm ## block ## _ ## inst ## _ ## reg_name
87
88 #define CLK_COMMON_REG_LIST_DCE_BASE() \
89 .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
90 .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
91
92 #if defined(CONFIG_DRM_AMD_DC_SI)
93 #define CLK_COMMON_REG_LIST_DCE60_BASE() \
94 SR(DENTIST_DISPCLK_CNTL)
95 #endif
96
97 #define CLK_COMMON_REG_LIST_DCN_BASE() \
98 SR(DENTIST_DISPCLK_CNTL)
99
100 #define CLK_COMMON_REG_LIST_DCN_201() \
101 SR(DENTIST_DISPCLK_CNTL), \
102 CLK_SRI(CLK4_CLK_PLL_REQ, CLK4, 0), \
103 CLK_SRI(CLK4_CLK2_CURRENT_CNT, CLK4, 0)
104
105 #define CLK_REG_LIST_NV10() \
106 SR(DENTIST_DISPCLK_CNTL), \
107 CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
108 CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
109
110 #define CLK_REG_LIST_DCN3() \
111 SR(DENTIST_DISPCLK_CNTL), \
112 CLK_SRI(CLK0_CLK_PLL_REQ, CLK02, 0), \
113 CLK_SRI(CLK0_CLK2_DFS_CNTL, CLK02, 0)
114
115 #define CLK_SF(reg_name, field_name, post_fix)\
116 .field_name = reg_name ## __ ## field_name ## post_fix
117
118 #define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
119 CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
120 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
121
122 #if defined(CONFIG_DRM_AMD_DC_SI)
123 #define CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh) \
124 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
125 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
126 #endif
127
128 #define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
129 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
130 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
131
132 #define CLK_MASK_SH_LIST_RV1(mask_sh) \
133 CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
134 CLK_SF(MP1_SMN_C2PMSG_67, CONTENT, mask_sh),\
135 CLK_SF(MP1_SMN_C2PMSG_83, CONTENT, mask_sh),\
136 CLK_SF(MP1_SMN_C2PMSG_91, CONTENT, mask_sh),
137
138 #define CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh) \
139 CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
140 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\
141 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh)
142
143 #define CLK_MASK_SH_LIST_NV10(mask_sh) \
144 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
145 CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_int, mask_sh),\
146 CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_frac, mask_sh)
147
148 #define CLK_COMMON_MASK_SH_LIST_DCN201_BASE(mask_sh) \
149 CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
150 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\
151 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh),\
152 CLK_SF(CLK4_0_CLK4_CLK_PLL_REQ, FbMult_int, mask_sh)
153
154 #define CLK_REG_LIST_DCN32() \
155 SR(DENTIST_DISPCLK_CNTL), \
156 CLK_SR_DCN32(CLK1_CLK_PLL_REQ), \
157 CLK_SR_DCN32(CLK1_CLK0_DFS_CNTL), \
158 CLK_SR_DCN32(CLK1_CLK1_DFS_CNTL), \
159 CLK_SR_DCN32(CLK1_CLK2_DFS_CNTL), \
160 CLK_SR_DCN32(CLK1_CLK3_DFS_CNTL), \
161 CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL), \
162 CLK_SR_DCN32(CLK1_CLK0_CURRENT_CNT), \
163 CLK_SR_DCN32(CLK1_CLK1_CURRENT_CNT), \
164 CLK_SR_DCN32(CLK1_CLK2_CURRENT_CNT), \
165 CLK_SR_DCN32(CLK1_CLK3_CURRENT_CNT), \
166 CLK_SR_DCN32(CLK1_CLK4_CURRENT_CNT), \
167 CLK_SR_DCN32(CLK4_CLK0_CURRENT_CNT)
168
169 #define CLK_COMMON_MASK_SH_LIST_DCN32(mask_sh) \
170 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
171 CLK_SF(CLK1_CLK_PLL_REQ, FbMult_int, mask_sh),\
172 CLK_SF(CLK1_CLK_PLL_REQ, FbMult_frac, mask_sh)
173
174 #define CLK_REG_LIST_DCN321() \
175 SR(DENTIST_DISPCLK_CNTL), \
176 CLK_SR_DCN321(CLK0_CLK_PLL_REQ, CLK01, 0), \
177 CLK_SR_DCN321(CLK0_CLK0_DFS_CNTL, CLK01, 0), \
178 CLK_SR_DCN321(CLK0_CLK1_DFS_CNTL, CLK01, 0), \
179 CLK_SR_DCN321(CLK0_CLK2_DFS_CNTL, CLK01, 0), \
180 CLK_SR_DCN321(CLK0_CLK3_DFS_CNTL, CLK01, 0), \
181 CLK_SR_DCN321(CLK0_CLK4_DFS_CNTL, CLK01, 0)
182
183 #define CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh) \
184 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
185 CLK_SF(CLK0_CLK_PLL_REQ, FbMult_int, mask_sh),\
186 CLK_SF(CLK0_CLK_PLL_REQ, FbMult_frac, mask_sh)
187
188 #define CLK_REG_LIST_DCN401() \
189 CLK_SR_DCN401(CLK0_CLK_PLL_REQ, CLK01, 0), \
190 CLK_SR_DCN401(CLK0_CLK0_DFS_CNTL, CLK01, 0), \
191 CLK_SR_DCN401(CLK0_CLK1_DFS_CNTL, CLK01, 0), \
192 CLK_SR_DCN401(CLK0_CLK2_DFS_CNTL, CLK01, 0), \
193 CLK_SR_DCN401(CLK0_CLK3_DFS_CNTL, CLK01, 0), \
194 CLK_SR_DCN401(CLK0_CLK4_DFS_CNTL, CLK01, 0), \
195 CLK_SR_DCN401(CLK2_CLK2_DFS_CNTL, CLK20, 0)
196
197 #define CLK_COMMON_MASK_SH_LIST_DCN401(mask_sh) \
198 CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh)
199
200 #define CLK_REG_FIELD_LIST(type) \
201 type DPREFCLK_SRC_SEL; \
202 type DENTIST_DPREFCLK_WDIVIDER; \
203 type DENTIST_DISPCLK_WDIVIDER; \
204 type DENTIST_DISPCLK_CHG_DONE;
205
206 #define CLK20_REG_FIELD_LIST(type) \
207 type DENTIST_DPPCLK_WDIVIDER; \
208 type DENTIST_DPPCLK_CHG_DONE; \
209 type FbMult_int; \
210 type FbMult_frac;
211
212 /*
213 ***************************************************************************************
214 ****************** Clock Manager Private Structures ***********************************
215 ***************************************************************************************
216 */
217
218 struct clk_mgr_registers {
219 uint32_t DPREFCLK_CNTL;
220 uint32_t DENTIST_DISPCLK_CNTL;
221
222 uint32_t CLK4_CLK2_CURRENT_CNT;
223 uint32_t CLK4_CLK_PLL_REQ;
224
225 uint32_t CLK4_CLK0_CURRENT_CNT;
226
227 uint32_t CLK3_CLK2_DFS_CNTL;
228 uint32_t CLK3_CLK_PLL_REQ;
229
230 uint32_t CLK0_CLK2_DFS_CNTL;
231 uint32_t CLK0_CLK_PLL_REQ;
232
233 uint32_t CLK1_CLK_PLL_REQ;
234 uint32_t CLK1_CLK0_DFS_CNTL;
235 uint32_t CLK1_CLK1_DFS_CNTL;
236 uint32_t CLK1_CLK2_DFS_CNTL;
237 uint32_t CLK1_CLK3_DFS_CNTL;
238 uint32_t CLK1_CLK4_DFS_CNTL;
239 uint32_t CLK2_CLK2_DFS_CNTL;
240
241 uint32_t CLK1_CLK0_CURRENT_CNT;
242 uint32_t CLK1_CLK1_CURRENT_CNT;
243 uint32_t CLK1_CLK2_CURRENT_CNT;
244 uint32_t CLK1_CLK3_CURRENT_CNT;
245 uint32_t CLK1_CLK4_CURRENT_CNT;
246
247 uint32_t CLK0_CLK0_DFS_CNTL;
248 uint32_t CLK0_CLK1_DFS_CNTL;
249 uint32_t CLK0_CLK3_DFS_CNTL;
250 uint32_t CLK0_CLK4_DFS_CNTL;
251 };
252
253 struct clk_mgr_shift {
254 CLK_REG_FIELD_LIST(uint8_t)
255 CLK20_REG_FIELD_LIST(uint8_t)
256 };
257
258 struct clk_mgr_mask {
259 CLK_REG_FIELD_LIST(uint32_t)
260 CLK20_REG_FIELD_LIST(uint32_t)
261 };
262
263 enum clock_type {
264 clock_type_dispclk = 1,
265 clock_type_dcfclk,
266 clock_type_socclk,
267 clock_type_pixelclk,
268 clock_type_phyclk,
269 clock_type_dppclk,
270 clock_type_fclk,
271 clock_type_dcfdsclk,
272 clock_type_dscclk,
273 clock_type_uclk,
274 clock_type_dramclk,
275 };
276
277
278 struct state_dependent_clocks {
279 int display_clk_khz;
280 int pixel_clk_khz;
281 };
282
283 struct clk_mgr_internal {
284 struct clk_mgr base;
285 int smu_ver;
286 struct pp_smu_funcs *pp_smu;
287 struct clk_mgr_internal_funcs *funcs;
288
289 struct dccg *dccg;
290
291 /*
292 * For backwards compatbility with previous implementation
293 * TODO: remove these after everything transitions to new pattern
294 * Rationale is that clk registers change a lot across DCE versions
295 * and a shared data structure doesn't really make sense.
296 */
297 const struct clk_mgr_registers *regs;
298 const struct clk_mgr_shift *clk_mgr_shift;
299 const struct clk_mgr_mask *clk_mgr_mask;
300
301 struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
302
303 /*TODO: figure out which of the below fields should be here vs in asic specific portion */
304 /* Cache the status of DFS-bypass feature*/
305 bool dfs_bypass_enabled;
306 /* True if the DFS-bypass feature is enabled and active. */
307 bool dfs_bypass_active;
308
309 uint32_t dfs_ref_freq_khz;
310 /*
311 * Cache the display clock returned by VBIOS if DFS-bypass is enabled.
312 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency
313 */
314 int dfs_bypass_disp_clk;
315
316 /**
317 * @ss_on_dprefclk:
318 *
319 * True if spread spectrum is enabled on the DP ref clock.
320 */
321 bool ss_on_dprefclk;
322
323 /**
324 * @xgmi_enabled:
325 *
326 * True if xGMI is enabled. On VG20, both audio and display clocks need
327 * to be adjusted with the WAFL link's SS info if xGMI is enabled.
328 */
329 bool xgmi_enabled;
330
331 /**
332 * @dprefclk_ss_percentage:
333 *
334 * DPREFCLK SS percentage (if down-spread enabled).
335 *
336 * Note that if XGMI is enabled, the SS info (percentage and divider)
337 * from the WAFL link is used instead. This is decided during
338 * dce_clk_mgr initialization.
339 */
340 int dprefclk_ss_percentage;
341
342 /**
343 * @dprefclk_ss_divider:
344 *
345 * DPREFCLK SS percentage Divider (100 or 1000).
346 */
347 int dprefclk_ss_divider;
348
349 enum dm_pp_clocks_state max_clks_state;
350 enum dm_pp_clocks_state cur_min_clks_state;
351 bool periodic_retraining_disabled;
352
353 unsigned int cur_phyclk_req_table[MAX_LINKS];
354
355 bool smu_present;
356 void *wm_range_table;
357 long long wm_range_table_addr;
358
359 bool dpm_present;
360 bool pme_trigger_pending;
361 };
362
363 struct clk_mgr_internal_funcs {
364 int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
365 int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr);
366 };
367
368
369 /*
370 ***************************************************************************************
371 ****************** Clock Manager Level Helper functions *******************************
372 ***************************************************************************************
373 */
374
375
should_set_clock(bool safe_to_lower,int calc_clk,int cur_clk)376 static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk)
377 {
378 return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk);
379 }
380
should_update_pstate_support(bool safe_to_lower,bool calc_support,bool cur_support)381 static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support)
382 {
383 if (cur_support != calc_support) {
384 if (calc_support && safe_to_lower)
385 return true;
386 else if (!calc_support && !safe_to_lower)
387 return true;
388 }
389
390 return false;
391 }
392
khz_to_mhz_ceil(int khz)393 static inline int khz_to_mhz_ceil(int khz)
394 {
395 return (khz + 999) / 1000;
396 }
397
khz_to_mhz_floor(int khz)398 static inline int khz_to_mhz_floor(int khz)
399 {
400 return khz / 1000;
401 }
402
403 int clk_mgr_helper_get_active_display_cnt(
404 struct dc *dc,
405 struct dc_state *context);
406
407 int clk_mgr_helper_get_active_plane_cnt(
408 struct dc *dc,
409 struct dc_state *context);
410
411
412
413 #endif //__DAL_CLK_MGR_INTERNAL_H__
414