/linux/drivers/dpll/ |
H A D | dpll_netlink.c | 178 struct dpll_device *dpll = ref->dpll; in dpll_msg_add_pin_prio() local 200 struct dpll_device *dpll = ref->dpll; in dpll_msg_add_pin_on_dpll_state() local 222 struct dpll_device *dpll = ref->dpll; in dpll_msg_add_pin_direction() local 242 struct dpll_device *dpll = ref->dpll; in dpll_msg_add_pin_phase_adjust() local 249 dpll, dpll_priv(dpll), in dpll_msg_add_pin_phase_adjust() 702 dpll = ref->dpll; in dpll_pin_freq_set() 714 dpll = ref->dpll; in dpll_pin_freq_set() 733 dpll = ref->dpll; in dpll_pin_freq_set() 892 dpll = ref->dpll; in dpll_pin_phase_adj_set() 905 dpll = ref->dpll; in dpll_pin_phase_adj_set() [all …]
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H A D | dpll_core.c | 164 if (ref->dpll != dpll) in dpll_xa_ref_dpll_add() 179 ref->dpll = dpll; in dpll_xa_ref_dpll_add() 216 if (ref->dpll != dpll) in dpll_xa_ref_dpll_del() 248 dpll = kzalloc(sizeof(*dpll), GFP_KERNEL); in dpll_device_alloc() 249 if (!dpll) in dpll_device_alloc() 256 ret = xa_alloc_cyclic(&dpll_device_xa, &dpll->id, dpll, xa_limit_32b, in dpll_device_alloc() 259 kfree(dpll); in dpll_device_alloc() 264 return dpll; in dpll_device_alloc() 292 ret = dpll; in dpll_device_get() 322 kfree(dpll); in dpll_device_put() [all …]
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H A D | Makefile | 6 obj-$(CONFIG_DPLL) += dpll.o 7 dpll-y += dpll_core.o 8 dpll-y += dpll_netlink.o 9 dpll-y += dpll_nl.o
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H A D | dpll_core.h | 73 struct dpll_device *dpll; member 80 void *dpll_priv(struct dpll_device *dpll); 81 void *dpll_pin_on_dpll_priv(struct dpll_device *dpll, struct dpll_pin *pin); 84 const struct dpll_device_ops *dpll_device_ops(struct dpll_device *dpll);
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H A D | dpll_netlink.h | 7 int dpll_device_create_ntf(struct dpll_device *dpll); 9 int dpll_device_delete_ntf(struct dpll_device *dpll);
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/linux/drivers/gpu/drm/i915/display/ |
H A D | intel_dpll.c | 331 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m() 425 u32 dpll = hw_state->dpll; in i9xx_crtc_clock_get() local 983 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) in i9xx_dpll_compute_fp() argument 985 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp() 990 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp() 1004 u32 dpll; in i9xx_dpll() local 1252 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune() 1904 const struct dpll *clock = &crtc_state->dpll; in vlv_prepare_pll() 2031 const struct dpll *clock = &crtc_state->dpll; in chv_prepare_pll() 2205 const struct dpll *dpll) in vlv_force_pll_on() argument [all …]
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H A D | intel_dpll.h | 11 struct dpll; 24 int i9xx_calc_dpll_params(int refclk, struct dpll *clock); 25 u32 i9xx_dpll_compute_fp(const struct dpll *dpll); 32 const struct dpll *dpll); 42 struct dpll *best_clock); 43 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
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H A D | intel_dpll_mgr.c | 537 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state() 649 hw_state->dpll, in ibx_dump_hw_state() 661 return a->dpll == b->dpll && in ibx_compare_hw_state() 2251 struct dpll *clk_div) in bxt_ddi_hdmi_pll_dividers() 2269 struct dpll *clk_div) in bxt_ddi_dp_pll_dividers() 2361 struct dpll clock; in bxt_ddi_pll_get_freq() 2378 struct dpll clk_div = {}; in bxt_ddi_dp_set_dpll_hw_state() 2389 struct dpll clk_div = {}; in bxt_ddi_hdmi_set_dpll_hw_state() 4529 if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks) in intel_dpll_update_ref_clks() 4581 if (i915->display.dpll.mgr) { in intel_dpll_dump_hw_state() [all …]
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/linux/include/linux/ |
H A D | dpll.h | 32 const struct dpll_device *dpll, void *dpll_priv, 36 const struct dpll_device *dpll, void *dpll_priv, 39 const struct dpll_device *dpll, void *dpll_priv, 52 const struct dpll_device *dpll, 61 const struct dpll_device *dpll, 66 const struct dpll_device *dpll, void *dpll_priv, 69 const struct dpll_device *dpll, void *dpll_priv, 72 const struct dpll_device *dpll, void *dpll_priv, 76 const struct dpll_device *dpll, void *dpll_priv, 80 const struct dpll_device *dpll, void *dpll_priv, [all …]
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/linux/drivers/gpu/drm/gma500/ |
H A D | psb_intel_display.c | 168 dpll |= in psb_intel_crtc_mode_set() 192 dpll |= 3; in psb_intel_crtc_mode_set() 220 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set() 255 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set() 256 REG_READ(map->dpll); in psb_intel_crtc_mode_set() 261 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set() 310 u32 dpll; in psb_intel_crtc_clock_get() local 317 dpll = REG_READ(map->dpll); in psb_intel_crtc_clock_get() 325 dpll = p->dpll; in psb_intel_crtc_clock_get() 342 ffs((dpll & in psb_intel_crtc_clock_get() [all …]
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H A D | oaktrail_crtc.c | 251 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms() 527 dpll |= DPLL_VGA_MODE_DIS; in oaktrail_crtc_mode_set() 530 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set() 533 dpll |= DPLLA_MODE_LVDS; in oaktrail_crtc_mode_set() 541 dpll |= DPLL_DVO_HIGH_SPEED; in oaktrail_crtc_mode_set() 542 dpll |= in oaktrail_crtc_mode_set() 554 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set() 556 if (dpll & DPLL_VCO_ENABLE) { in oaktrail_crtc_mode_set() 559 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_mode_set() 568 REG_WRITE_WITH_AUX(map->dpll, dpll, i); in oaktrail_crtc_mode_set() [all …]
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H A D | cdv_intel_display.c | 665 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set() 722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set() 723 REG_READ(map->dpll); in cdv_intel_crtc_mode_set() 758 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set() 767 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set() 769 REG_READ(map->dpll); in cdv_intel_crtc_mode_set() 842 u32 dpll; in cdv_intel_crtc_clock_get() local 849 dpll = REG_READ(map->dpll); in cdv_intel_crtc_clock_get() 857 dpll = p->dpll; in cdv_intel_crtc_clock_get() 873 ffs((dpll & in cdv_intel_crtc_clock_get() [all …]
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H A D | gma_display.c | 223 temp = REG_READ(map->dpll); in gma_crtc_dpms() 225 REG_WRITE(map->dpll, temp); in gma_crtc_dpms() 226 REG_READ(map->dpll); in gma_crtc_dpms() 230 REG_READ(map->dpll); in gma_crtc_dpms() 234 REG_READ(map->dpll); in gma_crtc_dpms() 311 temp = REG_READ(map->dpll); in gma_crtc_dpms() 314 REG_READ(map->dpll); in gma_crtc_dpms() 595 crtc_state->saveDPLL = REG_READ(map->dpll); in gma_crtc_save() 634 REG_WRITE(map->dpll, in gma_crtc_restore() 636 REG_READ(map->dpll); in gma_crtc_restore() [all …]
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/linux/Documentation/devicetree/bindings/clock/ti/ |
H A D | dpll.txt | 16 "ti,omap3-dpll-clock", 17 "ti,omap3-dpll-core-clock", 18 "ti,omap3-dpll-per-clock", 20 "ti,omap4-dpll-clock", 21 "ti,omap4-dpll-x2-clock", 22 "ti,omap4-dpll-core-clock", 25 "ti,omap5-mpu-dpll-clock", 27 "ti,am3-dpll-j-type-clock", 29 "ti,am3-dpll-clock", 30 "ti,am3-dpll-core-clock", [all …]
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/linux/Documentation/driver-api/ |
H A D | dpll.rst | 4 The Linux kernel dpll subsystem 53 provided for a single dpll device. 115 being directly registered to a dpll device. 180 on a pin and its parent dpll device. If pin-dpll phase offset measurement 182 attribute for each parent dpll device. 210 a dpll. 390 .. kernel-doc:: include/uapi/linux/dpll.h 500 if (IS_ERR(bp->dpll)) { 501 err = PTR_ERR(bp->dpll); 534 dpll_device_put(bp->dpll); [all …]
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/linux/Documentation/netlink/specs/ |
H A D | dpll.yaml | 3 name: dpll 12 working modes a dpll can support, differentiates if and how dpll selects 216 name: dpll 386 attribute-set: dpll 390 pre: dpll-lock-doit 405 attribute-set: dpll 409 pre: dpll-pre-doit 410 post: dpll-post-doit 432 attribute-set: dpll 436 pre: dpll-pre-doit [all …]
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/linux/drivers/net/ethernet/mellanox/mlx5/core/ |
H A D | dpll.c | 11 struct dpll_device *dpll; member 176 const struct dpll_device *dpll, in mlx5_dpll_pin_direction_get() argument 187 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_get() argument 205 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_set() argument 271 dpll_device_change_ntf(mdpll->dpll); in mlx5_dpll_periodic_work() 361 if (IS_ERR(mdpll->dpll)) { in mlx5_dpll_probe() 362 err = PTR_ERR(mdpll->dpll); in mlx5_dpll_probe() 398 dpll_pin_unregister(mdpll->dpll, mdpll->dpll_pin, in mlx5_dpll_probe() 405 dpll_device_put(mdpll->dpll); in mlx5_dpll_probe() 419 dpll_pin_unregister(mdpll->dpll, mdpll->dpll_pin, in mlx5_dpll_remove() [all …]
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/linux/drivers/net/ethernet/intel/ice/ |
H A D | ice_dpll.c | 520 dpll->input_prio[pin->idx] = prio; in ice_dpll_hw_input_prio_set() 1268 dpll_device_change_ntf(d->dpll); in ice_dpll_notify_changes() 1715 pf->dplls.eec.dpll, pf->dplls.pps.dpll); in ice_dpll_init_pins() 1723 pf->dplls.eec.dpll, in ice_dpll_init_pins() 1724 pf->dplls.pps.dpll); in ice_dpll_init_pins() 1739 pf->dplls.eec.dpll); in ice_dpll_init_pins() 1743 pf->dplls.eec.dpll); in ice_dpll_init_pins() 1761 dpll_device_put(d->dpll); in ice_dpll_deinit_dpll() 1786 if (IS_ERR(d->dpll)) { in ice_dpll_init_dpll() 1787 ret = PTR_ERR(d->dpll); in ice_dpll_init_dpll() [all …]
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/linux/Documentation/devicetree/bindings/media/i2c/ |
H A D | adv748x.yaml | 38 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 39 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 40 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 41 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 42 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 43 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 44 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 45 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 46 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] 47 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ] [all …]
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/linux/arch/arm/boot/dts/ti/omap/ |
H A D | dra7xx-clocks.dtsi | 235 dpll_abe_x2_ck: clock-dpll-abe-x2 { 313 dpll_core_x2_ck: clock-dpll-core-x2 { 398 compatible = "ti,omap4-dpll-clock"; 448 compatible = "ti,omap4-dpll-clock"; 498 compatible = "ti,omap4-dpll-clock"; 560 compatible = "ti,omap4-dpll-clock"; 597 compatible = "ti,omap4-dpll-clock"; 688 compatible = "ti,omap4-dpll-clock"; 775 dpll_ddr_x2_ck: clock-dpll-ddr-x2 { 794 dpll_dsp_x2_ck: clock-dpll-dsp-x2 { [all …]
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H A D | am43xx-clocks.dtsi | 231 compatible = "ti,am3-dpll-core-clock"; 237 dpll_core_x2_ck: clock-dpll-core-x2 { 239 compatible = "ti,am3-dpll-x2-clock"; 282 compatible = "ti,am3-dpll-clock"; 288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 { 311 compatible = "ti,am3-dpll-clock"; 331 compatible = "ti,am3-dpll-clock"; 352 compatible = "ti,am3-dpll-j-type-clock"; 635 compatible = "ti,am3-dpll-clock"; 711 dpll_ddr_x2_ck: clock-dpll-ddr-x2 { [all …]
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H A D | am33xx-clocks.dtsi | 191 compatible = "ti,am3-dpll-core-clock"; 197 dpll_core_x2_ck: clock-dpll-core-x2 { 199 compatible = "ti,am3-dpll-x2-clock"; 204 dpll_core_m4_ck: clock-dpll-core-m4@480 { 214 dpll_core_m5_ck: clock-dpll-core-m5@484 { 224 dpll_core_m6_ck: clock-dpll-core-m6@4d8 { 236 compatible = "ti,am3-dpll-clock"; 242 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 { 260 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 { 287 dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 { [all …]
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/linux/arch/arm/mach-omap1/ |
H A D | sram.S | 36 strh r0, [r2] @ set dpll into bypass mode 41 strh r0, [r2] @ write new dpll value 49 lock: ldrh r4, [r2], #0 @ read back dpll value 52 tst r4, #1 << 0 @ dpll rate locked?
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/linux/Documentation/devicetree/bindings/clock/ |
H A D | microchip,sparx5-dpll.yaml | 4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml# 18 const: microchip,sparx5-dpll 46 compatible = "microchip,sparx5-dpll";
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/linux/drivers/ata/ |
H A D | pata_hpt3x2n.c | 312 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local 319 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer() 328 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local 330 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue() 332 flags |= dpll; in hpt3x2n_qc_issue() 335 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
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