Searched refs:index_mask (Results 1 – 12 of 12) sorted by relevance
69 u32 index_mask; member97 return (index + 1) & q->index_mask; in queue_next_index()159 return ((prod - cons) & q->index_mask) == 0; in queue_empty()167 return ((prod + 1 - cons) & q->index_mask) == 0; in queue_full()176 return (prod - cons) & q->index_mask; in queue_count()194 prod = (prod + 1) & q->index_mask; in queue_advance_producer()202 prod = (prod + 1) & q->index_mask; in queue_advance_producer()223 cons = (q->index + 1) & q->index_mask; in queue_advance_consumer()243 cons = (cons + 1) & q->index_mask; in queue_advance_consumer()268 return q->buf->data + ((index & q->index_mask) in queue_addr_from_index()[all …]
85 q->index_mask = num_slots - 1; in rxe_queue_init()94 q->buf->index_mask = q->index_mask; in rxe_queue_init()125 while ((prod - cons) & q->index_mask) { in resize_finish()
137 if (attr->srq_limit > srq->rq.queue->buf->index_mask) { in rxe_srq_chk_attr()140 srq->rq.queue->buf->index_mask); in rxe_srq_chk_attr()
478 attr->max_wr = srq->rq.queue->buf->index_mask; in rxe_query_srq()
84 u32 elem_size, index_mask, max_entries; in array_map_alloc() local101 index_mask = mask64; in array_map_alloc()106 max_entries = index_mask + 1; in array_map_alloc()142 array->index_mask = index_mask; in array_map_alloc()221 *insn++ = BPF_ALU32_IMM(BPF_AND, ret, array->index_mask); in array_map_gen_lookup()312 pptr = array->pptrs[index & array->index_mask]; in bpf_percpu_array_copy()371 (u64)array->elem_size * (index & array->index_mask); in array_map_update_elem()410 pptr = array->pptrs[index & array->index_mask]; in bpf_percpu_array_update()513 pptr = array->pptrs[index & array->index_mask]; in percpu_array_map_seq_show_elem()601 index = info->index & array->index_mask; in bpf_array_map_seq_start()[all …]
76 inner_array_meta->index_mask = inner_array->index_mask; in bpf_map_meta_alloc()
20173 map)->index_mask); in do_misc_fixups()
46 uint32_t index_mask = 0; in radeon_encoder_clones() local51 return index_mask; in radeon_encoder_clones()54 return index_mask; in radeon_encoder_clones()57 return index_mask; in radeon_encoder_clones()72 index_mask |= (1 << count); in radeon_encoder_clones()74 return index_mask; in radeon_encoder_clones()
545 int index_mask = 0; in gma_connector_clones() local552 index_mask |= (1 << entry); in gma_connector_clones()557 return index_mask; in gma_connector_clones()
400 u32 index_mask = 0, index_clear = 0; in tsens_set_interrupt_v2() local411 index_mask = UP_INT_MASK_0 + hw_id; in tsens_set_interrupt_v2()415 index_mask = LOW_INT_MASK_0 + hw_id; in tsens_set_interrupt_v2()419 index_mask = CRIT_INT_MASK_0 + hw_id; in tsens_set_interrupt_v2()425 regmap_field_write(priv->rf[index_mask], 0); in tsens_set_interrupt_v2()427 regmap_field_write(priv->rf[index_mask], 1); in tsens_set_interrupt_v2()
222 __u32 index_mask; member
1892 u32 index_mask; member