Home
last modified time | relevance | path

Searched refs:invalidate (Results 1 – 25 of 141) sorted by relevance

123456

/linux/arch/arm/mm/
H A Dcache-v6.S43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
152 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
157 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
[all …]
H A Dcache-fa.S45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
66 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
68 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
69 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
92 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
93 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
98 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
133 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
138 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
160 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
H A Dproc-arm926.S72 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
75 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
135 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
141 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
163 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
166 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
213 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
238 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
306 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
H A Dproc-arm925.S112 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
147 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
169 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
178 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
200 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
203 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
250 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
275 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
343 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
401 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
[all …]
H A Dproc-mohawk.S65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
67 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
96 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
143 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
146 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
186 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
211 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
324 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
386 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
[all …]
H A Dproc-arm922.S82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
142 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
165 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
203 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
228 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
252 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
346 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
360 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
[all …]
H A Dcache-v4wt.S49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
71 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
72 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
91 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
93 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
128 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
147 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
165 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
H A Dproc-arm920.S80 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
83 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
111 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
163 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
201 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
226 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
250 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
343 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
357 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
[all …]
H A Dproc-fa526.S61 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
108 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
110 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
112 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
113 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
117 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
143 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
146 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
148 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
[all …]
H A Dproc-arm1022.S88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
155 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
185 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
225 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
278 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
388 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
392 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
417 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
[all …]
H A Dproc-arm1026.S88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
150 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
220 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
273 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
378 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
382 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
407 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
[all …]
H A Dproc-arm946.S90 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
144 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
147 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
195 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
221 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
290 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
337 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
H A Dproc-arm1020e.S88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
186 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
226 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
279 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
396 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
400 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
425 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
[all …]
H A Dtlb-v7.S50 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
52 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
54 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
79 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
81 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
83 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
H A Dtlb-v6.S49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
51 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
79 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
80 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
82 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
H A Dproc-arm1020.S88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
157 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
189 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
231 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
289 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
411 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
415 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
442 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
[all …]
H A Dproc-feroceon.S98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
131 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
164 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
186 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
189 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
229 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
255 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
270 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
295 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
H A Dproc-xsc3.S69 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
153 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
201 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
206 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
283 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
374 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
442 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
[all …]
H A Dcache-v4wb.S59 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
78 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
113 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
119 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
178 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
200 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
H A Dtlb-v4wb.S39 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
42 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
63 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
64 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
H A Dcache-v7.S87 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
166 mcr p15, 0, r5, c7, c14, 2 @ clean & invalidate by set/way
202 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
218 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
306 USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line
311 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable
312 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB
376 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
381 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line
384 mcrlo p15, 0, r0, c7, c6, 1 @ invalidate D / U line
[all …]
H A Dtlb-v4wbi.S41 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
42 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
54 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
55 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
H A Dproc-sa1100.S76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
152 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
154 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
194 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
208 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
211 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dproc-sa110.S68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
143 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
169 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
172 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dhv_vhca.c36 void (*invalidate)(struct mlx5_hv_vhca_agent *agent, member
83 if (!agent || !agent->invalidate) in mlx5_hv_vhca_invalidate_work()
89 agent->invalidate(agent, hwork->block_mask); in mlx5_hv_vhca_invalidate_work()
256 void (*invalidate)(struct mlx5_hv_vhca_agent*, in mlx5_hv_vhca_agent_create()
284 agent->invalidate = invalidate; in mlx5_hv_vhca_agent_create()

123456