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Searched refs:mmD4VGA_CONTROL (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dce120/
H A Ddce120_timing_generator.c404 offset = mmD4VGA_CONTROL - mmD1VGA_CONTROL; in dce120_timing_generator_disable_vga()
/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator.c1816 addr = mmD4VGA_CONTROL; in dce110_timing_generator_disable_vga()
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h1044 #define mmD4VGA_CONTROL 0x00F9 macro
H A Ddce_8_0_d.h5147 #define mmD4VGA_CONTROL 0xf9 macro
H A Ddce_10_0_d.h6030 #define mmD4VGA_CONTROL 0xf9 macro
H A Ddce_11_0_d.h6107 #define mmD4VGA_CONTROL 0xf9 macro
H A Ddce_11_2_d.h7781 #define mmD4VGA_CONTROL 0xf9 macro
H A Ddce_12_0_offset.h642 #define mmD4VGA_CONTROL … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v6_0.c1801 mmD4VGA_CONTROL,
H A Ddce_v8_0.c1761 mmD4VGA_CONTROL,
H A Ddce_v10_0.c1814 mmD4VGA_CONTROL,
H A Ddce_v11_0.c1864 mmD4VGA_CONTROL,
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h105 #define mmD4VGA_CONTROL … macro
H A Ddcn_3_0_1_offset.h188 #define mmD4VGA_CONTROL … macro
H A Ddcn_1_0_offset.h452 #define mmD4VGA_CONTROL … macro
H A Ddcn_2_1_0_offset.h140 #define mmD4VGA_CONTROL … macro
H A Ddcn_3_0_2_offset.h120 #define mmD4VGA_CONTROL … macro
H A Ddcn_2_0_0_offset.h120 #define mmD4VGA_CONTROL … macro
H A Ddcn_3_0_0_offset.h102 #define mmD4VGA_CONTROL … macro