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Searched refs:mmDP0_DP_MSE_SAT1 (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3142 #define mmDP0_DP_MSE_SAT1 0x1CE5 macro
H A Ddce_8_0_d.h4124 #define mmDP0_DP_MSE_SAT1 0x1ce5 macro
H A Ddce_10_0_d.h4756 #define mmDP0_DP_MSE_SAT1 0x4ad3 macro
H A Ddce_11_0_d.h4817 #define mmDP0_DP_MSE_SAT1 0x4ad3 macro
H A Ddce_11_2_d.h6049 #define mmDP0_DP_MSE_SAT1 0x4ad3 macro
H A Ddce_12_0_offset.h10288 #define mmDP0_DP_MSE_SAT1 … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h5552 #define mmDP0_DP_MSE_SAT1 … macro
H A Ddcn_3_0_3_offset.h5046 #define mmDP0_DP_MSE_SAT1 … macro
H A Ddcn_3_0_1_offset.h8008 #define mmDP0_DP_MSE_SAT1 … macro
H A Ddcn_1_0_offset.h8437 #define mmDP0_DP_MSE_SAT1 … macro
H A Ddcn_2_1_0_offset.h9941 #define mmDP0_DP_MSE_SAT1 … macro
H A Ddcn_3_0_2_offset.h9640 #define mmDP0_DP_MSE_SAT1 … macro
H A Ddcn_2_0_0_offset.h11034 #define mmDP0_DP_MSE_SAT1 … macro
H A Ddcn_3_0_0_offset.h10784 #define mmDP0_DP_MSE_SAT1 … macro