1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include "amdgpu.h"
30 #include "amdgpu_gfx.h"
31 #include "amdgpu_psp.h"
32 #include "nv.h"
33 #include "nvd.h"
34
35 #include "gc/gc_10_1_0_offset.h"
36 #include "gc/gc_10_1_0_sh_mask.h"
37 #include "smuio/smuio_11_0_0_offset.h"
38 #include "smuio/smuio_11_0_0_sh_mask.h"
39 #include "navi10_enum.h"
40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
41
42 #include "soc15.h"
43 #include "soc15d.h"
44 #include "soc15_common.h"
45 #include "clearstate_gfx10.h"
46 #include "v10_structs.h"
47 #include "gfx_v10_0.h"
48 #include "nbio_v2_3.h"
49
50 /*
51 * Navi10 has two graphic rings to share each graphic pipe.
52 * 1. Primary ring
53 * 2. Async ring
54 */
55 #define GFX10_NUM_GFX_RINGS_NV1X 1
56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2
57 #define GFX10_MEC_HPD_SIZE 2048
58
59 #define F32_CE_PROGRAM_RAM_SIZE 65536
60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
61
62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087
63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
68
69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8
70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L
71
72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006
73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1
74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007
75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1
76
77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55
78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0
79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0
80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1
81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1
82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1
83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec
84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0
85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1
86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2
88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3
90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4
92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0
93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5
94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0
95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6
96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a
98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L
99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL
100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2
101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL
102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
104
105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish 0x0105
106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1
107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish 0x0106
108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1
109
110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025
111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026
113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1
114
115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d
116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1
117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e
118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1
119
120 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261
123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f
125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1
126 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e
127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1
128 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241
129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1
130 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250
131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1
132 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240
133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1
134 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440
135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1
136 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580
137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0
138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL
139
140 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814
141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1
142 #define mmCP_HYP_PFP_UCODE_DATA 0x5815
143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1
144 #define mmCP_HYP_CE_UCODE_ADDR 0x5818
145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1
146 #define mmCP_HYP_CE_UCODE_DATA 0x5819
147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1
148 #define mmCP_HYP_ME_UCODE_ADDR 0x5816
149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1
150 #define mmCP_HYP_ME_UCODE_DATA 0x5817
151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1
152
153 #define mmCPG_PSP_DEBUG 0x5c10
154 #define mmCPG_PSP_DEBUG_BASE_IDX 1
155 #define mmCPC_PSP_DEBUG 0x5c11
156 #define mmCPC_PSP_DEBUG_BASE_IDX 1
157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L
158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L
159
160 //CC_GC_SA_UNIT_DISABLE
161 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9
162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0
163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8
164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L
165 //GC_USER_SA_UNIT_DISABLE
166 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea
167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0
168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8
169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L
170 //PA_SC_ENHANCE_3
171 #define mmPA_SC_ENHANCE_3 0x1085
172 #define mmPA_SC_ENHANCE_3_BASE_IDX 0
173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L
175
176 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c
177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1
178
179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3
180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db
182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
183
184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030
185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0
186
187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5
188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1
189
190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
192 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
196
197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
204 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
208
209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
211 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
215
216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
222
223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
229
230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
236
237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
243
244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
250
251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
257
258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
264
265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
271
272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
278
279 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
280 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
281 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
282 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
283 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
284 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
285 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
286 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
287 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
288 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
289 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
290 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
291 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
292 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
293 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
294 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
295 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
296 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
297 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
298 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
299 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
300 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
301 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
302 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
303 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
304 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
305 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
306 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
307 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
308 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
309 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
310 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
311 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
312 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
313 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
314 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
315 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
316 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
317 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
318 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
319 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
320 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
321 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
322 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
323 SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
324 SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
325 SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
326 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
327 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
328 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
329 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
330 SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
331 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
332 SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
333 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
334 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
335 SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
336 SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
337 SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
338 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
339 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
340 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
341 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
342 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
343 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
344 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
345 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
346 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
347 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
348 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
349 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
350 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
351 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
352 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
353 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
354 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
355 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
356 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
357 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
358 SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
359 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
360 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
361 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
362 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
363 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
364 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
365 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
366 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
367 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
368 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
369 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST)
370 };
371
372 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
413 };
414
415 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = {
416 /* Pending on emulation bring up */
417 };
418
419 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = {
420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1472 };
1473
1474 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = {
1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1513 };
1514
1515 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = {
1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1558 };
1559
1560 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = {
1561 /* Pending on emulation bring up */
1562 };
1563
1564 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = {
1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2185 };
2186
2187 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = {
2188 /* Pending on emulation bring up */
2189 };
2190
2191 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = {
2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3244 };
3245
3246 static const struct soc15_reg_golden golden_settings_gc_10_3[] = {
3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3290 };
3291
3292 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = {
3293 /* Pending on emulation bring up */
3294 };
3295
3296 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = {
3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3338
3339 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3341 };
3342
3343 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {
3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3368
3369 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3371 };
3372
3373 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {
3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3394 };
3395
3396 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {
3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020)
3433 };
3434
3435 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3468 };
3469
3470 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3505 };
3506
3507 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {
3508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3530 };
3531
3532 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3555 };
3556
3557 #define DEFAULT_SH_MEM_CONFIG \
3558 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3559 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3560 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3561 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3562
3563 /* TODO: pending on golden setting value of gb address config */
3564 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3565
3566 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3567 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3568 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3569 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3570 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3571 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3572 struct amdgpu_cu_info *cu_info);
3573 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3574 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3575 u32 sh_num, u32 instance, int xcc_id);
3576 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3577
3578 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3579 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3580 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3581 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3582 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3583 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3584 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3585 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3586 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3587 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3588 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3589 uint16_t pasid, uint32_t flush_type,
3590 bool all_hub, uint8_t dst_sel);
3591 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
3592 unsigned int vmid);
3593
3594 static int gfx_v10_0_set_powergating_state(void *handle,
3595 enum amd_powergating_state state);
gfx10_kiq_set_resources(struct amdgpu_ring * kiq_ring,uint64_t queue_mask)3596 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3597 {
3598 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3599 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3600 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3601 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3602 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3603 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3604 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3605 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3606 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3607 }
3608
gfx10_kiq_map_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring)3609 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3610 struct amdgpu_ring *ring)
3611 {
3612 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3613 uint64_t wptr_addr = ring->wptr_gpu_addr;
3614 uint32_t eng_sel = 0;
3615
3616 switch (ring->funcs->type) {
3617 case AMDGPU_RING_TYPE_COMPUTE:
3618 eng_sel = 0;
3619 break;
3620 case AMDGPU_RING_TYPE_GFX:
3621 eng_sel = 4;
3622 break;
3623 case AMDGPU_RING_TYPE_MES:
3624 eng_sel = 5;
3625 break;
3626 default:
3627 WARN_ON(1);
3628 }
3629
3630 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3631 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3632 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3633 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3634 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3635 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3636 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3637 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3638 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3639 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3640 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3641 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3642 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3643 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3644 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3645 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3646 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3647 }
3648
gfx10_kiq_unmap_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,enum amdgpu_unmap_queues_action action,u64 gpu_addr,u64 seq)3649 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3650 struct amdgpu_ring *ring,
3651 enum amdgpu_unmap_queues_action action,
3652 u64 gpu_addr, u64 seq)
3653 {
3654 struct amdgpu_device *adev = kiq_ring->adev;
3655 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3656
3657 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
3658 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
3659 return;
3660 }
3661
3662 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3663 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3664 PACKET3_UNMAP_QUEUES_ACTION(action) |
3665 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3666 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3667 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3668 amdgpu_ring_write(kiq_ring,
3669 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3670
3671 if (action == PREEMPT_QUEUES_NO_UNMAP) {
3672 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3673 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3674 amdgpu_ring_write(kiq_ring, seq);
3675 } else {
3676 amdgpu_ring_write(kiq_ring, 0);
3677 amdgpu_ring_write(kiq_ring, 0);
3678 amdgpu_ring_write(kiq_ring, 0);
3679 }
3680 }
3681
gfx10_kiq_query_status(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,u64 addr,u64 seq)3682 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3683 struct amdgpu_ring *ring,
3684 u64 addr,
3685 u64 seq)
3686 {
3687 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3688
3689 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3690 amdgpu_ring_write(kiq_ring,
3691 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3692 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3693 PACKET3_QUERY_STATUS_COMMAND(2));
3694 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3695 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3696 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3697 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3698 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3699 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3700 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3701 }
3702
gfx10_kiq_invalidate_tlbs(struct amdgpu_ring * kiq_ring,uint16_t pasid,uint32_t flush_type,bool all_hub)3703 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3704 uint16_t pasid, uint32_t flush_type,
3705 bool all_hub)
3706 {
3707 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3708 }
3709
3710 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3711 .kiq_set_resources = gfx10_kiq_set_resources,
3712 .kiq_map_queues = gfx10_kiq_map_queues,
3713 .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3714 .kiq_query_status = gfx10_kiq_query_status,
3715 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3716 .set_resources_size = 8,
3717 .map_queues_size = 7,
3718 .unmap_queues_size = 6,
3719 .query_status_size = 7,
3720 .invalidate_tlbs_size = 2,
3721 };
3722
gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device * adev)3723 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3724 {
3725 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs;
3726 }
3727
gfx_v10_0_init_spm_golden_registers(struct amdgpu_device * adev)3728 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3729 {
3730 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3731 case IP_VERSION(10, 1, 10):
3732 soc15_program_register_sequence(adev,
3733 golden_settings_gc_rlc_spm_10_0_nv10,
3734 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3735 break;
3736 case IP_VERSION(10, 1, 1):
3737 soc15_program_register_sequence(adev,
3738 golden_settings_gc_rlc_spm_10_1_nv14,
3739 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3740 break;
3741 case IP_VERSION(10, 1, 2):
3742 soc15_program_register_sequence(adev,
3743 golden_settings_gc_rlc_spm_10_1_2_nv12,
3744 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3745 break;
3746 default:
3747 break;
3748 }
3749 }
3750
gfx_v10_0_init_golden_registers(struct amdgpu_device * adev)3751 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3752 {
3753 if (amdgpu_sriov_vf(adev))
3754 return;
3755
3756 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3757 case IP_VERSION(10, 1, 10):
3758 soc15_program_register_sequence(adev,
3759 golden_settings_gc_10_1,
3760 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3761 soc15_program_register_sequence(adev,
3762 golden_settings_gc_10_0_nv10,
3763 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3764 break;
3765 case IP_VERSION(10, 1, 1):
3766 soc15_program_register_sequence(adev,
3767 golden_settings_gc_10_1_1,
3768 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3769 soc15_program_register_sequence(adev,
3770 golden_settings_gc_10_1_nv14,
3771 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3772 break;
3773 case IP_VERSION(10, 1, 2):
3774 soc15_program_register_sequence(adev,
3775 golden_settings_gc_10_1_2,
3776 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3777 soc15_program_register_sequence(adev,
3778 golden_settings_gc_10_1_2_nv12,
3779 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3780 break;
3781 case IP_VERSION(10, 3, 0):
3782 soc15_program_register_sequence(adev,
3783 golden_settings_gc_10_3,
3784 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3785 soc15_program_register_sequence(adev,
3786 golden_settings_gc_10_3_sienna_cichlid,
3787 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3788 break;
3789 case IP_VERSION(10, 3, 2):
3790 soc15_program_register_sequence(adev,
3791 golden_settings_gc_10_3_2,
3792 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3793 break;
3794 case IP_VERSION(10, 3, 1):
3795 soc15_program_register_sequence(adev,
3796 golden_settings_gc_10_3_vangogh,
3797 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3798 break;
3799 case IP_VERSION(10, 3, 3):
3800 soc15_program_register_sequence(adev,
3801 golden_settings_gc_10_3_3,
3802 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3803 break;
3804 case IP_VERSION(10, 3, 4):
3805 soc15_program_register_sequence(adev,
3806 golden_settings_gc_10_3_4,
3807 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3808 break;
3809 case IP_VERSION(10, 3, 5):
3810 soc15_program_register_sequence(adev,
3811 golden_settings_gc_10_3_5,
3812 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3813 break;
3814 case IP_VERSION(10, 1, 3):
3815 case IP_VERSION(10, 1, 4):
3816 soc15_program_register_sequence(adev,
3817 golden_settings_gc_10_0_cyan_skillfish,
3818 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3819 break;
3820 case IP_VERSION(10, 3, 6):
3821 soc15_program_register_sequence(adev,
3822 golden_settings_gc_10_3_6,
3823 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3824 break;
3825 case IP_VERSION(10, 3, 7):
3826 soc15_program_register_sequence(adev,
3827 golden_settings_gc_10_3_7,
3828 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3829 break;
3830 default:
3831 break;
3832 }
3833 gfx_v10_0_init_spm_golden_registers(adev);
3834 }
3835
gfx_v10_0_write_data_to_reg(struct amdgpu_ring * ring,int eng_sel,bool wc,uint32_t reg,uint32_t val)3836 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3837 bool wc, uint32_t reg, uint32_t val)
3838 {
3839 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3840 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3841 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3842 amdgpu_ring_write(ring, reg);
3843 amdgpu_ring_write(ring, 0);
3844 amdgpu_ring_write(ring, val);
3845 }
3846
gfx_v10_0_wait_reg_mem(struct amdgpu_ring * ring,int eng_sel,int mem_space,int opt,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)3847 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3848 int mem_space, int opt, uint32_t addr0,
3849 uint32_t addr1, uint32_t ref, uint32_t mask,
3850 uint32_t inv)
3851 {
3852 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3853 amdgpu_ring_write(ring,
3854 /* memory (1) or register (0) */
3855 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3856 WAIT_REG_MEM_OPERATION(opt) | /* wait */
3857 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3858 WAIT_REG_MEM_ENGINE(eng_sel)));
3859
3860 if (mem_space)
3861 BUG_ON(addr0 & 0x3); /* Dword align */
3862 amdgpu_ring_write(ring, addr0);
3863 amdgpu_ring_write(ring, addr1);
3864 amdgpu_ring_write(ring, ref);
3865 amdgpu_ring_write(ring, mask);
3866 amdgpu_ring_write(ring, inv); /* poll interval */
3867 }
3868
gfx_v10_0_ring_test_ring(struct amdgpu_ring * ring)3869 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3870 {
3871 struct amdgpu_device *adev = ring->adev;
3872 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3873 uint32_t tmp = 0;
3874 unsigned int i;
3875 int r;
3876
3877 WREG32(scratch, 0xCAFEDEAD);
3878 r = amdgpu_ring_alloc(ring, 3);
3879 if (r) {
3880 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3881 ring->idx, r);
3882 return r;
3883 }
3884
3885 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3886 amdgpu_ring_write(ring, scratch -
3887 PACKET3_SET_UCONFIG_REG_START);
3888 amdgpu_ring_write(ring, 0xDEADBEEF);
3889 amdgpu_ring_commit(ring);
3890
3891 for (i = 0; i < adev->usec_timeout; i++) {
3892 tmp = RREG32(scratch);
3893 if (tmp == 0xDEADBEEF)
3894 break;
3895 if (amdgpu_emu_mode == 1)
3896 msleep(1);
3897 else
3898 udelay(1);
3899 }
3900
3901 if (i >= adev->usec_timeout)
3902 r = -ETIMEDOUT;
3903
3904 return r;
3905 }
3906
gfx_v10_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)3907 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3908 {
3909 struct amdgpu_device *adev = ring->adev;
3910 struct amdgpu_ib ib;
3911 struct dma_fence *f = NULL;
3912 unsigned int index;
3913 uint64_t gpu_addr;
3914 volatile uint32_t *cpu_ptr;
3915 long r;
3916
3917 memset(&ib, 0, sizeof(ib));
3918
3919 if (ring->is_mes_queue) {
3920 uint32_t padding, offset;
3921
3922 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
3923 padding = amdgpu_mes_ctx_get_offs(ring,
3924 AMDGPU_MES_CTX_PADDING_OFFS);
3925
3926 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
3927 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
3928
3929 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
3930 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
3931 *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
3932 } else {
3933 r = amdgpu_device_wb_get(adev, &index);
3934 if (r)
3935 return r;
3936
3937 gpu_addr = adev->wb.gpu_addr + (index * 4);
3938 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3939 cpu_ptr = &adev->wb.wb[index];
3940
3941 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
3942 if (r) {
3943 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
3944 goto err1;
3945 }
3946 }
3947
3948 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3949 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3950 ib.ptr[2] = lower_32_bits(gpu_addr);
3951 ib.ptr[3] = upper_32_bits(gpu_addr);
3952 ib.ptr[4] = 0xDEADBEEF;
3953 ib.length_dw = 5;
3954
3955 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3956 if (r)
3957 goto err2;
3958
3959 r = dma_fence_wait_timeout(f, false, timeout);
3960 if (r == 0) {
3961 r = -ETIMEDOUT;
3962 goto err2;
3963 } else if (r < 0) {
3964 goto err2;
3965 }
3966
3967 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
3968 r = 0;
3969 else
3970 r = -EINVAL;
3971 err2:
3972 if (!ring->is_mes_queue)
3973 amdgpu_ib_free(adev, &ib, NULL);
3974 dma_fence_put(f);
3975 err1:
3976 if (!ring->is_mes_queue)
3977 amdgpu_device_wb_free(adev, index);
3978 return r;
3979 }
3980
gfx_v10_0_free_microcode(struct amdgpu_device * adev)3981 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3982 {
3983 amdgpu_ucode_release(&adev->gfx.pfp_fw);
3984 amdgpu_ucode_release(&adev->gfx.me_fw);
3985 amdgpu_ucode_release(&adev->gfx.ce_fw);
3986 amdgpu_ucode_release(&adev->gfx.rlc_fw);
3987 amdgpu_ucode_release(&adev->gfx.mec_fw);
3988 amdgpu_ucode_release(&adev->gfx.mec2_fw);
3989
3990 kfree(adev->gfx.rlc.register_list_format);
3991 }
3992
gfx_v10_0_check_fw_write_wait(struct amdgpu_device * adev)3993 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3994 {
3995 adev->gfx.cp_fw_write_wait = false;
3996
3997 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3998 case IP_VERSION(10, 1, 10):
3999 case IP_VERSION(10, 1, 2):
4000 case IP_VERSION(10, 1, 1):
4001 case IP_VERSION(10, 1, 3):
4002 case IP_VERSION(10, 1, 4):
4003 if ((adev->gfx.me_fw_version >= 0x00000046) &&
4004 (adev->gfx.me_feature_version >= 27) &&
4005 (adev->gfx.pfp_fw_version >= 0x00000068) &&
4006 (adev->gfx.pfp_feature_version >= 27) &&
4007 (adev->gfx.mec_fw_version >= 0x0000005b) &&
4008 (adev->gfx.mec_feature_version >= 27))
4009 adev->gfx.cp_fw_write_wait = true;
4010 break;
4011 case IP_VERSION(10, 3, 0):
4012 case IP_VERSION(10, 3, 2):
4013 case IP_VERSION(10, 3, 1):
4014 case IP_VERSION(10, 3, 4):
4015 case IP_VERSION(10, 3, 5):
4016 case IP_VERSION(10, 3, 6):
4017 case IP_VERSION(10, 3, 3):
4018 case IP_VERSION(10, 3, 7):
4019 adev->gfx.cp_fw_write_wait = true;
4020 break;
4021 default:
4022 break;
4023 }
4024
4025 if (!adev->gfx.cp_fw_write_wait)
4026 DRM_WARN_ONCE("CP firmware version too old, please update!");
4027 }
4028
gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device * adev)4029 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
4030 {
4031 bool ret = false;
4032
4033 switch (adev->pdev->revision) {
4034 case 0xc2:
4035 case 0xc3:
4036 ret = true;
4037 break;
4038 default:
4039 ret = false;
4040 break;
4041 }
4042
4043 return ret;
4044 }
4045
gfx_v10_0_check_gfxoff_flag(struct amdgpu_device * adev)4046 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
4047 {
4048 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4049 case IP_VERSION(10, 1, 10):
4050 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
4051 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
4052 break;
4053 default:
4054 break;
4055 }
4056 }
4057
gfx_v10_0_init_microcode(struct amdgpu_device * adev)4058 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
4059 {
4060 char fw_name[53];
4061 char ucode_prefix[30];
4062 const char *wks = "";
4063 int err;
4064 const struct rlc_firmware_header_v2_0 *rlc_hdr;
4065 uint16_t version_major;
4066 uint16_t version_minor;
4067
4068 DRM_DEBUG("\n");
4069
4070 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) &&
4071 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00)))
4072 wks = "_wks";
4073 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
4074
4075 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);
4076 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
4077 if (err)
4078 goto out;
4079 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
4080
4081 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks);
4082 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
4083 if (err)
4084 goto out;
4085 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
4086
4087 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks);
4088 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
4089 if (err)
4090 goto out;
4091 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
4092
4093 if (!amdgpu_sriov_vf(adev)) {
4094 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
4095 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4096 if (err)
4097 goto out;
4098
4099 /* don't validate this firmware. There are apparently firmwares
4100 * in the wild with incorrect size in the header
4101 */
4102 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4103 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4104 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4105 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
4106 if (err)
4107 goto out;
4108 }
4109
4110 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks);
4111 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
4112 if (err)
4113 goto out;
4114 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
4115 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
4116
4117 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);
4118 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
4119 if (!err) {
4120 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
4121 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4122 } else {
4123 err = 0;
4124 adev->gfx.mec2_fw = NULL;
4125 }
4126
4127 gfx_v10_0_check_fw_write_wait(adev);
4128 out:
4129 if (err) {
4130 amdgpu_ucode_release(&adev->gfx.pfp_fw);
4131 amdgpu_ucode_release(&adev->gfx.me_fw);
4132 amdgpu_ucode_release(&adev->gfx.ce_fw);
4133 amdgpu_ucode_release(&adev->gfx.rlc_fw);
4134 amdgpu_ucode_release(&adev->gfx.mec_fw);
4135 amdgpu_ucode_release(&adev->gfx.mec2_fw);
4136 }
4137
4138 gfx_v10_0_check_gfxoff_flag(adev);
4139
4140 return err;
4141 }
4142
gfx_v10_0_get_csb_size(struct amdgpu_device * adev)4143 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4144 {
4145 u32 count = 0;
4146 const struct cs_section_def *sect = NULL;
4147 const struct cs_extent_def *ext = NULL;
4148
4149 /* begin clear state */
4150 count += 2;
4151 /* context control state */
4152 count += 3;
4153
4154 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4155 for (ext = sect->section; ext->extent != NULL; ++ext) {
4156 if (sect->id == SECT_CONTEXT)
4157 count += 2 + ext->reg_count;
4158 else
4159 return 0;
4160 }
4161 }
4162
4163 /* set PA_SC_TILE_STEERING_OVERRIDE */
4164 count += 3;
4165 /* end clear state */
4166 count += 2;
4167 /* clear state */
4168 count += 2;
4169
4170 return count;
4171 }
4172
gfx_v10_0_get_csb_buffer(struct amdgpu_device * adev,volatile u32 * buffer)4173 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4174 volatile u32 *buffer)
4175 {
4176 u32 count = 0, i;
4177 const struct cs_section_def *sect = NULL;
4178 const struct cs_extent_def *ext = NULL;
4179 int ctx_reg_offset;
4180
4181 if (adev->gfx.rlc.cs_data == NULL)
4182 return;
4183 if (buffer == NULL)
4184 return;
4185
4186 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4187 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4188
4189 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4190 buffer[count++] = cpu_to_le32(0x80000000);
4191 buffer[count++] = cpu_to_le32(0x80000000);
4192
4193 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4194 for (ext = sect->section; ext->extent != NULL; ++ext) {
4195 if (sect->id == SECT_CONTEXT) {
4196 buffer[count++] =
4197 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4198 buffer[count++] = cpu_to_le32(ext->reg_index -
4199 PACKET3_SET_CONTEXT_REG_START);
4200 for (i = 0; i < ext->reg_count; i++)
4201 buffer[count++] = cpu_to_le32(ext->extent[i]);
4202 } else {
4203 return;
4204 }
4205 }
4206 }
4207
4208 ctx_reg_offset =
4209 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4210 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4211 buffer[count++] = cpu_to_le32(ctx_reg_offset);
4212 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4213
4214 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4215 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4216
4217 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4218 buffer[count++] = cpu_to_le32(0);
4219 }
4220
gfx_v10_0_rlc_fini(struct amdgpu_device * adev)4221 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4222 {
4223 /* clear state block */
4224 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4225 &adev->gfx.rlc.clear_state_gpu_addr,
4226 (void **)&adev->gfx.rlc.cs_ptr);
4227
4228 /* jump table block */
4229 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4230 &adev->gfx.rlc.cp_table_gpu_addr,
4231 (void **)&adev->gfx.rlc.cp_table_ptr);
4232 }
4233
gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device * adev)4234 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4235 {
4236 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4237
4238 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
4239 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4240 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4241 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4242 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4243 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4244 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4245 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4246 case IP_VERSION(10, 3, 0):
4247 reg_access_ctrl->spare_int =
4248 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4249 break;
4250 default:
4251 reg_access_ctrl->spare_int =
4252 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4253 break;
4254 }
4255 adev->gfx.rlc.rlcg_reg_access_supported = true;
4256 }
4257
gfx_v10_0_rlc_init(struct amdgpu_device * adev)4258 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4259 {
4260 const struct cs_section_def *cs_data;
4261 int r;
4262
4263 adev->gfx.rlc.cs_data = gfx10_cs_data;
4264
4265 cs_data = adev->gfx.rlc.cs_data;
4266
4267 if (cs_data) {
4268 /* init clear state block */
4269 r = amdgpu_gfx_rlc_init_csb(adev);
4270 if (r)
4271 return r;
4272 }
4273
4274 return 0;
4275 }
4276
gfx_v10_0_mec_fini(struct amdgpu_device * adev)4277 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4278 {
4279 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4280 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4281 }
4282
gfx_v10_0_me_init(struct amdgpu_device * adev)4283 static void gfx_v10_0_me_init(struct amdgpu_device *adev)
4284 {
4285 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4286
4287 amdgpu_gfx_graphics_queue_acquire(adev);
4288 }
4289
gfx_v10_0_mec_init(struct amdgpu_device * adev)4290 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4291 {
4292 int r;
4293 u32 *hpd;
4294 const __le32 *fw_data = NULL;
4295 unsigned int fw_size;
4296 u32 *fw = NULL;
4297 size_t mec_hpd_size;
4298
4299 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4300
4301 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4302
4303 /* take ownership of the relevant compute queues */
4304 amdgpu_gfx_compute_queue_acquire(adev);
4305 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4306
4307 if (mec_hpd_size) {
4308 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4309 AMDGPU_GEM_DOMAIN_GTT,
4310 &adev->gfx.mec.hpd_eop_obj,
4311 &adev->gfx.mec.hpd_eop_gpu_addr,
4312 (void **)&hpd);
4313 if (r) {
4314 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4315 gfx_v10_0_mec_fini(adev);
4316 return r;
4317 }
4318
4319 memset(hpd, 0, mec_hpd_size);
4320
4321 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4322 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4323 }
4324
4325 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4326 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4327
4328 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4329 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4330 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4331
4332 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4333 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4334 &adev->gfx.mec.mec_fw_obj,
4335 &adev->gfx.mec.mec_fw_gpu_addr,
4336 (void **)&fw);
4337 if (r) {
4338 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4339 gfx_v10_0_mec_fini(adev);
4340 return r;
4341 }
4342
4343 memcpy(fw, fw_data, fw_size);
4344
4345 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4346 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4347 }
4348
4349 return 0;
4350 }
4351
wave_read_ind(struct amdgpu_device * adev,uint32_t wave,uint32_t address)4352 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4353 {
4354 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4355 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4356 (address << SQ_IND_INDEX__INDEX__SHIFT));
4357 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4358 }
4359
wave_read_regs(struct amdgpu_device * adev,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)4360 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4361 uint32_t thread, uint32_t regno,
4362 uint32_t num, uint32_t *out)
4363 {
4364 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4365 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4366 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4367 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4368 (SQ_IND_INDEX__AUTO_INCR_MASK));
4369 while (num--)
4370 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4371 }
4372
gfx_v10_0_read_wave_data(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)4373 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4374 {
4375 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4376 * field when performing a select_se_sh so it should be
4377 * zero here
4378 */
4379 WARN_ON(simd != 0);
4380
4381 /* type 2 wave data */
4382 dst[(*no_fields)++] = 2;
4383 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4384 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4385 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4386 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4387 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4388 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4389 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4390 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4391 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4392 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4393 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4394 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4395 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4396 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4397 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4398 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4399 }
4400
gfx_v10_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)4401 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4402 uint32_t wave, uint32_t start,
4403 uint32_t size, uint32_t *dst)
4404 {
4405 WARN_ON(simd != 0);
4406
4407 wave_read_regs(
4408 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4409 dst);
4410 }
4411
gfx_v10_0_read_wave_vgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst)4412 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4413 uint32_t wave, uint32_t thread,
4414 uint32_t start, uint32_t size,
4415 uint32_t *dst)
4416 {
4417 wave_read_regs(
4418 adev, wave, thread,
4419 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4420 }
4421
gfx_v10_0_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm,u32 xcc_id)4422 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4423 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
4424 {
4425 nv_grbm_select(adev, me, pipe, q, vm);
4426 }
4427
gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device * adev,bool enable)4428 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4429 bool enable)
4430 {
4431 uint32_t data, def;
4432
4433 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4434
4435 if (enable)
4436 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4437 else
4438 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4439
4440 if (data != def)
4441 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4442 }
4443
4444 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4445 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4446 .select_se_sh = &gfx_v10_0_select_se_sh,
4447 .read_wave_data = &gfx_v10_0_read_wave_data,
4448 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4449 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4450 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4451 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4452 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4453 };
4454
gfx_v10_0_gpu_early_init(struct amdgpu_device * adev)4455 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4456 {
4457 u32 gb_addr_config;
4458
4459 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4460 case IP_VERSION(10, 1, 10):
4461 case IP_VERSION(10, 1, 1):
4462 case IP_VERSION(10, 1, 2):
4463 adev->gfx.config.max_hw_contexts = 8;
4464 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4465 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4466 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4467 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4468 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4469 break;
4470 case IP_VERSION(10, 3, 0):
4471 case IP_VERSION(10, 3, 2):
4472 case IP_VERSION(10, 3, 1):
4473 case IP_VERSION(10, 3, 4):
4474 case IP_VERSION(10, 3, 5):
4475 case IP_VERSION(10, 3, 6):
4476 case IP_VERSION(10, 3, 3):
4477 case IP_VERSION(10, 3, 7):
4478 adev->gfx.config.max_hw_contexts = 8;
4479 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4480 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4481 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4482 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4483 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4484 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4485 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4486 break;
4487 case IP_VERSION(10, 1, 3):
4488 case IP_VERSION(10, 1, 4):
4489 adev->gfx.config.max_hw_contexts = 8;
4490 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4491 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4492 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4493 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4494 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4495 break;
4496 default:
4497 BUG();
4498 break;
4499 }
4500
4501 adev->gfx.config.gb_addr_config = gb_addr_config;
4502
4503 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4504 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4505 GB_ADDR_CONFIG, NUM_PIPES);
4506
4507 adev->gfx.config.max_tile_pipes =
4508 adev->gfx.config.gb_addr_config_fields.num_pipes;
4509
4510 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4511 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4512 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4513 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4514 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4515 GB_ADDR_CONFIG, NUM_RB_PER_SE);
4516 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4517 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4518 GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4519 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4520 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4521 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4522 }
4523
gfx_v10_0_gfx_ring_init(struct amdgpu_device * adev,int ring_id,int me,int pipe,int queue)4524 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4525 int me, int pipe, int queue)
4526 {
4527 struct amdgpu_ring *ring;
4528 unsigned int irq_type;
4529 unsigned int hw_prio;
4530
4531 ring = &adev->gfx.gfx_ring[ring_id];
4532
4533 ring->me = me;
4534 ring->pipe = pipe;
4535 ring->queue = queue;
4536
4537 ring->ring_obj = NULL;
4538 ring->use_doorbell = true;
4539
4540 if (!ring_id)
4541 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4542 else
4543 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4544 ring->vm_hub = AMDGPU_GFXHUB(0);
4545 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4546
4547 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4548 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4549 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4550 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4551 hw_prio, NULL);
4552 }
4553
gfx_v10_0_compute_ring_init(struct amdgpu_device * adev,int ring_id,int mec,int pipe,int queue)4554 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4555 int mec, int pipe, int queue)
4556 {
4557 unsigned int irq_type;
4558 struct amdgpu_ring *ring;
4559 unsigned int hw_prio;
4560
4561 ring = &adev->gfx.compute_ring[ring_id];
4562
4563 /* mec0 is me1 */
4564 ring->me = mec + 1;
4565 ring->pipe = pipe;
4566 ring->queue = queue;
4567
4568 ring->ring_obj = NULL;
4569 ring->use_doorbell = true;
4570 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4571 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4572 + (ring_id * GFX10_MEC_HPD_SIZE);
4573 ring->vm_hub = AMDGPU_GFXHUB(0);
4574 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4575
4576 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4577 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4578 + ring->pipe;
4579 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4580 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4581 /* type-2 packets are deprecated on MEC, use type-3 instead */
4582 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4583 hw_prio, NULL);
4584 }
4585
gfx_v10_0_alloc_dump_mem(struct amdgpu_device * adev)4586 static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev)
4587 {
4588 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
4589 uint32_t *ptr;
4590
4591 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
4592 if (ptr == NULL) {
4593 DRM_ERROR("Failed to allocate memory for IP Dump\n");
4594 adev->gfx.ip_dump = NULL;
4595 adev->gfx.reg_count = 0;
4596 } else {
4597 adev->gfx.ip_dump = ptr;
4598 adev->gfx.reg_count = reg_count;
4599 }
4600 }
4601
gfx_v10_0_sw_init(void * handle)4602 static int gfx_v10_0_sw_init(void *handle)
4603 {
4604 int i, j, k, r, ring_id = 0;
4605 int xcc_id = 0;
4606 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4607
4608 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4609 case IP_VERSION(10, 1, 10):
4610 case IP_VERSION(10, 1, 1):
4611 case IP_VERSION(10, 1, 2):
4612 case IP_VERSION(10, 1, 3):
4613 case IP_VERSION(10, 1, 4):
4614 adev->gfx.me.num_me = 1;
4615 adev->gfx.me.num_pipe_per_me = 1;
4616 adev->gfx.me.num_queue_per_pipe = 1;
4617 adev->gfx.mec.num_mec = 2;
4618 adev->gfx.mec.num_pipe_per_mec = 4;
4619 adev->gfx.mec.num_queue_per_pipe = 8;
4620 break;
4621 case IP_VERSION(10, 3, 0):
4622 case IP_VERSION(10, 3, 2):
4623 case IP_VERSION(10, 3, 1):
4624 case IP_VERSION(10, 3, 4):
4625 case IP_VERSION(10, 3, 5):
4626 case IP_VERSION(10, 3, 6):
4627 case IP_VERSION(10, 3, 3):
4628 case IP_VERSION(10, 3, 7):
4629 adev->gfx.me.num_me = 1;
4630 adev->gfx.me.num_pipe_per_me = 2;
4631 adev->gfx.me.num_queue_per_pipe = 1;
4632 adev->gfx.mec.num_mec = 2;
4633 adev->gfx.mec.num_pipe_per_mec = 4;
4634 adev->gfx.mec.num_queue_per_pipe = 4;
4635 break;
4636 default:
4637 adev->gfx.me.num_me = 1;
4638 adev->gfx.me.num_pipe_per_me = 1;
4639 adev->gfx.me.num_queue_per_pipe = 1;
4640 adev->gfx.mec.num_mec = 1;
4641 adev->gfx.mec.num_pipe_per_mec = 4;
4642 adev->gfx.mec.num_queue_per_pipe = 8;
4643 break;
4644 }
4645
4646 /* KIQ event */
4647 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4648 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4649 &adev->gfx.kiq[0].irq);
4650 if (r)
4651 return r;
4652
4653 /* EOP Event */
4654 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4655 GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4656 &adev->gfx.eop_irq);
4657 if (r)
4658 return r;
4659
4660 /* Privileged reg */
4661 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4662 &adev->gfx.priv_reg_irq);
4663 if (r)
4664 return r;
4665
4666 /* Privileged inst */
4667 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4668 &adev->gfx.priv_inst_irq);
4669 if (r)
4670 return r;
4671
4672 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4673
4674 gfx_v10_0_me_init(adev);
4675
4676 if (adev->gfx.rlc.funcs) {
4677 if (adev->gfx.rlc.funcs->init) {
4678 r = adev->gfx.rlc.funcs->init(adev);
4679 if (r) {
4680 dev_err(adev->dev, "Failed to init rlc BOs!\n");
4681 return r;
4682 }
4683 }
4684 }
4685
4686 r = gfx_v10_0_mec_init(adev);
4687 if (r) {
4688 DRM_ERROR("Failed to init MEC BOs!\n");
4689 return r;
4690 }
4691
4692 /* set up the gfx ring */
4693 for (i = 0; i < adev->gfx.me.num_me; i++) {
4694 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4695 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4696 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4697 continue;
4698
4699 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4700 i, k, j);
4701 if (r)
4702 return r;
4703 ring_id++;
4704 }
4705 }
4706 }
4707
4708 ring_id = 0;
4709 /* set up the compute queues - allocate horizontally across pipes */
4710 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4711 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4712 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4713 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
4714 k, j))
4715 continue;
4716
4717 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4718 i, k, j);
4719 if (r)
4720 return r;
4721
4722 ring_id++;
4723 }
4724 }
4725 }
4726
4727 if (!adev->enable_mes_kiq) {
4728 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);
4729 if (r) {
4730 DRM_ERROR("Failed to init KIQ BOs!\n");
4731 return r;
4732 }
4733
4734 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
4735 if (r)
4736 return r;
4737 }
4738
4739 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0);
4740 if (r)
4741 return r;
4742
4743 /* allocate visible FB for rlc auto-loading fw */
4744 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4745 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4746 if (r)
4747 return r;
4748 }
4749
4750 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4751
4752 gfx_v10_0_gpu_early_init(adev);
4753
4754 gfx_v10_0_alloc_dump_mem(adev);
4755
4756 return 0;
4757 }
4758
gfx_v10_0_pfp_fini(struct amdgpu_device * adev)4759 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4760 {
4761 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4762 &adev->gfx.pfp.pfp_fw_gpu_addr,
4763 (void **)&adev->gfx.pfp.pfp_fw_ptr);
4764 }
4765
gfx_v10_0_ce_fini(struct amdgpu_device * adev)4766 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4767 {
4768 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4769 &adev->gfx.ce.ce_fw_gpu_addr,
4770 (void **)&adev->gfx.ce.ce_fw_ptr);
4771 }
4772
gfx_v10_0_me_fini(struct amdgpu_device * adev)4773 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4774 {
4775 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4776 &adev->gfx.me.me_fw_gpu_addr,
4777 (void **)&adev->gfx.me.me_fw_ptr);
4778 }
4779
gfx_v10_0_sw_fini(void * handle)4780 static int gfx_v10_0_sw_fini(void *handle)
4781 {
4782 int i;
4783 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4784
4785 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4786 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4787 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4788 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4789
4790 amdgpu_gfx_mqd_sw_fini(adev, 0);
4791
4792 if (!adev->enable_mes_kiq) {
4793 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
4794 amdgpu_gfx_kiq_fini(adev, 0);
4795 }
4796
4797 gfx_v10_0_pfp_fini(adev);
4798 gfx_v10_0_ce_fini(adev);
4799 gfx_v10_0_me_fini(adev);
4800 gfx_v10_0_rlc_fini(adev);
4801 gfx_v10_0_mec_fini(adev);
4802
4803 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4804 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4805
4806 gfx_v10_0_free_microcode(adev);
4807
4808 kfree(adev->gfx.ip_dump);
4809
4810 return 0;
4811 }
4812
gfx_v10_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id)4813 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4814 u32 sh_num, u32 instance, int xcc_id)
4815 {
4816 u32 data;
4817
4818 if (instance == 0xffffffff)
4819 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4820 INSTANCE_BROADCAST_WRITES, 1);
4821 else
4822 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4823 instance);
4824
4825 if (se_num == 0xffffffff)
4826 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4827 1);
4828 else
4829 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4830
4831 if (sh_num == 0xffffffff)
4832 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4833 1);
4834 else
4835 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4836
4837 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4838 }
4839
gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device * adev)4840 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4841 {
4842 u32 data, mask;
4843
4844 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4845 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4846
4847 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4848 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4849
4850 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4851 adev->gfx.config.max_sh_per_se);
4852
4853 return (~data) & mask;
4854 }
4855
gfx_v10_0_setup_rb(struct amdgpu_device * adev)4856 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4857 {
4858 int i, j;
4859 u32 data;
4860 u32 active_rbs = 0;
4861 u32 bitmap;
4862 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4863 adev->gfx.config.max_sh_per_se;
4864
4865 mutex_lock(&adev->grbm_idx_mutex);
4866 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4867 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4868 bitmap = i * adev->gfx.config.max_sh_per_se + j;
4869 if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
4870 IP_VERSION(10, 3, 0)) ||
4871 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
4872 IP_VERSION(10, 3, 3)) ||
4873 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
4874 IP_VERSION(10, 3, 6))) &&
4875 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4876 continue;
4877 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
4878 data = gfx_v10_0_get_rb_active_bitmap(adev);
4879 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4880 rb_bitmap_width_per_sh);
4881 }
4882 }
4883 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
4884 mutex_unlock(&adev->grbm_idx_mutex);
4885
4886 adev->gfx.config.backend_enable_mask = active_rbs;
4887 adev->gfx.config.num_rbs = hweight32(active_rbs);
4888 }
4889
gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device * adev)4890 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4891 {
4892 uint32_t num_sc;
4893 uint32_t enabled_rb_per_sh;
4894 uint32_t active_rb_bitmap;
4895 uint32_t num_rb_per_sc;
4896 uint32_t num_packer_per_sc;
4897 uint32_t pa_sc_tile_steering_override;
4898
4899 /* for ASICs that integrates GFX v10.3
4900 * pa_sc_tile_steering_override should be set to 0
4901 */
4902 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
4903 return 0;
4904
4905 /* init num_sc */
4906 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4907 adev->gfx.config.num_sc_per_sh;
4908 /* init num_rb_per_sc */
4909 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4910 enabled_rb_per_sh = hweight32(active_rb_bitmap);
4911 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4912 /* init num_packer_per_sc */
4913 num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4914
4915 pa_sc_tile_steering_override = 0;
4916 pa_sc_tile_steering_override |=
4917 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4918 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4919 pa_sc_tile_steering_override |=
4920 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4921 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4922 pa_sc_tile_steering_override |=
4923 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4924 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4925
4926 return pa_sc_tile_steering_override;
4927 }
4928
4929 #define DEFAULT_SH_MEM_BASES (0x6000)
4930
gfx_v10_0_debug_trap_config_init(struct amdgpu_device * adev,uint32_t first_vmid,uint32_t last_vmid)4931 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev,
4932 uint32_t first_vmid,
4933 uint32_t last_vmid)
4934 {
4935 uint32_t data;
4936 uint32_t trap_config_vmid_mask = 0;
4937 int i;
4938
4939 /* Calculate trap config vmid mask */
4940 for (i = first_vmid; i < last_vmid; i++)
4941 trap_config_vmid_mask |= (1 << i);
4942
4943 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,
4944 VMID_SEL, trap_config_vmid_mask);
4945 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
4946 TRAP_EN, 1);
4947 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
4948 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
4949
4950 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
4951 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
4952 }
4953
gfx_v10_0_init_compute_vmid(struct amdgpu_device * adev)4954 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4955 {
4956 int i;
4957 uint32_t sh_mem_bases;
4958
4959 /*
4960 * Configure apertures:
4961 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
4962 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
4963 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
4964 */
4965 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4966
4967 mutex_lock(&adev->srbm_mutex);
4968 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4969 nv_grbm_select(adev, 0, 0, 0, i);
4970 /* CP and shaders */
4971 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4972 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4973 }
4974 nv_grbm_select(adev, 0, 0, 0, 0);
4975 mutex_unlock(&adev->srbm_mutex);
4976
4977 /*
4978 * Initialize all compute VMIDs to have no GDS, GWS, or OA
4979 * access. These should be enabled by FW for target VMIDs.
4980 */
4981 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4982 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4983 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4984 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4985 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4986 }
4987
4988 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid,
4989 AMDGPU_NUM_VMID);
4990 }
4991
gfx_v10_0_init_gds_vmid(struct amdgpu_device * adev)4992 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4993 {
4994 int vmid;
4995
4996 /*
4997 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4998 * access. Compute VMIDs should be enabled by FW for target VMIDs,
4999 * the driver can enable them for graphics. VMID0 should maintain
5000 * access so that HWS firmware can save/restore entries.
5001 */
5002 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5003 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5004 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5005 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5006 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5007 }
5008 }
5009
5010
gfx_v10_0_tcp_harvest(struct amdgpu_device * adev)5011 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5012 {
5013 int i, j, k;
5014 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5015 u32 tmp, wgp_active_bitmap = 0;
5016 u32 gcrd_targets_disable_tcp = 0;
5017 u32 utcl_invreq_disable = 0;
5018 /*
5019 * GCRD_TARGETS_DISABLE field contains
5020 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5021 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5022 */
5023 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5024 2 * max_wgp_per_sh + /* TCP */
5025 max_wgp_per_sh + /* SQC */
5026 4); /* GL1C */
5027 /*
5028 * UTCL1_UTCL0_INVREQ_DISABLE field contains
5029 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5030 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5031 */
5032 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5033 2 * max_wgp_per_sh + /* TCP */
5034 2 * max_wgp_per_sh + /* SQC */
5035 4 + /* RMI */
5036 1); /* SQG */
5037
5038 mutex_lock(&adev->grbm_idx_mutex);
5039 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5040 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5041 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5042 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5043 /*
5044 * Set corresponding TCP bits for the inactive WGPs in
5045 * GCRD_SA_TARGETS_DISABLE
5046 */
5047 gcrd_targets_disable_tcp = 0;
5048 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5049 utcl_invreq_disable = 0;
5050
5051 for (k = 0; k < max_wgp_per_sh; k++) {
5052 if (!(wgp_active_bitmap & (1 << k))) {
5053 gcrd_targets_disable_tcp |= 3 << (2 * k);
5054 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5055 utcl_invreq_disable |= (3 << (2 * k)) |
5056 (3 << (2 * (max_wgp_per_sh + k)));
5057 }
5058 }
5059
5060 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5061 /* only override TCP & SQC bits */
5062 tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5063 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5064 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5065
5066 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5067 /* only override TCP & SQC bits */
5068 tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5069 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5070 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5071 }
5072 }
5073
5074 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5075 mutex_unlock(&adev->grbm_idx_mutex);
5076 }
5077
gfx_v10_0_get_tcc_info(struct amdgpu_device * adev)5078 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5079 {
5080 /* TCCs are global (not instanced). */
5081 uint32_t tcc_disable;
5082
5083 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) {
5084 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5085 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5086 } else {
5087 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5088 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5089 }
5090
5091 adev->gfx.config.tcc_disabled_mask =
5092 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5093 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5094 }
5095
gfx_v10_0_constants_init(struct amdgpu_device * adev)5096 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5097 {
5098 u32 tmp;
5099 int i;
5100
5101 if (!amdgpu_sriov_vf(adev))
5102 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5103
5104 gfx_v10_0_setup_rb(adev);
5105 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5106 gfx_v10_0_get_tcc_info(adev);
5107 adev->gfx.config.pa_sc_tile_steering_override =
5108 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5109
5110 /* XXX SH_MEM regs */
5111 /* where to put LDS, scratch, GPUVM in FSA64 space */
5112 mutex_lock(&adev->srbm_mutex);
5113 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
5114 nv_grbm_select(adev, 0, 0, 0, i);
5115 /* CP and shaders */
5116 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5117 if (i != 0) {
5118 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5119 (adev->gmc.private_aperture_start >> 48));
5120 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5121 (adev->gmc.shared_aperture_start >> 48));
5122 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5123 }
5124 }
5125 nv_grbm_select(adev, 0, 0, 0, 0);
5126
5127 mutex_unlock(&adev->srbm_mutex);
5128
5129 gfx_v10_0_init_compute_vmid(adev);
5130 gfx_v10_0_init_gds_vmid(adev);
5131
5132 }
5133
gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable)5134 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5135 bool enable)
5136 {
5137 u32 tmp;
5138
5139 if (amdgpu_sriov_vf(adev))
5140 return;
5141
5142 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5143
5144 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5145 enable ? 1 : 0);
5146 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5147 enable ? 1 : 0);
5148 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5149 enable ? 1 : 0);
5150 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5151 enable ? 1 : 0);
5152
5153 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5154 }
5155
gfx_v10_0_init_csb(struct amdgpu_device * adev)5156 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5157 {
5158 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5159
5160 /* csib */
5161 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
5162 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5163 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5164 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5165 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5166 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5167 } else {
5168 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5169 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5170 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5171 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5172 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5173 }
5174 return 0;
5175 }
5176
gfx_v10_0_rlc_stop(struct amdgpu_device * adev)5177 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5178 {
5179 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5180
5181 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5182 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5183 }
5184
gfx_v10_0_rlc_reset(struct amdgpu_device * adev)5185 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5186 {
5187 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5188 udelay(50);
5189 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5190 udelay(50);
5191 }
5192
gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device * adev,bool enable)5193 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5194 bool enable)
5195 {
5196 uint32_t rlc_pg_cntl;
5197
5198 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5199
5200 if (!enable) {
5201 /* RLC_PG_CNTL[23] = 0 (default)
5202 * RLC will wait for handshake acks with SMU
5203 * GFXOFF will be enabled
5204 * RLC_PG_CNTL[23] = 1
5205 * RLC will not issue any message to SMU
5206 * hence no handshake between SMU & RLC
5207 * GFXOFF will be disabled
5208 */
5209 rlc_pg_cntl |= 0x800000;
5210 } else
5211 rlc_pg_cntl &= ~0x800000;
5212 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5213 }
5214
gfx_v10_0_rlc_start(struct amdgpu_device * adev)5215 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5216 {
5217 /*
5218 * TODO: enable rlc & smu handshake until smu
5219 * and gfxoff feature works as expected
5220 */
5221 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5222 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5223
5224 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5225 udelay(50);
5226 }
5227
gfx_v10_0_rlc_enable_srm(struct amdgpu_device * adev)5228 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5229 {
5230 uint32_t tmp;
5231
5232 /* enable Save Restore Machine */
5233 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5234 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5235 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5236 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5237 }
5238
gfx_v10_0_rlc_load_microcode(struct amdgpu_device * adev)5239 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5240 {
5241 const struct rlc_firmware_header_v2_0 *hdr;
5242 const __le32 *fw_data;
5243 unsigned int i, fw_size;
5244
5245 if (!adev->gfx.rlc_fw)
5246 return -EINVAL;
5247
5248 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5249 amdgpu_ucode_print_rlc_hdr(&hdr->header);
5250
5251 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5252 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5253 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5254
5255 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5256 RLCG_UCODE_LOADING_START_ADDRESS);
5257
5258 for (i = 0; i < fw_size; i++)
5259 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5260 le32_to_cpup(fw_data++));
5261
5262 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5263
5264 return 0;
5265 }
5266
gfx_v10_0_rlc_resume(struct amdgpu_device * adev)5267 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5268 {
5269 int r;
5270
5271 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5272 adev->psp.autoload_supported) {
5273
5274 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5275 if (r)
5276 return r;
5277
5278 gfx_v10_0_init_csb(adev);
5279
5280 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5281
5282 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5283 gfx_v10_0_rlc_enable_srm(adev);
5284 } else {
5285 if (amdgpu_sriov_vf(adev)) {
5286 gfx_v10_0_init_csb(adev);
5287 return 0;
5288 }
5289
5290 adev->gfx.rlc.funcs->stop(adev);
5291
5292 /* disable CG */
5293 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5294
5295 /* disable PG */
5296 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5297
5298 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5299 /* legacy rlc firmware loading */
5300 r = gfx_v10_0_rlc_load_microcode(adev);
5301 if (r)
5302 return r;
5303 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5304 /* rlc backdoor autoload firmware */
5305 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5306 if (r)
5307 return r;
5308 }
5309
5310 gfx_v10_0_init_csb(adev);
5311
5312 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5313
5314 adev->gfx.rlc.funcs->start(adev);
5315
5316 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5317 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5318 if (r)
5319 return r;
5320 }
5321 }
5322
5323 return 0;
5324 }
5325
5326 static struct {
5327 FIRMWARE_ID id;
5328 unsigned int offset;
5329 unsigned int size;
5330 } rlc_autoload_info[FIRMWARE_ID_MAX];
5331
gfx_v10_0_parse_rlc_toc(struct amdgpu_device * adev)5332 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5333 {
5334 int ret;
5335 RLC_TABLE_OF_CONTENT *rlc_toc;
5336
5337 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5338 AMDGPU_GEM_DOMAIN_GTT,
5339 &adev->gfx.rlc.rlc_toc_bo,
5340 &adev->gfx.rlc.rlc_toc_gpu_addr,
5341 (void **)&adev->gfx.rlc.rlc_toc_buf);
5342 if (ret) {
5343 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5344 return ret;
5345 }
5346
5347 /* Copy toc from psp sos fw to rlc toc buffer */
5348 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5349
5350 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5351 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5352 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5353 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5354 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5355 /* Offset needs 4KB alignment */
5356 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5357 }
5358
5359 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5360 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5361 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5362
5363 rlc_toc++;
5364 }
5365
5366 return 0;
5367 }
5368
gfx_v10_0_calc_toc_total_size(struct amdgpu_device * adev)5369 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5370 {
5371 uint32_t total_size = 0;
5372 FIRMWARE_ID id;
5373 int ret;
5374
5375 ret = gfx_v10_0_parse_rlc_toc(adev);
5376 if (ret) {
5377 dev_err(adev->dev, "failed to parse rlc toc\n");
5378 return 0;
5379 }
5380
5381 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5382 total_size += rlc_autoload_info[id].size;
5383
5384 /* In case the offset in rlc toc ucode is aligned */
5385 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5386 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5387 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5388
5389 return total_size;
5390 }
5391
gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device * adev)5392 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5393 {
5394 int r;
5395 uint32_t total_size;
5396
5397 total_size = gfx_v10_0_calc_toc_total_size(adev);
5398
5399 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5400 AMDGPU_GEM_DOMAIN_GTT,
5401 &adev->gfx.rlc.rlc_autoload_bo,
5402 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5403 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5404 if (r) {
5405 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5406 return r;
5407 }
5408
5409 return 0;
5410 }
5411
gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device * adev)5412 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5413 {
5414 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5415 &adev->gfx.rlc.rlc_toc_gpu_addr,
5416 (void **)&adev->gfx.rlc.rlc_toc_buf);
5417 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5418 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5419 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5420 }
5421
gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device * adev,FIRMWARE_ID id,const void * fw_data,uint32_t fw_size)5422 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5423 FIRMWARE_ID id,
5424 const void *fw_data,
5425 uint32_t fw_size)
5426 {
5427 uint32_t toc_offset;
5428 uint32_t toc_fw_size;
5429 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5430
5431 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5432 return;
5433
5434 toc_offset = rlc_autoload_info[id].offset;
5435 toc_fw_size = rlc_autoload_info[id].size;
5436
5437 if (fw_size == 0)
5438 fw_size = toc_fw_size;
5439
5440 if (fw_size > toc_fw_size)
5441 fw_size = toc_fw_size;
5442
5443 memcpy(ptr + toc_offset, fw_data, fw_size);
5444
5445 if (fw_size < toc_fw_size)
5446 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5447 }
5448
gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device * adev)5449 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5450 {
5451 void *data;
5452 uint32_t size;
5453
5454 data = adev->gfx.rlc.rlc_toc_buf;
5455 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5456
5457 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5458 FIRMWARE_ID_RLC_TOC,
5459 data, size);
5460 }
5461
gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device * adev)5462 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5463 {
5464 const __le32 *fw_data;
5465 uint32_t fw_size;
5466 const struct gfx_firmware_header_v1_0 *cp_hdr;
5467 const struct rlc_firmware_header_v2_0 *rlc_hdr;
5468
5469 /* pfp ucode */
5470 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5471 adev->gfx.pfp_fw->data;
5472 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5473 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5474 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5475 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5476 FIRMWARE_ID_CP_PFP,
5477 fw_data, fw_size);
5478
5479 /* ce ucode */
5480 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5481 adev->gfx.ce_fw->data;
5482 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5483 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5484 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5485 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5486 FIRMWARE_ID_CP_CE,
5487 fw_data, fw_size);
5488
5489 /* me ucode */
5490 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5491 adev->gfx.me_fw->data;
5492 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5493 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5494 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5495 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5496 FIRMWARE_ID_CP_ME,
5497 fw_data, fw_size);
5498
5499 /* rlc ucode */
5500 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5501 adev->gfx.rlc_fw->data;
5502 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5503 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5504 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5505 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5506 FIRMWARE_ID_RLC_G_UCODE,
5507 fw_data, fw_size);
5508
5509 /* mec1 ucode */
5510 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5511 adev->gfx.mec_fw->data;
5512 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5513 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5514 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5515 cp_hdr->jt_size * 4;
5516 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5517 FIRMWARE_ID_CP_MEC,
5518 fw_data, fw_size);
5519 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5520 }
5521
5522 /* Temporarily put sdma part here */
gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device * adev)5523 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5524 {
5525 const __le32 *fw_data;
5526 uint32_t fw_size;
5527 const struct sdma_firmware_header_v1_0 *sdma_hdr;
5528 int i;
5529
5530 for (i = 0; i < adev->sdma.num_instances; i++) {
5531 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5532 adev->sdma.instance[i].fw->data;
5533 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5534 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5535 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5536
5537 if (i == 0) {
5538 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5539 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5540 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5541 FIRMWARE_ID_SDMA0_JT,
5542 (uint32_t *)fw_data +
5543 sdma_hdr->jt_offset,
5544 sdma_hdr->jt_size * 4);
5545 } else if (i == 1) {
5546 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5547 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5548 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5549 FIRMWARE_ID_SDMA1_JT,
5550 (uint32_t *)fw_data +
5551 sdma_hdr->jt_offset,
5552 sdma_hdr->jt_size * 4);
5553 }
5554 }
5555 }
5556
gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device * adev)5557 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5558 {
5559 uint32_t rlc_g_offset, rlc_g_size, tmp;
5560 uint64_t gpu_addr;
5561
5562 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5563 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5564 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5565
5566 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5567 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5568 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5569
5570 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5571 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5572 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5573
5574 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5575 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5576 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5577 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5578 return -EINVAL;
5579 }
5580
5581 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5582 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5583 DRM_ERROR("RLC ROM should halt itself\n");
5584 return -EINVAL;
5585 }
5586
5587 return 0;
5588 }
5589
gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device * adev)5590 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5591 {
5592 uint32_t usec_timeout = 50000; /* wait for 50ms */
5593 uint32_t tmp;
5594 int i;
5595 uint64_t addr;
5596
5597 /* Trigger an invalidation of the L1 instruction caches */
5598 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5599 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5600 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5601
5602 /* Wait for invalidation complete */
5603 for (i = 0; i < usec_timeout; i++) {
5604 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5605 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5606 INVALIDATE_CACHE_COMPLETE))
5607 break;
5608 udelay(1);
5609 }
5610
5611 if (i >= usec_timeout) {
5612 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5613 return -EINVAL;
5614 }
5615
5616 /* Program me ucode address into intruction cache address register */
5617 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5618 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5619 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5620 lower_32_bits(addr) & 0xFFFFF000);
5621 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5622 upper_32_bits(addr));
5623
5624 return 0;
5625 }
5626
gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device * adev)5627 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5628 {
5629 uint32_t usec_timeout = 50000; /* wait for 50ms */
5630 uint32_t tmp;
5631 int i;
5632 uint64_t addr;
5633
5634 /* Trigger an invalidation of the L1 instruction caches */
5635 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5636 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5637 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5638
5639 /* Wait for invalidation complete */
5640 for (i = 0; i < usec_timeout; i++) {
5641 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5642 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5643 INVALIDATE_CACHE_COMPLETE))
5644 break;
5645 udelay(1);
5646 }
5647
5648 if (i >= usec_timeout) {
5649 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5650 return -EINVAL;
5651 }
5652
5653 /* Program ce ucode address into intruction cache address register */
5654 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5655 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5656 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5657 lower_32_bits(addr) & 0xFFFFF000);
5658 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5659 upper_32_bits(addr));
5660
5661 return 0;
5662 }
5663
gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device * adev)5664 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5665 {
5666 uint32_t usec_timeout = 50000; /* wait for 50ms */
5667 uint32_t tmp;
5668 int i;
5669 uint64_t addr;
5670
5671 /* Trigger an invalidation of the L1 instruction caches */
5672 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5673 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5674 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5675
5676 /* Wait for invalidation complete */
5677 for (i = 0; i < usec_timeout; i++) {
5678 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5679 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5680 INVALIDATE_CACHE_COMPLETE))
5681 break;
5682 udelay(1);
5683 }
5684
5685 if (i >= usec_timeout) {
5686 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5687 return -EINVAL;
5688 }
5689
5690 /* Program pfp ucode address into intruction cache address register */
5691 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5692 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5693 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5694 lower_32_bits(addr) & 0xFFFFF000);
5695 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5696 upper_32_bits(addr));
5697
5698 return 0;
5699 }
5700
gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device * adev)5701 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5702 {
5703 uint32_t usec_timeout = 50000; /* wait for 50ms */
5704 uint32_t tmp;
5705 int i;
5706 uint64_t addr;
5707
5708 /* Trigger an invalidation of the L1 instruction caches */
5709 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5710 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5711 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5712
5713 /* Wait for invalidation complete */
5714 for (i = 0; i < usec_timeout; i++) {
5715 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5716 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5717 INVALIDATE_CACHE_COMPLETE))
5718 break;
5719 udelay(1);
5720 }
5721
5722 if (i >= usec_timeout) {
5723 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5724 return -EINVAL;
5725 }
5726
5727 /* Program mec1 ucode address into intruction cache address register */
5728 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5729 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5730 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5731 lower_32_bits(addr) & 0xFFFFF000);
5732 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5733 upper_32_bits(addr));
5734
5735 return 0;
5736 }
5737
gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device * adev)5738 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5739 {
5740 uint32_t cp_status;
5741 uint32_t bootload_status;
5742 int i, r;
5743
5744 for (i = 0; i < adev->usec_timeout; i++) {
5745 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5746 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5747 if ((cp_status == 0) &&
5748 (REG_GET_FIELD(bootload_status,
5749 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5750 break;
5751 }
5752 udelay(1);
5753 }
5754
5755 if (i >= adev->usec_timeout) {
5756 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5757 return -ETIMEDOUT;
5758 }
5759
5760 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5761 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5762 if (r)
5763 return r;
5764
5765 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5766 if (r)
5767 return r;
5768
5769 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5770 if (r)
5771 return r;
5772
5773 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5774 if (r)
5775 return r;
5776 }
5777
5778 return 0;
5779 }
5780
gfx_v10_0_cp_gfx_enable(struct amdgpu_device * adev,bool enable)5781 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5782 {
5783 int i;
5784 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5785
5786 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5787 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5788 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5789
5790 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
5791 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5792 else
5793 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5794
5795 if (adev->job_hang && !enable)
5796 return 0;
5797
5798 for (i = 0; i < adev->usec_timeout; i++) {
5799 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5800 break;
5801 udelay(1);
5802 }
5803
5804 if (i >= adev->usec_timeout)
5805 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5806
5807 return 0;
5808 }
5809
gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device * adev)5810 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5811 {
5812 int r;
5813 const struct gfx_firmware_header_v1_0 *pfp_hdr;
5814 const __le32 *fw_data;
5815 unsigned int i, fw_size;
5816 uint32_t tmp;
5817 uint32_t usec_timeout = 50000; /* wait for 50ms */
5818
5819 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5820 adev->gfx.pfp_fw->data;
5821
5822 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5823
5824 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5825 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5826 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5827
5828 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5829 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5830 &adev->gfx.pfp.pfp_fw_obj,
5831 &adev->gfx.pfp.pfp_fw_gpu_addr,
5832 (void **)&adev->gfx.pfp.pfp_fw_ptr);
5833 if (r) {
5834 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5835 gfx_v10_0_pfp_fini(adev);
5836 return r;
5837 }
5838
5839 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5840
5841 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5842 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5843
5844 /* Trigger an invalidation of the L1 instruction caches */
5845 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5846 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5847 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5848
5849 /* Wait for invalidation complete */
5850 for (i = 0; i < usec_timeout; i++) {
5851 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5852 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5853 INVALIDATE_CACHE_COMPLETE))
5854 break;
5855 udelay(1);
5856 }
5857
5858 if (i >= usec_timeout) {
5859 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5860 return -EINVAL;
5861 }
5862
5863 if (amdgpu_emu_mode == 1)
5864 adev->hdp.funcs->flush_hdp(adev, NULL);
5865
5866 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5867 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5868 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5869 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5870 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5871 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5872 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5873 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5874 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5875 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5876
5877 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5878
5879 for (i = 0; i < pfp_hdr->jt_size; i++)
5880 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5881 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5882
5883 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5884
5885 return 0;
5886 }
5887
gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device * adev)5888 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5889 {
5890 int r;
5891 const struct gfx_firmware_header_v1_0 *ce_hdr;
5892 const __le32 *fw_data;
5893 unsigned int i, fw_size;
5894 uint32_t tmp;
5895 uint32_t usec_timeout = 50000; /* wait for 50ms */
5896
5897 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5898 adev->gfx.ce_fw->data;
5899
5900 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5901
5902 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5903 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5904 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5905
5906 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5907 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5908 &adev->gfx.ce.ce_fw_obj,
5909 &adev->gfx.ce.ce_fw_gpu_addr,
5910 (void **)&adev->gfx.ce.ce_fw_ptr);
5911 if (r) {
5912 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5913 gfx_v10_0_ce_fini(adev);
5914 return r;
5915 }
5916
5917 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5918
5919 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5920 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5921
5922 /* Trigger an invalidation of the L1 instruction caches */
5923 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5924 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5925 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5926
5927 /* Wait for invalidation complete */
5928 for (i = 0; i < usec_timeout; i++) {
5929 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5930 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5931 INVALIDATE_CACHE_COMPLETE))
5932 break;
5933 udelay(1);
5934 }
5935
5936 if (i >= usec_timeout) {
5937 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5938 return -EINVAL;
5939 }
5940
5941 if (amdgpu_emu_mode == 1)
5942 adev->hdp.funcs->flush_hdp(adev, NULL);
5943
5944 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5945 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5946 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5947 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5948 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5949 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5950 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5951 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5952 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5953
5954 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5955
5956 for (i = 0; i < ce_hdr->jt_size; i++)
5957 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5958 le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5959
5960 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5961
5962 return 0;
5963 }
5964
gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device * adev)5965 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5966 {
5967 int r;
5968 const struct gfx_firmware_header_v1_0 *me_hdr;
5969 const __le32 *fw_data;
5970 unsigned int i, fw_size;
5971 uint32_t tmp;
5972 uint32_t usec_timeout = 50000; /* wait for 50ms */
5973
5974 me_hdr = (const struct gfx_firmware_header_v1_0 *)
5975 adev->gfx.me_fw->data;
5976
5977 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5978
5979 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5980 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5981 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5982
5983 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5984 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5985 &adev->gfx.me.me_fw_obj,
5986 &adev->gfx.me.me_fw_gpu_addr,
5987 (void **)&adev->gfx.me.me_fw_ptr);
5988 if (r) {
5989 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5990 gfx_v10_0_me_fini(adev);
5991 return r;
5992 }
5993
5994 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5995
5996 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5997 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5998
5999 /* Trigger an invalidation of the L1 instruction caches */
6000 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6001 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6002 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6003
6004 /* Wait for invalidation complete */
6005 for (i = 0; i < usec_timeout; i++) {
6006 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6007 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6008 INVALIDATE_CACHE_COMPLETE))
6009 break;
6010 udelay(1);
6011 }
6012
6013 if (i >= usec_timeout) {
6014 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6015 return -EINVAL;
6016 }
6017
6018 if (amdgpu_emu_mode == 1)
6019 adev->hdp.funcs->flush_hdp(adev, NULL);
6020
6021 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6022 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6023 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6024 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6025 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6026 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6027 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6028 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6029 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6030
6031 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6032
6033 for (i = 0; i < me_hdr->jt_size; i++)
6034 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6035 le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6036
6037 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6038
6039 return 0;
6040 }
6041
gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device * adev)6042 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6043 {
6044 int r;
6045
6046 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6047 return -EINVAL;
6048
6049 gfx_v10_0_cp_gfx_enable(adev, false);
6050
6051 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6052 if (r) {
6053 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6054 return r;
6055 }
6056
6057 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6058 if (r) {
6059 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6060 return r;
6061 }
6062
6063 r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6064 if (r) {
6065 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6066 return r;
6067 }
6068
6069 return 0;
6070 }
6071
gfx_v10_0_cp_gfx_start(struct amdgpu_device * adev)6072 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6073 {
6074 struct amdgpu_ring *ring;
6075 const struct cs_section_def *sect = NULL;
6076 const struct cs_extent_def *ext = NULL;
6077 int r, i;
6078 int ctx_reg_offset;
6079
6080 /* init the CP */
6081 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6082 adev->gfx.config.max_hw_contexts - 1);
6083 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6084
6085 gfx_v10_0_cp_gfx_enable(adev, true);
6086
6087 ring = &adev->gfx.gfx_ring[0];
6088 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6089 if (r) {
6090 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6091 return r;
6092 }
6093
6094 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6095 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6096
6097 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6098 amdgpu_ring_write(ring, 0x80000000);
6099 amdgpu_ring_write(ring, 0x80000000);
6100
6101 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6102 for (ext = sect->section; ext->extent != NULL; ++ext) {
6103 if (sect->id == SECT_CONTEXT) {
6104 amdgpu_ring_write(ring,
6105 PACKET3(PACKET3_SET_CONTEXT_REG,
6106 ext->reg_count));
6107 amdgpu_ring_write(ring, ext->reg_index -
6108 PACKET3_SET_CONTEXT_REG_START);
6109 for (i = 0; i < ext->reg_count; i++)
6110 amdgpu_ring_write(ring, ext->extent[i]);
6111 }
6112 }
6113 }
6114
6115 ctx_reg_offset =
6116 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6117 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6118 amdgpu_ring_write(ring, ctx_reg_offset);
6119 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6120
6121 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6122 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6123
6124 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6125 amdgpu_ring_write(ring, 0);
6126
6127 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6128 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6129 amdgpu_ring_write(ring, 0x8000);
6130 amdgpu_ring_write(ring, 0x8000);
6131
6132 amdgpu_ring_commit(ring);
6133
6134 /* submit cs packet to copy state 0 to next available state */
6135 if (adev->gfx.num_gfx_rings > 1) {
6136 /* maximum supported gfx ring is 2 */
6137 ring = &adev->gfx.gfx_ring[1];
6138 r = amdgpu_ring_alloc(ring, 2);
6139 if (r) {
6140 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6141 return r;
6142 }
6143
6144 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6145 amdgpu_ring_write(ring, 0);
6146
6147 amdgpu_ring_commit(ring);
6148 }
6149 return 0;
6150 }
6151
gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device * adev,CP_PIPE_ID pipe)6152 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6153 CP_PIPE_ID pipe)
6154 {
6155 u32 tmp;
6156
6157 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6158 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6159
6160 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6161 }
6162
gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device * adev,struct amdgpu_ring * ring)6163 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6164 struct amdgpu_ring *ring)
6165 {
6166 u32 tmp;
6167
6168 if (!amdgpu_async_gfx_ring) {
6169 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6170 if (ring->use_doorbell) {
6171 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6172 DOORBELL_OFFSET, ring->doorbell_index);
6173 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6174 DOORBELL_EN, 1);
6175 } else {
6176 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6177 DOORBELL_EN, 0);
6178 }
6179 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6180 }
6181 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6182 case IP_VERSION(10, 3, 0):
6183 case IP_VERSION(10, 3, 2):
6184 case IP_VERSION(10, 3, 1):
6185 case IP_VERSION(10, 3, 4):
6186 case IP_VERSION(10, 3, 5):
6187 case IP_VERSION(10, 3, 6):
6188 case IP_VERSION(10, 3, 3):
6189 case IP_VERSION(10, 3, 7):
6190 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6191 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6192 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6193
6194 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6195 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6196 break;
6197 default:
6198 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6199 DOORBELL_RANGE_LOWER, ring->doorbell_index);
6200 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6201
6202 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6203 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6204 break;
6205 }
6206 }
6207
gfx_v10_0_cp_gfx_resume(struct amdgpu_device * adev)6208 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6209 {
6210 struct amdgpu_ring *ring;
6211 u32 tmp;
6212 u32 rb_bufsz;
6213 u64 rb_addr, rptr_addr, wptr_gpu_addr;
6214
6215 /* Set the write pointer delay */
6216 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6217
6218 /* set the RB to use vmid 0 */
6219 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6220
6221 /* Init gfx ring 0 for pipe 0 */
6222 mutex_lock(&adev->srbm_mutex);
6223 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6224
6225 /* Set ring buffer size */
6226 ring = &adev->gfx.gfx_ring[0];
6227 rb_bufsz = order_base_2(ring->ring_size / 8);
6228 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6229 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6230 #ifdef __BIG_ENDIAN
6231 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6232 #endif
6233 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6234
6235 /* Initialize the ring buffer's write pointers */
6236 ring->wptr = 0;
6237 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6238 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6239
6240 /* set the wb address wether it's enabled or not */
6241 rptr_addr = ring->rptr_gpu_addr;
6242 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6243 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6244 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6245
6246 wptr_gpu_addr = ring->wptr_gpu_addr;
6247 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6248 lower_32_bits(wptr_gpu_addr));
6249 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6250 upper_32_bits(wptr_gpu_addr));
6251
6252 mdelay(1);
6253 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6254
6255 rb_addr = ring->gpu_addr >> 8;
6256 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6257 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6258
6259 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6260
6261 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6262 mutex_unlock(&adev->srbm_mutex);
6263
6264 /* Init gfx ring 1 for pipe 1 */
6265 if (adev->gfx.num_gfx_rings > 1) {
6266 mutex_lock(&adev->srbm_mutex);
6267 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6268 /* maximum supported gfx ring is 2 */
6269 ring = &adev->gfx.gfx_ring[1];
6270 rb_bufsz = order_base_2(ring->ring_size / 8);
6271 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6272 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6273 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6274 /* Initialize the ring buffer's write pointers */
6275 ring->wptr = 0;
6276 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6277 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6278 /* Set the wb address wether it's enabled or not */
6279 rptr_addr = ring->rptr_gpu_addr;
6280 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6281 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6282 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6283 wptr_gpu_addr = ring->wptr_gpu_addr;
6284 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6285 lower_32_bits(wptr_gpu_addr));
6286 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6287 upper_32_bits(wptr_gpu_addr));
6288
6289 mdelay(1);
6290 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6291
6292 rb_addr = ring->gpu_addr >> 8;
6293 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6294 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6295 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6296
6297 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6298 mutex_unlock(&adev->srbm_mutex);
6299 }
6300 /* Switch to pipe 0 */
6301 mutex_lock(&adev->srbm_mutex);
6302 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6303 mutex_unlock(&adev->srbm_mutex);
6304
6305 /* start the ring */
6306 gfx_v10_0_cp_gfx_start(adev);
6307
6308 return 0;
6309 }
6310
gfx_v10_0_cp_compute_enable(struct amdgpu_device * adev,bool enable)6311 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6312 {
6313 if (enable) {
6314 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6315 case IP_VERSION(10, 3, 0):
6316 case IP_VERSION(10, 3, 2):
6317 case IP_VERSION(10, 3, 1):
6318 case IP_VERSION(10, 3, 4):
6319 case IP_VERSION(10, 3, 5):
6320 case IP_VERSION(10, 3, 6):
6321 case IP_VERSION(10, 3, 3):
6322 case IP_VERSION(10, 3, 7):
6323 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6324 break;
6325 default:
6326 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6327 break;
6328 }
6329 } else {
6330 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6331 case IP_VERSION(10, 3, 0):
6332 case IP_VERSION(10, 3, 2):
6333 case IP_VERSION(10, 3, 1):
6334 case IP_VERSION(10, 3, 4):
6335 case IP_VERSION(10, 3, 5):
6336 case IP_VERSION(10, 3, 6):
6337 case IP_VERSION(10, 3, 3):
6338 case IP_VERSION(10, 3, 7):
6339 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6340 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6341 CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6342 break;
6343 default:
6344 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6345 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6346 CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6347 break;
6348 }
6349 adev->gfx.kiq[0].ring.sched.ready = false;
6350 }
6351 udelay(50);
6352 }
6353
gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device * adev)6354 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6355 {
6356 const struct gfx_firmware_header_v1_0 *mec_hdr;
6357 const __le32 *fw_data;
6358 unsigned int i;
6359 u32 tmp;
6360 u32 usec_timeout = 50000; /* Wait for 50 ms */
6361
6362 if (!adev->gfx.mec_fw)
6363 return -EINVAL;
6364
6365 gfx_v10_0_cp_compute_enable(adev, false);
6366
6367 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6368 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6369
6370 fw_data = (const __le32 *)
6371 (adev->gfx.mec_fw->data +
6372 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6373
6374 /* Trigger an invalidation of the L1 instruction caches */
6375 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6376 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6377 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6378
6379 /* Wait for invalidation complete */
6380 for (i = 0; i < usec_timeout; i++) {
6381 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6382 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6383 INVALIDATE_CACHE_COMPLETE))
6384 break;
6385 udelay(1);
6386 }
6387
6388 if (i >= usec_timeout) {
6389 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6390 return -EINVAL;
6391 }
6392
6393 if (amdgpu_emu_mode == 1)
6394 adev->hdp.funcs->flush_hdp(adev, NULL);
6395
6396 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6397 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6398 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6399 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6400 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6401
6402 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6403 0xFFFFF000);
6404 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6405 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6406
6407 /* MEC1 */
6408 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6409
6410 for (i = 0; i < mec_hdr->jt_size; i++)
6411 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6412 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6413
6414 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6415
6416 /*
6417 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6418 * different microcode than MEC1.
6419 */
6420
6421 return 0;
6422 }
6423
gfx_v10_0_kiq_setting(struct amdgpu_ring * ring)6424 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6425 {
6426 uint32_t tmp;
6427 struct amdgpu_device *adev = ring->adev;
6428
6429 /* tell RLC which is KIQ queue */
6430 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6431 case IP_VERSION(10, 3, 0):
6432 case IP_VERSION(10, 3, 2):
6433 case IP_VERSION(10, 3, 1):
6434 case IP_VERSION(10, 3, 4):
6435 case IP_VERSION(10, 3, 5):
6436 case IP_VERSION(10, 3, 6):
6437 case IP_VERSION(10, 3, 3):
6438 case IP_VERSION(10, 3, 7):
6439 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6440 tmp &= 0xffffff00;
6441 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6442 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6443 tmp |= 0x80;
6444 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6445 break;
6446 default:
6447 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6448 tmp &= 0xffffff00;
6449 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6450 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6451 tmp |= 0x80;
6452 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6453 break;
6454 }
6455 }
6456
gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device * adev,struct v10_gfx_mqd * mqd,struct amdgpu_mqd_prop * prop)6457 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6458 struct v10_gfx_mqd *mqd,
6459 struct amdgpu_mqd_prop *prop)
6460 {
6461 bool priority = 0;
6462 u32 tmp;
6463
6464 /* set up default queue priority level
6465 * 0x0 = low priority, 0x1 = high priority
6466 */
6467 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6468 priority = 1;
6469
6470 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6471 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6472 mqd->cp_gfx_hqd_queue_priority = tmp;
6473 }
6474
gfx_v10_0_gfx_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)6475 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6476 struct amdgpu_mqd_prop *prop)
6477 {
6478 struct v10_gfx_mqd *mqd = m;
6479 uint64_t hqd_gpu_addr, wb_gpu_addr;
6480 uint32_t tmp;
6481 uint32_t rb_bufsz;
6482
6483 /* set up gfx hqd wptr */
6484 mqd->cp_gfx_hqd_wptr = 0;
6485 mqd->cp_gfx_hqd_wptr_hi = 0;
6486
6487 /* set the pointer to the MQD */
6488 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6489 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6490
6491 /* set up mqd control */
6492 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6493 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6494 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6495 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6496 mqd->cp_gfx_mqd_control = tmp;
6497
6498 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6499 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6500 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6501 mqd->cp_gfx_hqd_vmid = 0;
6502
6503 /* set up gfx queue priority */
6504 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6505
6506 /* set up time quantum */
6507 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6508 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6509 mqd->cp_gfx_hqd_quantum = tmp;
6510
6511 /* set up gfx hqd base. this is similar as CP_RB_BASE */
6512 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6513 mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6514 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6515
6516 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6517 wb_gpu_addr = prop->rptr_gpu_addr;
6518 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6519 mqd->cp_gfx_hqd_rptr_addr_hi =
6520 upper_32_bits(wb_gpu_addr) & 0xffff;
6521
6522 /* set up rb_wptr_poll addr */
6523 wb_gpu_addr = prop->wptr_gpu_addr;
6524 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6525 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6526
6527 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6528 rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6529 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6530 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6531 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6532 #ifdef __BIG_ENDIAN
6533 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6534 #endif
6535 mqd->cp_gfx_hqd_cntl = tmp;
6536
6537 /* set up cp_doorbell_control */
6538 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6539 if (prop->use_doorbell) {
6540 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6541 DOORBELL_OFFSET, prop->doorbell_index);
6542 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6543 DOORBELL_EN, 1);
6544 } else
6545 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6546 DOORBELL_EN, 0);
6547 mqd->cp_rb_doorbell_control = tmp;
6548
6549 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6550 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6551
6552 /* active the queue */
6553 mqd->cp_gfx_hqd_active = 1;
6554
6555 return 0;
6556 }
6557
gfx_v10_0_gfx_init_queue(struct amdgpu_ring * ring)6558 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6559 {
6560 struct amdgpu_device *adev = ring->adev;
6561 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6562 int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6563
6564 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6565 memset((void *)mqd, 0, sizeof(*mqd));
6566 mutex_lock(&adev->srbm_mutex);
6567 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6568 amdgpu_ring_init_mqd(ring);
6569
6570 /*
6571 * if there are 2 gfx rings, set the lower doorbell
6572 * range of the first ring, otherwise the range of
6573 * the second ring will override the first ring
6574 */
6575 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6576 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6577
6578 nv_grbm_select(adev, 0, 0, 0, 0);
6579 mutex_unlock(&adev->srbm_mutex);
6580 if (adev->gfx.me.mqd_backup[mqd_idx])
6581 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6582 } else {
6583 mutex_lock(&adev->srbm_mutex);
6584 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6585 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6586 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6587
6588 nv_grbm_select(adev, 0, 0, 0, 0);
6589 mutex_unlock(&adev->srbm_mutex);
6590 /* restore mqd with the backup copy */
6591 if (adev->gfx.me.mqd_backup[mqd_idx])
6592 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6593 /* reset the ring */
6594 ring->wptr = 0;
6595 *ring->wptr_cpu_addr = 0;
6596 amdgpu_ring_clear_ring(ring);
6597 }
6598
6599 return 0;
6600 }
6601
gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device * adev)6602 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6603 {
6604 int r, i;
6605 struct amdgpu_ring *ring;
6606
6607 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6608 ring = &adev->gfx.gfx_ring[i];
6609
6610 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6611 if (unlikely(r != 0))
6612 return r;
6613
6614 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6615 if (!r) {
6616 r = gfx_v10_0_gfx_init_queue(ring);
6617 amdgpu_bo_kunmap(ring->mqd_obj);
6618 ring->mqd_ptr = NULL;
6619 }
6620 amdgpu_bo_unreserve(ring->mqd_obj);
6621 if (r)
6622 return r;
6623 }
6624
6625 r = amdgpu_gfx_enable_kgq(adev, 0);
6626 if (r)
6627 return r;
6628
6629 return gfx_v10_0_cp_gfx_start(adev);
6630 }
6631
gfx_v10_0_compute_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)6632 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6633 struct amdgpu_mqd_prop *prop)
6634 {
6635 struct v10_compute_mqd *mqd = m;
6636 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6637 uint32_t tmp;
6638
6639 mqd->header = 0xC0310800;
6640 mqd->compute_pipelinestat_enable = 0x00000001;
6641 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6642 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6643 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6644 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6645 mqd->compute_misc_reserved = 0x00000003;
6646
6647 eop_base_addr = prop->eop_gpu_addr >> 8;
6648 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6649 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6650
6651 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6652 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6653 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6654 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6655
6656 mqd->cp_hqd_eop_control = tmp;
6657
6658 /* enable doorbell? */
6659 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6660
6661 if (prop->use_doorbell) {
6662 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6663 DOORBELL_OFFSET, prop->doorbell_index);
6664 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6665 DOORBELL_EN, 1);
6666 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6667 DOORBELL_SOURCE, 0);
6668 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6669 DOORBELL_HIT, 0);
6670 } else {
6671 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6672 DOORBELL_EN, 0);
6673 }
6674
6675 mqd->cp_hqd_pq_doorbell_control = tmp;
6676
6677 /* disable the queue if it's active */
6678 mqd->cp_hqd_dequeue_request = 0;
6679 mqd->cp_hqd_pq_rptr = 0;
6680 mqd->cp_hqd_pq_wptr_lo = 0;
6681 mqd->cp_hqd_pq_wptr_hi = 0;
6682
6683 /* set the pointer to the MQD */
6684 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6685 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6686
6687 /* set MQD vmid to 0 */
6688 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6689 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6690 mqd->cp_mqd_control = tmp;
6691
6692 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6693 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6694 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6695 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6696
6697 /* set up the HQD, this is similar to CP_RB0_CNTL */
6698 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6699 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6700 (order_base_2(prop->queue_size / 4) - 1));
6701 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6702 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6703 #ifdef __BIG_ENDIAN
6704 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6705 #endif
6706 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
6707 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
6708 prop->allow_tunneling);
6709 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6710 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6711 mqd->cp_hqd_pq_control = tmp;
6712
6713 /* set the wb address whether it's enabled or not */
6714 wb_gpu_addr = prop->rptr_gpu_addr;
6715 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6716 mqd->cp_hqd_pq_rptr_report_addr_hi =
6717 upper_32_bits(wb_gpu_addr) & 0xffff;
6718
6719 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6720 wb_gpu_addr = prop->wptr_gpu_addr;
6721 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6722 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6723
6724 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6725 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6726
6727 /* set the vmid for the queue */
6728 mqd->cp_hqd_vmid = 0;
6729
6730 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6731 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6732 mqd->cp_hqd_persistent_state = tmp;
6733
6734 /* set MIN_IB_AVAIL_SIZE */
6735 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6736 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6737 mqd->cp_hqd_ib_control = tmp;
6738
6739 /* set static priority for a compute queue/ring */
6740 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
6741 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
6742
6743 mqd->cp_hqd_active = prop->hqd_active;
6744
6745 return 0;
6746 }
6747
gfx_v10_0_kiq_init_register(struct amdgpu_ring * ring)6748 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6749 {
6750 struct amdgpu_device *adev = ring->adev;
6751 struct v10_compute_mqd *mqd = ring->mqd_ptr;
6752 int j;
6753
6754 /* inactivate the queue */
6755 if (amdgpu_sriov_vf(adev))
6756 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6757
6758 /* disable wptr polling */
6759 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6760
6761 /* disable the queue if it's active */
6762 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6763 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6764 for (j = 0; j < adev->usec_timeout; j++) {
6765 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6766 break;
6767 udelay(1);
6768 }
6769 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6770 mqd->cp_hqd_dequeue_request);
6771 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6772 mqd->cp_hqd_pq_rptr);
6773 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6774 mqd->cp_hqd_pq_wptr_lo);
6775 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6776 mqd->cp_hqd_pq_wptr_hi);
6777 }
6778
6779 /* disable doorbells */
6780 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
6781
6782 /* write the EOP addr */
6783 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6784 mqd->cp_hqd_eop_base_addr_lo);
6785 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6786 mqd->cp_hqd_eop_base_addr_hi);
6787
6788 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6789 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6790 mqd->cp_hqd_eop_control);
6791
6792 /* set the pointer to the MQD */
6793 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6794 mqd->cp_mqd_base_addr_lo);
6795 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6796 mqd->cp_mqd_base_addr_hi);
6797
6798 /* set MQD vmid to 0 */
6799 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6800 mqd->cp_mqd_control);
6801
6802 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6803 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6804 mqd->cp_hqd_pq_base_lo);
6805 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6806 mqd->cp_hqd_pq_base_hi);
6807
6808 /* set up the HQD, this is similar to CP_RB0_CNTL */
6809 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6810 mqd->cp_hqd_pq_control);
6811
6812 /* set the wb address whether it's enabled or not */
6813 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6814 mqd->cp_hqd_pq_rptr_report_addr_lo);
6815 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6816 mqd->cp_hqd_pq_rptr_report_addr_hi);
6817
6818 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6819 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6820 mqd->cp_hqd_pq_wptr_poll_addr_lo);
6821 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6822 mqd->cp_hqd_pq_wptr_poll_addr_hi);
6823
6824 /* enable the doorbell if requested */
6825 if (ring->use_doorbell) {
6826 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6827 (adev->doorbell_index.kiq * 2) << 2);
6828 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6829 (adev->doorbell_index.userqueue_end * 2) << 2);
6830 }
6831
6832 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6833 mqd->cp_hqd_pq_doorbell_control);
6834
6835 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6836 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6837 mqd->cp_hqd_pq_wptr_lo);
6838 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6839 mqd->cp_hqd_pq_wptr_hi);
6840
6841 /* set the vmid for the queue */
6842 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6843
6844 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6845 mqd->cp_hqd_persistent_state);
6846
6847 /* activate the queue */
6848 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6849 mqd->cp_hqd_active);
6850
6851 if (ring->use_doorbell)
6852 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6853
6854 return 0;
6855 }
6856
gfx_v10_0_kiq_init_queue(struct amdgpu_ring * ring)6857 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6858 {
6859 struct amdgpu_device *adev = ring->adev;
6860 struct v10_compute_mqd *mqd = ring->mqd_ptr;
6861
6862 gfx_v10_0_kiq_setting(ring);
6863
6864 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6865 /* reset MQD to a clean status */
6866 if (adev->gfx.kiq[0].mqd_backup)
6867 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
6868
6869 /* reset ring buffer */
6870 ring->wptr = 0;
6871 amdgpu_ring_clear_ring(ring);
6872
6873 mutex_lock(&adev->srbm_mutex);
6874 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6875 gfx_v10_0_kiq_init_register(ring);
6876 nv_grbm_select(adev, 0, 0, 0, 0);
6877 mutex_unlock(&adev->srbm_mutex);
6878 } else {
6879 memset((void *)mqd, 0, sizeof(*mqd));
6880 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
6881 amdgpu_ring_clear_ring(ring);
6882 mutex_lock(&adev->srbm_mutex);
6883 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6884 amdgpu_ring_init_mqd(ring);
6885 gfx_v10_0_kiq_init_register(ring);
6886 nv_grbm_select(adev, 0, 0, 0, 0);
6887 mutex_unlock(&adev->srbm_mutex);
6888
6889 if (adev->gfx.kiq[0].mqd_backup)
6890 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
6891 }
6892
6893 return 0;
6894 }
6895
gfx_v10_0_kcq_init_queue(struct amdgpu_ring * ring)6896 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6897 {
6898 struct amdgpu_device *adev = ring->adev;
6899 struct v10_compute_mqd *mqd = ring->mqd_ptr;
6900 int mqd_idx = ring - &adev->gfx.compute_ring[0];
6901
6902 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6903 memset((void *)mqd, 0, sizeof(*mqd));
6904 mutex_lock(&adev->srbm_mutex);
6905 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6906 amdgpu_ring_init_mqd(ring);
6907 nv_grbm_select(adev, 0, 0, 0, 0);
6908 mutex_unlock(&adev->srbm_mutex);
6909
6910 if (adev->gfx.mec.mqd_backup[mqd_idx])
6911 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6912 } else {
6913 /* restore MQD to a clean status */
6914 if (adev->gfx.mec.mqd_backup[mqd_idx])
6915 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6916 /* reset ring buffer */
6917 ring->wptr = 0;
6918 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
6919 amdgpu_ring_clear_ring(ring);
6920 }
6921
6922 return 0;
6923 }
6924
gfx_v10_0_kiq_resume(struct amdgpu_device * adev)6925 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6926 {
6927 struct amdgpu_ring *ring;
6928 int r;
6929
6930 ring = &adev->gfx.kiq[0].ring;
6931
6932 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6933 if (unlikely(r != 0))
6934 return r;
6935
6936 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6937 if (unlikely(r != 0)) {
6938 amdgpu_bo_unreserve(ring->mqd_obj);
6939 return r;
6940 }
6941
6942 gfx_v10_0_kiq_init_queue(ring);
6943 amdgpu_bo_kunmap(ring->mqd_obj);
6944 ring->mqd_ptr = NULL;
6945 amdgpu_bo_unreserve(ring->mqd_obj);
6946 return 0;
6947 }
6948
gfx_v10_0_kcq_resume(struct amdgpu_device * adev)6949 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6950 {
6951 struct amdgpu_ring *ring = NULL;
6952 int r = 0, i;
6953
6954 gfx_v10_0_cp_compute_enable(adev, true);
6955
6956 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6957 ring = &adev->gfx.compute_ring[i];
6958
6959 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6960 if (unlikely(r != 0))
6961 goto done;
6962 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6963 if (!r) {
6964 r = gfx_v10_0_kcq_init_queue(ring);
6965 amdgpu_bo_kunmap(ring->mqd_obj);
6966 ring->mqd_ptr = NULL;
6967 }
6968 amdgpu_bo_unreserve(ring->mqd_obj);
6969 if (r)
6970 goto done;
6971 }
6972
6973 r = amdgpu_gfx_enable_kcq(adev, 0);
6974 done:
6975 return r;
6976 }
6977
gfx_v10_0_cp_resume(struct amdgpu_device * adev)6978 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6979 {
6980 int r, i;
6981 struct amdgpu_ring *ring;
6982
6983 if (!(adev->flags & AMD_IS_APU))
6984 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6985
6986 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6987 /* legacy firmware loading */
6988 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6989 if (r)
6990 return r;
6991
6992 r = gfx_v10_0_cp_compute_load_microcode(adev);
6993 if (r)
6994 return r;
6995 }
6996
6997 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
6998 r = amdgpu_mes_kiq_hw_init(adev);
6999 else
7000 r = gfx_v10_0_kiq_resume(adev);
7001 if (r)
7002 return r;
7003
7004 r = gfx_v10_0_kcq_resume(adev);
7005 if (r)
7006 return r;
7007
7008 if (!amdgpu_async_gfx_ring) {
7009 r = gfx_v10_0_cp_gfx_resume(adev);
7010 if (r)
7011 return r;
7012 } else {
7013 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7014 if (r)
7015 return r;
7016 }
7017
7018 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7019 ring = &adev->gfx.gfx_ring[i];
7020 r = amdgpu_ring_test_helper(ring);
7021 if (r)
7022 return r;
7023 }
7024
7025 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7026 ring = &adev->gfx.compute_ring[i];
7027 r = amdgpu_ring_test_helper(ring);
7028 if (r)
7029 return r;
7030 }
7031
7032 return 0;
7033 }
7034
gfx_v10_0_cp_enable(struct amdgpu_device * adev,bool enable)7035 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7036 {
7037 gfx_v10_0_cp_gfx_enable(adev, enable);
7038 gfx_v10_0_cp_compute_enable(adev, enable);
7039 }
7040
gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device * adev)7041 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7042 {
7043 uint32_t data, pattern = 0xDEADBEEF;
7044
7045 /*
7046 * check if mmVGT_ESGS_RING_SIZE_UMD
7047 * has been remapped to mmVGT_ESGS_RING_SIZE
7048 */
7049 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7050 case IP_VERSION(10, 3, 0):
7051 case IP_VERSION(10, 3, 2):
7052 case IP_VERSION(10, 3, 4):
7053 case IP_VERSION(10, 3, 5):
7054 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7055 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7056 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7057
7058 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7059 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7060 return true;
7061 }
7062 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7063 break;
7064 case IP_VERSION(10, 3, 1):
7065 case IP_VERSION(10, 3, 3):
7066 case IP_VERSION(10, 3, 6):
7067 case IP_VERSION(10, 3, 7):
7068 return true;
7069 default:
7070 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7071 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7072 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7073
7074 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7075 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7076 return true;
7077 }
7078 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7079 break;
7080 }
7081
7082 return false;
7083 }
7084
gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device * adev)7085 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7086 {
7087 uint32_t data;
7088
7089 if (amdgpu_sriov_vf(adev))
7090 return;
7091
7092 /*
7093 * Initialize cam_index to 0
7094 * index will auto-inc after each data writing
7095 */
7096 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7097
7098 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7099 case IP_VERSION(10, 3, 0):
7100 case IP_VERSION(10, 3, 2):
7101 case IP_VERSION(10, 3, 1):
7102 case IP_VERSION(10, 3, 4):
7103 case IP_VERSION(10, 3, 5):
7104 case IP_VERSION(10, 3, 6):
7105 case IP_VERSION(10, 3, 3):
7106 case IP_VERSION(10, 3, 7):
7107 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7108 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7109 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7110 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7111 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7112 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7113 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7114
7115 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7116 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7117 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7118 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7119 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7120 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7121 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7122
7123 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7124 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7125 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7126 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7127 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7128 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7129 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7130
7131 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7132 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7133 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7134 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7135 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7136 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7137 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7138
7139 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7140 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7141 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7142 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7143 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7144 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7145 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7146
7147 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7148 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7149 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7150 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7151 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7152 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7153 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7154
7155 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7156 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7157 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7158 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7159 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7160 break;
7161 default:
7162 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7163 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7164 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7165 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7166 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7167 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7168 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7169
7170 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7171 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7172 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7173 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7174 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7175 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7176 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7177
7178 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7179 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7180 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7181 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7182 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7183 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7184 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7185
7186 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7187 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7188 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7189 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7190 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7191 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7192 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7193
7194 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7195 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7196 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7197 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7198 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7199 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7200 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7201
7202 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7203 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7204 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7205 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7206 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7207 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7208 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7209
7210 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7211 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7212 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7213 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7214 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7215 break;
7216 }
7217
7218 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7219 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7220 }
7221
gfx_v10_0_disable_gpa_mode(struct amdgpu_device * adev)7222 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7223 {
7224 uint32_t data;
7225
7226 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7227 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7228 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7229
7230 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7231 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7232 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7233 }
7234
gfx_v10_0_hw_init(void * handle)7235 static int gfx_v10_0_hw_init(void *handle)
7236 {
7237 int r;
7238 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7239
7240 if (!amdgpu_emu_mode)
7241 gfx_v10_0_init_golden_registers(adev);
7242
7243 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7244 /**
7245 * For gfx 10, rlc firmware loading relies on smu firmware is
7246 * loaded firstly, so in direct type, it has to load smc ucode
7247 * here before rlc.
7248 */
7249 if (!(adev->flags & AMD_IS_APU)) {
7250 r = amdgpu_pm_load_smu_firmware(adev, NULL);
7251 if (r)
7252 return r;
7253 }
7254 gfx_v10_0_disable_gpa_mode(adev);
7255 }
7256
7257 /* if GRBM CAM not remapped, set up the remapping */
7258 if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7259 gfx_v10_0_setup_grbm_cam_remapping(adev);
7260
7261 gfx_v10_0_constants_init(adev);
7262
7263 r = gfx_v10_0_rlc_resume(adev);
7264 if (r)
7265 return r;
7266
7267 /*
7268 * init golden registers and rlc resume may override some registers,
7269 * reconfig them here
7270 */
7271 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) ||
7272 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) ||
7273 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
7274 gfx_v10_0_tcp_harvest(adev);
7275
7276 r = gfx_v10_0_cp_resume(adev);
7277 if (r)
7278 return r;
7279
7280 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
7281 gfx_v10_3_program_pbb_mode(adev);
7282
7283 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev))
7284 gfx_v10_3_set_power_brake_sequence(adev);
7285
7286 return r;
7287 }
7288
gfx_v10_0_hw_fini(void * handle)7289 static int gfx_v10_0_hw_fini(void *handle)
7290 {
7291 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7292
7293 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7294 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7295
7296 /* WA added for Vangogh asic fixing the SMU suspend failure
7297 * It needs to set power gating again during gfxoff control
7298 * otherwise the gfxoff disallowing will be failed to set.
7299 */
7300 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
7301 gfx_v10_0_set_powergating_state(handle, AMD_PG_STATE_UNGATE);
7302
7303 if (!adev->no_hw_access) {
7304 if (amdgpu_async_gfx_ring) {
7305 if (amdgpu_gfx_disable_kgq(adev, 0))
7306 DRM_ERROR("KGQ disable failed\n");
7307 }
7308
7309 if (amdgpu_gfx_disable_kcq(adev, 0))
7310 DRM_ERROR("KCQ disable failed\n");
7311 }
7312
7313 if (amdgpu_sriov_vf(adev)) {
7314 gfx_v10_0_cp_gfx_enable(adev, false);
7315 /* Remove the steps of clearing KIQ position.
7316 * It causes GFX hang when another Win guest is rendering.
7317 */
7318 return 0;
7319 }
7320 gfx_v10_0_cp_enable(adev, false);
7321 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7322
7323 return 0;
7324 }
7325
gfx_v10_0_suspend(void * handle)7326 static int gfx_v10_0_suspend(void *handle)
7327 {
7328 return gfx_v10_0_hw_fini(handle);
7329 }
7330
gfx_v10_0_resume(void * handle)7331 static int gfx_v10_0_resume(void *handle)
7332 {
7333 return gfx_v10_0_hw_init(handle);
7334 }
7335
gfx_v10_0_is_idle(void * handle)7336 static bool gfx_v10_0_is_idle(void *handle)
7337 {
7338 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7339
7340 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7341 GRBM_STATUS, GUI_ACTIVE))
7342 return false;
7343 else
7344 return true;
7345 }
7346
gfx_v10_0_wait_for_idle(void * handle)7347 static int gfx_v10_0_wait_for_idle(void *handle)
7348 {
7349 unsigned int i;
7350 u32 tmp;
7351 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7352
7353 for (i = 0; i < adev->usec_timeout; i++) {
7354 /* read MC_STATUS */
7355 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7356 GRBM_STATUS__GUI_ACTIVE_MASK;
7357
7358 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7359 return 0;
7360 udelay(1);
7361 }
7362 return -ETIMEDOUT;
7363 }
7364
gfx_v10_0_soft_reset(void * handle)7365 static int gfx_v10_0_soft_reset(void *handle)
7366 {
7367 u32 grbm_soft_reset = 0;
7368 u32 tmp;
7369 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7370
7371 /* GRBM_STATUS */
7372 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7373 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7374 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7375 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7376 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7377 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7378 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7379 GRBM_SOFT_RESET, SOFT_RESET_CP,
7380 1);
7381 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7382 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7383 1);
7384 }
7385
7386 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7387 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7388 GRBM_SOFT_RESET, SOFT_RESET_CP,
7389 1);
7390 }
7391
7392 /* GRBM_STATUS2 */
7393 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7394 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7395 case IP_VERSION(10, 3, 0):
7396 case IP_VERSION(10, 3, 2):
7397 case IP_VERSION(10, 3, 1):
7398 case IP_VERSION(10, 3, 4):
7399 case IP_VERSION(10, 3, 5):
7400 case IP_VERSION(10, 3, 6):
7401 case IP_VERSION(10, 3, 3):
7402 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7403 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7404 GRBM_SOFT_RESET,
7405 SOFT_RESET_RLC,
7406 1);
7407 break;
7408 default:
7409 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7410 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7411 GRBM_SOFT_RESET,
7412 SOFT_RESET_RLC,
7413 1);
7414 break;
7415 }
7416
7417 if (grbm_soft_reset) {
7418 /* stop the rlc */
7419 gfx_v10_0_rlc_stop(adev);
7420
7421 /* Disable GFX parsing/prefetching */
7422 gfx_v10_0_cp_gfx_enable(adev, false);
7423
7424 /* Disable MEC parsing/prefetching */
7425 gfx_v10_0_cp_compute_enable(adev, false);
7426
7427 if (grbm_soft_reset) {
7428 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7429 tmp |= grbm_soft_reset;
7430 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7431 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7432 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7433
7434 udelay(50);
7435
7436 tmp &= ~grbm_soft_reset;
7437 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7438 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7439 }
7440
7441 /* Wait a little for things to settle down */
7442 udelay(50);
7443 }
7444 return 0;
7445 }
7446
gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device * adev)7447 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7448 {
7449 uint64_t clock, clock_lo, clock_hi, hi_check;
7450
7451 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7452 case IP_VERSION(10, 1, 3):
7453 case IP_VERSION(10, 1, 4):
7454 preempt_disable();
7455 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7456 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7457 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7458 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7459 * roughly every 42 seconds.
7460 */
7461 if (hi_check != clock_hi) {
7462 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7463 clock_hi = hi_check;
7464 }
7465 preempt_enable();
7466 clock = clock_lo | (clock_hi << 32ULL);
7467 break;
7468 case IP_VERSION(10, 3, 1):
7469 case IP_VERSION(10, 3, 3):
7470 case IP_VERSION(10, 3, 7):
7471 preempt_disable();
7472 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7473 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7474 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7475 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7476 * roughly every 42 seconds.
7477 */
7478 if (hi_check != clock_hi) {
7479 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7480 clock_hi = hi_check;
7481 }
7482 preempt_enable();
7483 clock = clock_lo | (clock_hi << 32ULL);
7484 break;
7485 case IP_VERSION(10, 3, 6):
7486 preempt_disable();
7487 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7488 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7489 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7490 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7491 * roughly every 42 seconds.
7492 */
7493 if (hi_check != clock_hi) {
7494 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7495 clock_hi = hi_check;
7496 }
7497 preempt_enable();
7498 clock = clock_lo | (clock_hi << 32ULL);
7499 break;
7500 default:
7501 preempt_disable();
7502 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7503 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7504 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7505 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7506 * roughly every 42 seconds.
7507 */
7508 if (hi_check != clock_hi) {
7509 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7510 clock_hi = hi_check;
7511 }
7512 preempt_enable();
7513 clock = clock_lo | (clock_hi << 32ULL);
7514 break;
7515 }
7516 return clock;
7517 }
7518
gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring * ring,uint32_t vmid,uint32_t gds_base,uint32_t gds_size,uint32_t gws_base,uint32_t gws_size,uint32_t oa_base,uint32_t oa_size)7519 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7520 uint32_t vmid,
7521 uint32_t gds_base, uint32_t gds_size,
7522 uint32_t gws_base, uint32_t gws_size,
7523 uint32_t oa_base, uint32_t oa_size)
7524 {
7525 struct amdgpu_device *adev = ring->adev;
7526
7527 /* GDS Base */
7528 gfx_v10_0_write_data_to_reg(ring, 0, false,
7529 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7530 gds_base);
7531
7532 /* GDS Size */
7533 gfx_v10_0_write_data_to_reg(ring, 0, false,
7534 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7535 gds_size);
7536
7537 /* GWS */
7538 gfx_v10_0_write_data_to_reg(ring, 0, false,
7539 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7540 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7541
7542 /* OA */
7543 gfx_v10_0_write_data_to_reg(ring, 0, false,
7544 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7545 (1 << (oa_size + oa_base)) - (1 << oa_base));
7546 }
7547
gfx_v10_0_early_init(void * handle)7548 static int gfx_v10_0_early_init(void *handle)
7549 {
7550 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7551
7552 adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
7553
7554 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7555 case IP_VERSION(10, 1, 10):
7556 case IP_VERSION(10, 1, 1):
7557 case IP_VERSION(10, 1, 2):
7558 case IP_VERSION(10, 1, 3):
7559 case IP_VERSION(10, 1, 4):
7560 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7561 break;
7562 case IP_VERSION(10, 3, 0):
7563 case IP_VERSION(10, 3, 2):
7564 case IP_VERSION(10, 3, 1):
7565 case IP_VERSION(10, 3, 4):
7566 case IP_VERSION(10, 3, 5):
7567 case IP_VERSION(10, 3, 6):
7568 case IP_VERSION(10, 3, 3):
7569 case IP_VERSION(10, 3, 7):
7570 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7571 break;
7572 default:
7573 break;
7574 }
7575
7576 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7577 AMDGPU_MAX_COMPUTE_RINGS);
7578
7579 gfx_v10_0_set_kiq_pm4_funcs(adev);
7580 gfx_v10_0_set_ring_funcs(adev);
7581 gfx_v10_0_set_irq_funcs(adev);
7582 gfx_v10_0_set_gds_init(adev);
7583 gfx_v10_0_set_rlc_funcs(adev);
7584 gfx_v10_0_set_mqd_funcs(adev);
7585
7586 /* init rlcg reg access ctrl */
7587 gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7588
7589 return gfx_v10_0_init_microcode(adev);
7590 }
7591
gfx_v10_0_late_init(void * handle)7592 static int gfx_v10_0_late_init(void *handle)
7593 {
7594 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7595 int r;
7596
7597 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7598 if (r)
7599 return r;
7600
7601 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7602 if (r)
7603 return r;
7604
7605 return 0;
7606 }
7607
gfx_v10_0_is_rlc_enabled(struct amdgpu_device * adev)7608 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7609 {
7610 uint32_t rlc_cntl;
7611
7612 /* if RLC is not enabled, do nothing */
7613 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7614 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7615 }
7616
gfx_v10_0_set_safe_mode(struct amdgpu_device * adev,int xcc_id)7617 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
7618 {
7619 uint32_t data;
7620 unsigned int i;
7621
7622 data = RLC_SAFE_MODE__CMD_MASK;
7623 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7624
7625 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7626 case IP_VERSION(10, 3, 0):
7627 case IP_VERSION(10, 3, 2):
7628 case IP_VERSION(10, 3, 1):
7629 case IP_VERSION(10, 3, 4):
7630 case IP_VERSION(10, 3, 5):
7631 case IP_VERSION(10, 3, 6):
7632 case IP_VERSION(10, 3, 3):
7633 case IP_VERSION(10, 3, 7):
7634 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7635
7636 /* wait for RLC_SAFE_MODE */
7637 for (i = 0; i < adev->usec_timeout; i++) {
7638 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7639 RLC_SAFE_MODE, CMD))
7640 break;
7641 udelay(1);
7642 }
7643 break;
7644 default:
7645 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7646
7647 /* wait for RLC_SAFE_MODE */
7648 for (i = 0; i < adev->usec_timeout; i++) {
7649 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7650 RLC_SAFE_MODE, CMD))
7651 break;
7652 udelay(1);
7653 }
7654 break;
7655 }
7656 }
7657
gfx_v10_0_unset_safe_mode(struct amdgpu_device * adev,int xcc_id)7658 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
7659 {
7660 uint32_t data;
7661
7662 data = RLC_SAFE_MODE__CMD_MASK;
7663 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7664 case IP_VERSION(10, 3, 0):
7665 case IP_VERSION(10, 3, 2):
7666 case IP_VERSION(10, 3, 1):
7667 case IP_VERSION(10, 3, 4):
7668 case IP_VERSION(10, 3, 5):
7669 case IP_VERSION(10, 3, 6):
7670 case IP_VERSION(10, 3, 3):
7671 case IP_VERSION(10, 3, 7):
7672 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7673 break;
7674 default:
7675 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7676 break;
7677 }
7678 }
7679
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)7680 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7681 bool enable)
7682 {
7683 uint32_t data, def;
7684
7685 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7686 return;
7687
7688 /* It is disabled by HW by default */
7689 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7690 /* 0 - Disable some blocks' MGCG */
7691 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7692 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7693 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7694 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7695
7696 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7697 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7698 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7699 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7700 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7701 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7702 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7703 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7704
7705 if (def != data)
7706 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7707
7708 /* MGLS is a global flag to control all MGLS in GFX */
7709 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7710 /* 2 - RLC memory Light sleep */
7711 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7712 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7713 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7714 if (def != data)
7715 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7716 }
7717 /* 3 - CP memory Light sleep */
7718 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7719 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7720 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7721 if (def != data)
7722 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7723 }
7724 }
7725 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7726 /* 1 - MGCG_OVERRIDE */
7727 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7728 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7729 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7730 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7731 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7732 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7733 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7734 if (def != data)
7735 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7736
7737 /* 2 - disable MGLS in CP */
7738 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7739 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7740 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7741 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7742 }
7743
7744 /* 3 - disable MGLS in RLC */
7745 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7746 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7747 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7748 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7749 }
7750
7751 }
7752 }
7753
gfx_v10_0_update_3d_clock_gating(struct amdgpu_device * adev,bool enable)7754 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7755 bool enable)
7756 {
7757 uint32_t data, def;
7758
7759 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7760 return;
7761
7762 /* Enable 3D CGCG/CGLS */
7763 if (enable) {
7764 /* write cmd to clear cgcg/cgls ov */
7765 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7766
7767 /* unset CGCG override */
7768 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7769 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7770
7771 /* update CGCG and CGLS override bits */
7772 if (def != data)
7773 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7774
7775 /* enable 3Dcgcg FSM(0x0000363f) */
7776 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7777 data = 0;
7778
7779 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7780 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7781 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7782
7783 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7784 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7785 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7786
7787 if (def != data)
7788 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7789
7790 /* set IDLE_POLL_COUNT(0x00900100) */
7791 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7792 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7793 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7794 if (def != data)
7795 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7796 } else {
7797 /* Disable CGCG/CGLS */
7798 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7799
7800 /* disable cgcg, cgls should be disabled */
7801 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7802 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7803
7804 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7805 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7806
7807 /* disable cgcg and cgls in FSM */
7808 if (def != data)
7809 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7810 }
7811 }
7812
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable)7813 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7814 bool enable)
7815 {
7816 uint32_t def, data;
7817
7818 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
7819 return;
7820
7821 if (enable) {
7822 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7823
7824 /* unset CGCG override */
7825 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7826 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7827
7828 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7829 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7830
7831 /* update CGCG and CGLS override bits */
7832 if (def != data)
7833 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7834
7835 /* enable cgcg FSM(0x0000363F) */
7836 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7837 data = 0;
7838
7839 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7840 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7841 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7842
7843 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7844 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7845 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7846
7847 if (def != data)
7848 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7849
7850 /* set IDLE_POLL_COUNT(0x00900100) */
7851 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7852 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7853 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7854 if (def != data)
7855 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7856 } else {
7857 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7858
7859 /* reset CGCG/CGLS bits */
7860 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7861 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7862
7863 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7864 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7865
7866 /* disable cgcg and cgls in FSM */
7867 if (def != data)
7868 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7869 }
7870 }
7871
gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device * adev,bool enable)7872 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7873 bool enable)
7874 {
7875 uint32_t def, data;
7876
7877 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
7878 return;
7879
7880 if (enable) {
7881 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7882 /* unset FGCG override */
7883 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7884 /* update FGCG override bits */
7885 if (def != data)
7886 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7887
7888 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7889 /* unset RLC SRAM CLK GATER override */
7890 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7891 /* update RLC SRAM CLK GATER override bits */
7892 if (def != data)
7893 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7894 } else {
7895 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7896 /* reset FGCG bits */
7897 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7898 /* disable FGCG*/
7899 if (def != data)
7900 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7901
7902 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7903 /* reset RLC SRAM CLK GATER bits */
7904 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7905 /* disable RLC SRAM CLK*/
7906 if (def != data)
7907 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7908 }
7909 }
7910
gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device * adev)7911 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
7912 {
7913 uint32_t reg_data = 0;
7914 uint32_t reg_idx = 0;
7915 uint32_t i;
7916
7917 const uint32_t tcp_ctrl_regs[] = {
7918 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
7919 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
7920 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
7921 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
7922 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
7923 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
7924 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
7925 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
7926 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
7927 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
7928 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
7929 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
7930 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
7931 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
7932 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
7933 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
7934 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
7935 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
7936 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
7937 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
7938 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
7939 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
7940 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
7941 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
7942 };
7943
7944 const uint32_t tcp_ctrl_regs_nv12[] = {
7945 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
7946 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
7947 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
7948 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
7949 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
7950 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
7951 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
7952 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
7953 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
7954 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
7955 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
7956 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
7957 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
7958 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
7959 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
7960 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
7961 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
7962 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
7963 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
7964 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
7965 };
7966
7967 const uint32_t sm_ctlr_regs[] = {
7968 mmCGTS_SA0_QUAD0_SM_CTRL_REG,
7969 mmCGTS_SA0_QUAD1_SM_CTRL_REG,
7970 mmCGTS_SA1_QUAD0_SM_CTRL_REG,
7971 mmCGTS_SA1_QUAD1_SM_CTRL_REG
7972 };
7973
7974 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
7975 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
7976 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
7977 tcp_ctrl_regs_nv12[i];
7978 reg_data = RREG32(reg_idx);
7979 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
7980 WREG32(reg_idx, reg_data);
7981 }
7982 } else {
7983 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
7984 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
7985 tcp_ctrl_regs[i];
7986 reg_data = RREG32(reg_idx);
7987 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
7988 WREG32(reg_idx, reg_data);
7989 }
7990 }
7991
7992 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
7993 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
7994 sm_ctlr_regs[i];
7995 reg_data = RREG32(reg_idx);
7996 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
7997 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
7998 WREG32(reg_idx, reg_data);
7999 }
8000 }
8001
gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable)8002 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8003 bool enable)
8004 {
8005 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8006
8007 if (enable) {
8008 /* enable FGCG firstly*/
8009 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8010 /* CGCG/CGLS should be enabled after MGCG/MGLS
8011 * === MGCG + MGLS ===
8012 */
8013 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8014 /* === CGCG /CGLS for GFX 3D Only === */
8015 gfx_v10_0_update_3d_clock_gating(adev, enable);
8016 /* === CGCG + CGLS === */
8017 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8018
8019 if ((amdgpu_ip_version(adev, GC_HWIP, 0) ==
8020 IP_VERSION(10, 1, 10)) ||
8021 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
8022 IP_VERSION(10, 1, 1)) ||
8023 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
8024 IP_VERSION(10, 1, 2)))
8025 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8026 } else {
8027 /* CGCG/CGLS should be disabled before MGCG/MGLS
8028 * === CGCG + CGLS ===
8029 */
8030 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8031 /* === CGCG /CGLS for GFX 3D Only === */
8032 gfx_v10_0_update_3d_clock_gating(adev, enable);
8033 /* === MGCG + MGLS === */
8034 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8035 /* disable fgcg at last*/
8036 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8037 }
8038
8039 if (adev->cg_flags &
8040 (AMD_CG_SUPPORT_GFX_MGCG |
8041 AMD_CG_SUPPORT_GFX_CGLS |
8042 AMD_CG_SUPPORT_GFX_CGCG |
8043 AMD_CG_SUPPORT_GFX_3D_CGCG |
8044 AMD_CG_SUPPORT_GFX_3D_CGLS))
8045 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8046
8047 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8048
8049 return 0;
8050 }
8051
gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device * adev,unsigned int vmid)8052 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
8053 unsigned int vmid)
8054 {
8055 u32 data;
8056
8057 /* not for *_SOC15 */
8058 data = RREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL);
8059
8060 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
8061 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8062
8063 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8064 }
8065
gfx_v10_0_update_spm_vmid(struct amdgpu_device * adev,struct amdgpu_ring * ring,unsigned int vmid)8066 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
8067 {
8068 amdgpu_gfx_off_ctrl(adev, false);
8069
8070 gfx_v10_0_update_spm_vmid_internal(adev, vmid);
8071
8072 amdgpu_gfx_off_ctrl(adev, true);
8073 }
8074
gfx_v10_0_check_rlcg_range(struct amdgpu_device * adev,uint32_t offset,struct soc15_reg_rlcg * entries,int arr_size)8075 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8076 uint32_t offset,
8077 struct soc15_reg_rlcg *entries, int arr_size)
8078 {
8079 int i;
8080 uint32_t reg;
8081
8082 if (!entries)
8083 return false;
8084
8085 for (i = 0; i < arr_size; i++) {
8086 const struct soc15_reg_rlcg *entry;
8087
8088 entry = &entries[i];
8089 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8090 if (offset == reg)
8091 return true;
8092 }
8093
8094 return false;
8095 }
8096
gfx_v10_0_is_rlcg_access_range(struct amdgpu_device * adev,u32 offset)8097 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8098 {
8099 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8100 }
8101
gfx_v10_cntl_power_gating(struct amdgpu_device * adev,bool enable)8102 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8103 {
8104 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8105
8106 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8107 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8108 else
8109 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8110
8111 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8112
8113 /*
8114 * CGPG enablement required and the register to program the hysteresis value
8115 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8116 * in refclk count. Note that RLC FW is modified to take 16 bits from
8117 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8118 *
8119 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8120 * of CGPG enablement starting point.
8121 * Power/performance team will optimize it and might give a new value later.
8122 */
8123 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8124 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8125 case IP_VERSION(10, 3, 1):
8126 case IP_VERSION(10, 3, 3):
8127 case IP_VERSION(10, 3, 6):
8128 case IP_VERSION(10, 3, 7):
8129 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8130 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8131 break;
8132 default:
8133 break;
8134 }
8135 }
8136 }
8137
gfx_v10_cntl_pg(struct amdgpu_device * adev,bool enable)8138 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8139 {
8140 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8141
8142 gfx_v10_cntl_power_gating(adev, enable);
8143
8144 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8145 }
8146
8147 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8148 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8149 .set_safe_mode = gfx_v10_0_set_safe_mode,
8150 .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8151 .init = gfx_v10_0_rlc_init,
8152 .get_csb_size = gfx_v10_0_get_csb_size,
8153 .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8154 .resume = gfx_v10_0_rlc_resume,
8155 .stop = gfx_v10_0_rlc_stop,
8156 .reset = gfx_v10_0_rlc_reset,
8157 .start = gfx_v10_0_rlc_start,
8158 .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8159 };
8160
8161 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8162 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8163 .set_safe_mode = gfx_v10_0_set_safe_mode,
8164 .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8165 .init = gfx_v10_0_rlc_init,
8166 .get_csb_size = gfx_v10_0_get_csb_size,
8167 .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8168 .resume = gfx_v10_0_rlc_resume,
8169 .stop = gfx_v10_0_rlc_stop,
8170 .reset = gfx_v10_0_rlc_reset,
8171 .start = gfx_v10_0_rlc_start,
8172 .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8173 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8174 };
8175
gfx_v10_0_set_powergating_state(void * handle,enum amd_powergating_state state)8176 static int gfx_v10_0_set_powergating_state(void *handle,
8177 enum amd_powergating_state state)
8178 {
8179 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8180 bool enable = (state == AMD_PG_STATE_GATE);
8181
8182 if (amdgpu_sriov_vf(adev))
8183 return 0;
8184
8185 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8186 case IP_VERSION(10, 1, 10):
8187 case IP_VERSION(10, 1, 1):
8188 case IP_VERSION(10, 1, 2):
8189 case IP_VERSION(10, 3, 0):
8190 case IP_VERSION(10, 3, 2):
8191 case IP_VERSION(10, 3, 4):
8192 case IP_VERSION(10, 3, 5):
8193 amdgpu_gfx_off_ctrl(adev, enable);
8194 break;
8195 case IP_VERSION(10, 3, 1):
8196 case IP_VERSION(10, 3, 3):
8197 case IP_VERSION(10, 3, 6):
8198 case IP_VERSION(10, 3, 7):
8199 if (!enable)
8200 amdgpu_gfx_off_ctrl(adev, false);
8201
8202 gfx_v10_cntl_pg(adev, enable);
8203
8204 if (enable)
8205 amdgpu_gfx_off_ctrl(adev, true);
8206
8207 break;
8208 default:
8209 break;
8210 }
8211 return 0;
8212 }
8213
gfx_v10_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)8214 static int gfx_v10_0_set_clockgating_state(void *handle,
8215 enum amd_clockgating_state state)
8216 {
8217 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8218
8219 if (amdgpu_sriov_vf(adev))
8220 return 0;
8221
8222 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8223 case IP_VERSION(10, 1, 10):
8224 case IP_VERSION(10, 1, 1):
8225 case IP_VERSION(10, 1, 2):
8226 case IP_VERSION(10, 3, 0):
8227 case IP_VERSION(10, 3, 2):
8228 case IP_VERSION(10, 3, 1):
8229 case IP_VERSION(10, 3, 4):
8230 case IP_VERSION(10, 3, 5):
8231 case IP_VERSION(10, 3, 6):
8232 case IP_VERSION(10, 3, 3):
8233 case IP_VERSION(10, 3, 7):
8234 gfx_v10_0_update_gfx_clock_gating(adev,
8235 state == AMD_CG_STATE_GATE);
8236 break;
8237 default:
8238 break;
8239 }
8240 return 0;
8241 }
8242
gfx_v10_0_get_clockgating_state(void * handle,u64 * flags)8243 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)
8244 {
8245 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8246 int data;
8247
8248 /* AMD_CG_SUPPORT_GFX_FGCG */
8249 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8250 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8251 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8252
8253 /* AMD_CG_SUPPORT_GFX_MGCG */
8254 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8255 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8256 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8257
8258 /* AMD_CG_SUPPORT_GFX_CGCG */
8259 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8260 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8261 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8262
8263 /* AMD_CG_SUPPORT_GFX_CGLS */
8264 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8265 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8266
8267 /* AMD_CG_SUPPORT_GFX_RLC_LS */
8268 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8269 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8270 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8271
8272 /* AMD_CG_SUPPORT_GFX_CP_LS */
8273 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8274 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8275 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8276
8277 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8278 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8279 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8280 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8281
8282 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8283 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8284 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8285 }
8286
gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring * ring)8287 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8288 {
8289 /* gfx10 is 32bit rptr*/
8290 return *(uint32_t *)ring->rptr_cpu_addr;
8291 }
8292
gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring * ring)8293 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8294 {
8295 struct amdgpu_device *adev = ring->adev;
8296 u64 wptr;
8297
8298 /* XXX check if swapping is necessary on BE */
8299 if (ring->use_doorbell) {
8300 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8301 } else {
8302 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8303 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8304 }
8305
8306 return wptr;
8307 }
8308
gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring * ring)8309 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8310 {
8311 struct amdgpu_device *adev = ring->adev;
8312 uint32_t *wptr_saved;
8313 uint32_t *is_queue_unmap;
8314 uint64_t aggregated_db_index;
8315 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;
8316 uint64_t wptr_tmp;
8317
8318 if (ring->is_mes_queue) {
8319 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8320 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8321 sizeof(uint32_t));
8322 aggregated_db_index =
8323 amdgpu_mes_get_aggregated_doorbell_index(adev,
8324 AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8325
8326 wptr_tmp = ring->wptr & ring->buf_mask;
8327 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
8328 *wptr_saved = wptr_tmp;
8329 /* assume doorbell always being used by mes mapped queue */
8330 if (*is_queue_unmap) {
8331 WDOORBELL64(aggregated_db_index, wptr_tmp);
8332 WDOORBELL64(ring->doorbell_index, wptr_tmp);
8333 } else {
8334 WDOORBELL64(ring->doorbell_index, wptr_tmp);
8335
8336 if (*is_queue_unmap)
8337 WDOORBELL64(aggregated_db_index, wptr_tmp);
8338 }
8339 } else {
8340 if (ring->use_doorbell) {
8341 /* XXX check if swapping is necessary on BE */
8342 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8343 ring->wptr);
8344 WDOORBELL64(ring->doorbell_index, ring->wptr);
8345 } else {
8346 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
8347 lower_32_bits(ring->wptr));
8348 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
8349 upper_32_bits(ring->wptr));
8350 }
8351 }
8352 }
8353
gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring * ring)8354 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8355 {
8356 /* gfx10 hardware is 32bit rptr */
8357 return *(uint32_t *)ring->rptr_cpu_addr;
8358 }
8359
gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring * ring)8360 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8361 {
8362 u64 wptr;
8363
8364 /* XXX check if swapping is necessary on BE */
8365 if (ring->use_doorbell)
8366 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8367 else
8368 BUG();
8369 return wptr;
8370 }
8371
gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring * ring)8372 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8373 {
8374 struct amdgpu_device *adev = ring->adev;
8375 uint32_t *wptr_saved;
8376 uint32_t *is_queue_unmap;
8377 uint64_t aggregated_db_index;
8378 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;
8379 uint64_t wptr_tmp;
8380
8381 if (ring->is_mes_queue) {
8382 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8383 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8384 sizeof(uint32_t));
8385 aggregated_db_index =
8386 amdgpu_mes_get_aggregated_doorbell_index(adev,
8387 AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8388
8389 wptr_tmp = ring->wptr & ring->buf_mask;
8390 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
8391 *wptr_saved = wptr_tmp;
8392 /* assume doorbell always used by mes mapped queue */
8393 if (*is_queue_unmap) {
8394 WDOORBELL64(aggregated_db_index, wptr_tmp);
8395 WDOORBELL64(ring->doorbell_index, wptr_tmp);
8396 } else {
8397 WDOORBELL64(ring->doorbell_index, wptr_tmp);
8398
8399 if (*is_queue_unmap)
8400 WDOORBELL64(aggregated_db_index, wptr_tmp);
8401 }
8402 } else {
8403 /* XXX check if swapping is necessary on BE */
8404 if (ring->use_doorbell) {
8405 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8406 ring->wptr);
8407 WDOORBELL64(ring->doorbell_index, ring->wptr);
8408 } else {
8409 BUG(); /* only DOORBELL method supported on gfx10 now */
8410 }
8411 }
8412 }
8413
gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)8414 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8415 {
8416 struct amdgpu_device *adev = ring->adev;
8417 u32 ref_and_mask, reg_mem_engine;
8418 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8419
8420 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8421 switch (ring->me) {
8422 case 1:
8423 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8424 break;
8425 case 2:
8426 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8427 break;
8428 default:
8429 return;
8430 }
8431 reg_mem_engine = 0;
8432 } else {
8433 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
8434 reg_mem_engine = 1; /* pfp */
8435 }
8436
8437 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8438 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8439 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8440 ref_and_mask, ref_and_mask, 0x20);
8441 }
8442
gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)8443 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8444 struct amdgpu_job *job,
8445 struct amdgpu_ib *ib,
8446 uint32_t flags)
8447 {
8448 unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8449 u32 header, control = 0;
8450
8451 if (ib->flags & AMDGPU_IB_FLAG_CE)
8452 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8453 else
8454 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8455
8456 control |= ib->length_dw | (vmid << 24);
8457
8458 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8459 control |= INDIRECT_BUFFER_PRE_ENB(1);
8460
8461 if (flags & AMDGPU_IB_PREEMPTED)
8462 control |= INDIRECT_BUFFER_PRE_RESUME(1);
8463
8464 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8465 gfx_v10_0_ring_emit_de_meta(ring,
8466 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8467 }
8468
8469 if (ring->is_mes_queue)
8470 /* inherit vmid from mqd */
8471 control |= 0x400000;
8472
8473 amdgpu_ring_write(ring, header);
8474 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8475 amdgpu_ring_write(ring,
8476 #ifdef __BIG_ENDIAN
8477 (2 << 0) |
8478 #endif
8479 lower_32_bits(ib->gpu_addr));
8480 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8481 amdgpu_ring_write(ring, control);
8482 }
8483
gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)8484 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8485 struct amdgpu_job *job,
8486 struct amdgpu_ib *ib,
8487 uint32_t flags)
8488 {
8489 unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8490 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8491
8492 if (ring->is_mes_queue)
8493 /* inherit vmid from mqd */
8494 control |= 0x40000000;
8495
8496 /* Currently, there is a high possibility to get wave ID mismatch
8497 * between ME and GDS, leading to a hw deadlock, because ME generates
8498 * different wave IDs than the GDS expects. This situation happens
8499 * randomly when at least 5 compute pipes use GDS ordered append.
8500 * The wave IDs generated by ME are also wrong after suspend/resume.
8501 * Those are probably bugs somewhere else in the kernel driver.
8502 *
8503 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8504 * GDS to 0 for this ring (me/pipe).
8505 */
8506 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8507 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8508 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8509 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8510 }
8511
8512 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8513 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8514 amdgpu_ring_write(ring,
8515 #ifdef __BIG_ENDIAN
8516 (2 << 0) |
8517 #endif
8518 lower_32_bits(ib->gpu_addr));
8519 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8520 amdgpu_ring_write(ring, control);
8521 }
8522
gfx_v10_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)8523 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8524 u64 seq, unsigned int flags)
8525 {
8526 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8527 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8528
8529 /* RELEASE_MEM - flush caches, send int */
8530 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8531 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8532 PACKET3_RELEASE_MEM_GCR_GL2_WB |
8533 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8534 PACKET3_RELEASE_MEM_GCR_GLM_WB |
8535 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8536 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8537 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8538 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8539 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8540
8541 /*
8542 * the address should be Qword aligned if 64bit write, Dword
8543 * aligned if only send 32bit data low (discard data high)
8544 */
8545 if (write64bit)
8546 BUG_ON(addr & 0x7);
8547 else
8548 BUG_ON(addr & 0x3);
8549 amdgpu_ring_write(ring, lower_32_bits(addr));
8550 amdgpu_ring_write(ring, upper_32_bits(addr));
8551 amdgpu_ring_write(ring, lower_32_bits(seq));
8552 amdgpu_ring_write(ring, upper_32_bits(seq));
8553 amdgpu_ring_write(ring, ring->is_mes_queue ?
8554 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
8555 }
8556
gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)8557 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8558 {
8559 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8560 uint32_t seq = ring->fence_drv.sync_seq;
8561 uint64_t addr = ring->fence_drv.gpu_addr;
8562
8563 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8564 upper_32_bits(addr), seq, 0xffffffff, 4);
8565 }
8566
gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring * ring,uint16_t pasid,uint32_t flush_type,bool all_hub,uint8_t dst_sel)8567 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8568 uint16_t pasid, uint32_t flush_type,
8569 bool all_hub, uint8_t dst_sel)
8570 {
8571 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8572 amdgpu_ring_write(ring,
8573 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8574 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8575 PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8576 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8577 }
8578
gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)8579 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8580 unsigned int vmid, uint64_t pd_addr)
8581 {
8582 if (ring->is_mes_queue)
8583 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
8584 else
8585 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8586
8587 /* compute doesn't have PFP */
8588 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8589 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8590 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8591 amdgpu_ring_write(ring, 0x0);
8592 }
8593 }
8594
gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)8595 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8596 u64 seq, unsigned int flags)
8597 {
8598 struct amdgpu_device *adev = ring->adev;
8599
8600 /* we only allocate 32bit for each seq wb address */
8601 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8602
8603 /* write fence seq to the "addr" */
8604 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8605 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8606 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8607 amdgpu_ring_write(ring, lower_32_bits(addr));
8608 amdgpu_ring_write(ring, upper_32_bits(addr));
8609 amdgpu_ring_write(ring, lower_32_bits(seq));
8610
8611 if (flags & AMDGPU_FENCE_FLAG_INT) {
8612 /* set register to trigger INT */
8613 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8614 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8615 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8616 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8617 amdgpu_ring_write(ring, 0);
8618 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8619 }
8620 }
8621
gfx_v10_0_ring_emit_sb(struct amdgpu_ring * ring)8622 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8623 {
8624 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8625 amdgpu_ring_write(ring, 0);
8626 }
8627
gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring * ring,uint32_t flags)8628 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8629 uint32_t flags)
8630 {
8631 uint32_t dw2 = 0;
8632
8633 if (ring->adev->gfx.mcbp)
8634 gfx_v10_0_ring_emit_ce_meta(ring,
8635 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8636
8637 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8638 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8639 /* set load_global_config & load_global_uconfig */
8640 dw2 |= 0x8001;
8641 /* set load_cs_sh_regs */
8642 dw2 |= 0x01000000;
8643 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8644 dw2 |= 0x10002;
8645
8646 /* set load_ce_ram if preamble presented */
8647 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8648 dw2 |= 0x10000000;
8649 } else {
8650 /* still load_ce_ram if this is the first time preamble presented
8651 * although there is no context switch happens.
8652 */
8653 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8654 dw2 |= 0x10000000;
8655 }
8656
8657 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8658 amdgpu_ring_write(ring, dw2);
8659 amdgpu_ring_write(ring, 0);
8660 }
8661
gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring * ring,uint64_t addr)8662 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
8663 uint64_t addr)
8664 {
8665 unsigned int ret;
8666
8667 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8668 amdgpu_ring_write(ring, lower_32_bits(addr));
8669 amdgpu_ring_write(ring, upper_32_bits(addr));
8670 /* discard following DWs if *cond_exec_gpu_addr==0 */
8671 amdgpu_ring_write(ring, 0);
8672 ret = ring->wptr & ring->buf_mask;
8673 /* patch dummy value later */
8674 amdgpu_ring_write(ring, 0);
8675
8676 return ret;
8677 }
8678
gfx_v10_0_ring_preempt_ib(struct amdgpu_ring * ring)8679 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8680 {
8681 int i, r = 0;
8682 struct amdgpu_device *adev = ring->adev;
8683 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
8684 struct amdgpu_ring *kiq_ring = &kiq->ring;
8685 unsigned long flags;
8686
8687 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8688 return -EINVAL;
8689
8690 spin_lock_irqsave(&kiq->ring_lock, flags);
8691
8692 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8693 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8694 return -ENOMEM;
8695 }
8696
8697 /* assert preemption condition */
8698 amdgpu_ring_set_preempt_cond_exec(ring, false);
8699
8700 /* assert IB preemption, emit the trailing fence */
8701 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8702 ring->trail_fence_gpu_addr,
8703 ++ring->trail_seq);
8704 amdgpu_ring_commit(kiq_ring);
8705
8706 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8707
8708 /* poll the trailing fence */
8709 for (i = 0; i < adev->usec_timeout; i++) {
8710 if (ring->trail_seq ==
8711 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8712 break;
8713 udelay(1);
8714 }
8715
8716 if (i >= adev->usec_timeout) {
8717 r = -EINVAL;
8718 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8719 }
8720
8721 /* deassert preemption condition */
8722 amdgpu_ring_set_preempt_cond_exec(ring, true);
8723 return r;
8724 }
8725
gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring * ring,bool resume)8726 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8727 {
8728 struct amdgpu_device *adev = ring->adev;
8729 struct v10_ce_ib_state ce_payload = {0};
8730 uint64_t offset, ce_payload_gpu_addr;
8731 void *ce_payload_cpu_addr;
8732 int cnt;
8733
8734 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8735
8736 if (ring->is_mes_queue) {
8737 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8738 gfx[0].gfx_meta_data) +
8739 offsetof(struct v10_gfx_meta_data, ce_payload);
8740 ce_payload_gpu_addr =
8741 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8742 ce_payload_cpu_addr =
8743 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
8744 } else {
8745 offset = offsetof(struct v10_gfx_meta_data, ce_payload);
8746 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8747 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8748 }
8749
8750 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8751 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8752 WRITE_DATA_DST_SEL(8) |
8753 WR_CONFIRM) |
8754 WRITE_DATA_CACHE_POLICY(0));
8755 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
8756 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
8757
8758 if (resume)
8759 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
8760 sizeof(ce_payload) >> 2);
8761 else
8762 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8763 sizeof(ce_payload) >> 2);
8764 }
8765
gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring * ring,bool resume)8766 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8767 {
8768 struct amdgpu_device *adev = ring->adev;
8769 struct v10_de_ib_state de_payload = {0};
8770 uint64_t offset, gds_addr, de_payload_gpu_addr;
8771 void *de_payload_cpu_addr;
8772 int cnt;
8773
8774 if (ring->is_mes_queue) {
8775 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8776 gfx[0].gfx_meta_data) +
8777 offsetof(struct v10_gfx_meta_data, de_payload);
8778 de_payload_gpu_addr =
8779 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8780 de_payload_cpu_addr =
8781 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
8782
8783 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8784 gfx[0].gds_backup) +
8785 offsetof(struct v10_gfx_meta_data, de_payload);
8786 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8787 } else {
8788 offset = offsetof(struct v10_gfx_meta_data, de_payload);
8789 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8790 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8791
8792 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
8793 AMDGPU_CSA_SIZE - adev->gds.gds_size,
8794 PAGE_SIZE);
8795 }
8796
8797 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8798 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8799
8800 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8801 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8802 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8803 WRITE_DATA_DST_SEL(8) |
8804 WR_CONFIRM) |
8805 WRITE_DATA_CACHE_POLICY(0));
8806 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
8807 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
8808
8809 if (resume)
8810 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
8811 sizeof(de_payload) >> 2);
8812 else
8813 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8814 sizeof(de_payload) >> 2);
8815 }
8816
gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring * ring,bool start,bool secure)8817 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8818 bool secure)
8819 {
8820 uint32_t v = secure ? FRAME_TMZ : 0;
8821
8822 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8823 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8824 }
8825
gfx_v10_0_ring_emit_rreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t reg_val_offs)8826 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8827 uint32_t reg_val_offs)
8828 {
8829 struct amdgpu_device *adev = ring->adev;
8830
8831 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8832 amdgpu_ring_write(ring, 0 | /* src: register*/
8833 (5 << 8) | /* dst: memory */
8834 (1 << 20)); /* write confirm */
8835 amdgpu_ring_write(ring, reg);
8836 amdgpu_ring_write(ring, 0);
8837 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8838 reg_val_offs * 4));
8839 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8840 reg_val_offs * 4));
8841 }
8842
gfx_v10_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)8843 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8844 uint32_t val)
8845 {
8846 uint32_t cmd = 0;
8847
8848 switch (ring->funcs->type) {
8849 case AMDGPU_RING_TYPE_GFX:
8850 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8851 break;
8852 case AMDGPU_RING_TYPE_KIQ:
8853 cmd = (1 << 16); /* no inc addr */
8854 break;
8855 default:
8856 cmd = WR_CONFIRM;
8857 break;
8858 }
8859 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8860 amdgpu_ring_write(ring, cmd);
8861 amdgpu_ring_write(ring, reg);
8862 amdgpu_ring_write(ring, 0);
8863 amdgpu_ring_write(ring, val);
8864 }
8865
gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)8866 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8867 uint32_t val, uint32_t mask)
8868 {
8869 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8870 }
8871
gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)8872 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8873 uint32_t reg0, uint32_t reg1,
8874 uint32_t ref, uint32_t mask)
8875 {
8876 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8877 struct amdgpu_device *adev = ring->adev;
8878 bool fw_version_ok = false;
8879
8880 fw_version_ok = adev->gfx.cp_fw_write_wait;
8881
8882 if (fw_version_ok)
8883 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8884 ref, mask, 0x20);
8885 else
8886 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8887 ref, mask);
8888 }
8889
gfx_v10_0_ring_soft_recovery(struct amdgpu_ring * ring,unsigned int vmid)8890 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8891 unsigned int vmid)
8892 {
8893 struct amdgpu_device *adev = ring->adev;
8894 uint32_t value = 0;
8895
8896 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8897 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8898 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8899 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8900 WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8901 }
8902
8903 static void
gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device * adev,uint32_t me,uint32_t pipe,enum amdgpu_interrupt_state state)8904 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8905 uint32_t me, uint32_t pipe,
8906 enum amdgpu_interrupt_state state)
8907 {
8908 uint32_t cp_int_cntl, cp_int_cntl_reg;
8909
8910 if (!me) {
8911 switch (pipe) {
8912 case 0:
8913 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8914 break;
8915 case 1:
8916 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8917 break;
8918 default:
8919 DRM_DEBUG("invalid pipe %d\n", pipe);
8920 return;
8921 }
8922 } else {
8923 DRM_DEBUG("invalid me %d\n", me);
8924 return;
8925 }
8926
8927 switch (state) {
8928 case AMDGPU_IRQ_STATE_DISABLE:
8929 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8930 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8931 TIME_STAMP_INT_ENABLE, 0);
8932 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8933 break;
8934 case AMDGPU_IRQ_STATE_ENABLE:
8935 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8936 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8937 TIME_STAMP_INT_ENABLE, 1);
8938 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8939 break;
8940 default:
8941 break;
8942 }
8943 }
8944
gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state)8945 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8946 int me, int pipe,
8947 enum amdgpu_interrupt_state state)
8948 {
8949 u32 mec_int_cntl, mec_int_cntl_reg;
8950
8951 /*
8952 * amdgpu controls only the first MEC. That's why this function only
8953 * handles the setting of interrupts for this specific MEC. All other
8954 * pipes' interrupts are set by amdkfd.
8955 */
8956
8957 if (me == 1) {
8958 switch (pipe) {
8959 case 0:
8960 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8961 break;
8962 case 1:
8963 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8964 break;
8965 case 2:
8966 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8967 break;
8968 case 3:
8969 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8970 break;
8971 default:
8972 DRM_DEBUG("invalid pipe %d\n", pipe);
8973 return;
8974 }
8975 } else {
8976 DRM_DEBUG("invalid me %d\n", me);
8977 return;
8978 }
8979
8980 switch (state) {
8981 case AMDGPU_IRQ_STATE_DISABLE:
8982 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8983 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8984 TIME_STAMP_INT_ENABLE, 0);
8985 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8986 break;
8987 case AMDGPU_IRQ_STATE_ENABLE:
8988 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8989 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8990 TIME_STAMP_INT_ENABLE, 1);
8991 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8992 break;
8993 default:
8994 break;
8995 }
8996 }
8997
gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)8998 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8999 struct amdgpu_irq_src *src,
9000 unsigned int type,
9001 enum amdgpu_interrupt_state state)
9002 {
9003 switch (type) {
9004 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9005 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9006 break;
9007 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9008 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9009 break;
9010 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9011 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9012 break;
9013 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9014 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9015 break;
9016 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9017 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9018 break;
9019 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9020 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9021 break;
9022 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9023 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9024 break;
9025 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9026 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9027 break;
9028 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9029 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9030 break;
9031 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9032 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9033 break;
9034 default:
9035 break;
9036 }
9037 return 0;
9038 }
9039
gfx_v10_0_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9040 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9041 struct amdgpu_irq_src *source,
9042 struct amdgpu_iv_entry *entry)
9043 {
9044 int i;
9045 u8 me_id, pipe_id, queue_id;
9046 struct amdgpu_ring *ring;
9047 uint32_t mes_queue_id = entry->src_data[0];
9048
9049 DRM_DEBUG("IH: CP EOP\n");
9050
9051 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
9052 struct amdgpu_mes_queue *queue;
9053
9054 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
9055
9056 spin_lock(&adev->mes.queue_id_lock);
9057 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
9058 if (queue) {
9059 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
9060 amdgpu_fence_process(queue->ring);
9061 }
9062 spin_unlock(&adev->mes.queue_id_lock);
9063 } else {
9064 me_id = (entry->ring_id & 0x0c) >> 2;
9065 pipe_id = (entry->ring_id & 0x03) >> 0;
9066 queue_id = (entry->ring_id & 0x70) >> 4;
9067
9068 switch (me_id) {
9069 case 0:
9070 if (pipe_id == 0)
9071 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9072 else
9073 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9074 break;
9075 case 1:
9076 case 2:
9077 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9078 ring = &adev->gfx.compute_ring[i];
9079 /* Per-queue interrupt is supported for MEC starting from VI.
9080 * The interrupt can only be enabled/disabled per pipe instead
9081 * of per queue.
9082 */
9083 if ((ring->me == me_id) &&
9084 (ring->pipe == pipe_id) &&
9085 (ring->queue == queue_id))
9086 amdgpu_fence_process(ring);
9087 }
9088 break;
9089 }
9090 }
9091
9092 return 0;
9093 }
9094
gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)9095 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9096 struct amdgpu_irq_src *source,
9097 unsigned int type,
9098 enum amdgpu_interrupt_state state)
9099 {
9100 switch (state) {
9101 case AMDGPU_IRQ_STATE_DISABLE:
9102 case AMDGPU_IRQ_STATE_ENABLE:
9103 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9104 PRIV_REG_INT_ENABLE,
9105 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9106 break;
9107 default:
9108 break;
9109 }
9110
9111 return 0;
9112 }
9113
gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)9114 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9115 struct amdgpu_irq_src *source,
9116 unsigned int type,
9117 enum amdgpu_interrupt_state state)
9118 {
9119 switch (state) {
9120 case AMDGPU_IRQ_STATE_DISABLE:
9121 case AMDGPU_IRQ_STATE_ENABLE:
9122 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9123 PRIV_INSTR_INT_ENABLE,
9124 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9125 break;
9126 default:
9127 break;
9128 }
9129
9130 return 0;
9131 }
9132
gfx_v10_0_handle_priv_fault(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)9133 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9134 struct amdgpu_iv_entry *entry)
9135 {
9136 u8 me_id, pipe_id, queue_id;
9137 struct amdgpu_ring *ring;
9138 int i;
9139
9140 me_id = (entry->ring_id & 0x0c) >> 2;
9141 pipe_id = (entry->ring_id & 0x03) >> 0;
9142 queue_id = (entry->ring_id & 0x70) >> 4;
9143
9144 switch (me_id) {
9145 case 0:
9146 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9147 ring = &adev->gfx.gfx_ring[i];
9148 /* we only enabled 1 gfx queue per pipe for now */
9149 if (ring->me == me_id && ring->pipe == pipe_id)
9150 drm_sched_fault(&ring->sched);
9151 }
9152 break;
9153 case 1:
9154 case 2:
9155 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9156 ring = &adev->gfx.compute_ring[i];
9157 if (ring->me == me_id && ring->pipe == pipe_id &&
9158 ring->queue == queue_id)
9159 drm_sched_fault(&ring->sched);
9160 }
9161 break;
9162 default:
9163 BUG();
9164 }
9165 }
9166
gfx_v10_0_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9167 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9168 struct amdgpu_irq_src *source,
9169 struct amdgpu_iv_entry *entry)
9170 {
9171 DRM_ERROR("Illegal register access in command stream\n");
9172 gfx_v10_0_handle_priv_fault(adev, entry);
9173 return 0;
9174 }
9175
gfx_v10_0_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9176 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9177 struct amdgpu_irq_src *source,
9178 struct amdgpu_iv_entry *entry)
9179 {
9180 DRM_ERROR("Illegal instruction in command stream\n");
9181 gfx_v10_0_handle_priv_fault(adev, entry);
9182 return 0;
9183 }
9184
gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)9185 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9186 struct amdgpu_irq_src *src,
9187 unsigned int type,
9188 enum amdgpu_interrupt_state state)
9189 {
9190 uint32_t tmp, target;
9191 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9192
9193 if (ring->me == 1)
9194 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9195 else
9196 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9197 target += ring->pipe;
9198
9199 switch (type) {
9200 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9201 if (state == AMDGPU_IRQ_STATE_DISABLE) {
9202 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9203 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9204 GENERIC2_INT_ENABLE, 0);
9205 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9206
9207 tmp = RREG32_SOC15_IP(GC, target);
9208 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9209 GENERIC2_INT_ENABLE, 0);
9210 WREG32_SOC15_IP(GC, target, tmp);
9211 } else {
9212 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9213 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9214 GENERIC2_INT_ENABLE, 1);
9215 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9216
9217 tmp = RREG32_SOC15_IP(GC, target);
9218 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9219 GENERIC2_INT_ENABLE, 1);
9220 WREG32_SOC15_IP(GC, target, tmp);
9221 }
9222 break;
9223 default:
9224 BUG(); /* kiq only support GENERIC2_INT now */
9225 break;
9226 }
9227 return 0;
9228 }
9229
gfx_v10_0_kiq_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9230 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9231 struct amdgpu_irq_src *source,
9232 struct amdgpu_iv_entry *entry)
9233 {
9234 u8 me_id, pipe_id, queue_id;
9235 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9236
9237 me_id = (entry->ring_id & 0x0c) >> 2;
9238 pipe_id = (entry->ring_id & 0x03) >> 0;
9239 queue_id = (entry->ring_id & 0x70) >> 4;
9240 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9241 me_id, pipe_id, queue_id);
9242
9243 amdgpu_fence_process(ring);
9244 return 0;
9245 }
9246
gfx_v10_0_emit_mem_sync(struct amdgpu_ring * ring)9247 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9248 {
9249 const unsigned int gcr_cntl =
9250 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9251 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9252 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9253 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9254 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9255 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9256 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9257 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9258
9259 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9260 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9261 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9262 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
9263 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
9264 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9265 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
9266 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9267 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9268 }
9269
gfx_v10_ip_print(void * handle,struct drm_printer * p)9270 static void gfx_v10_ip_print(void *handle, struct drm_printer *p)
9271 {
9272 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
9273 uint32_t i;
9274 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
9275
9276 if (!adev->gfx.ip_dump)
9277 return;
9278
9279 for (i = 0; i < reg_count; i++)
9280 drm_printf(p, "%-50s \t 0x%08x\n",
9281 gc_reg_list_10_1[i].reg_name,
9282 adev->gfx.ip_dump[i]);
9283 }
9284
gfx_v10_ip_dump(void * handle)9285 static void gfx_v10_ip_dump(void *handle)
9286 {
9287 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
9288 uint32_t i;
9289 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
9290
9291 if (!adev->gfx.ip_dump)
9292 return;
9293
9294 amdgpu_gfx_off_ctrl(adev, false);
9295 for (i = 0; i < reg_count; i++)
9296 adev->gfx.ip_dump[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
9297 amdgpu_gfx_off_ctrl(adev, true);
9298 }
9299
9300 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9301 .name = "gfx_v10_0",
9302 .early_init = gfx_v10_0_early_init,
9303 .late_init = gfx_v10_0_late_init,
9304 .sw_init = gfx_v10_0_sw_init,
9305 .sw_fini = gfx_v10_0_sw_fini,
9306 .hw_init = gfx_v10_0_hw_init,
9307 .hw_fini = gfx_v10_0_hw_fini,
9308 .suspend = gfx_v10_0_suspend,
9309 .resume = gfx_v10_0_resume,
9310 .is_idle = gfx_v10_0_is_idle,
9311 .wait_for_idle = gfx_v10_0_wait_for_idle,
9312 .soft_reset = gfx_v10_0_soft_reset,
9313 .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9314 .set_powergating_state = gfx_v10_0_set_powergating_state,
9315 .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9316 .dump_ip_state = gfx_v10_ip_dump,
9317 .print_ip_state = gfx_v10_ip_print,
9318 };
9319
9320 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9321 .type = AMDGPU_RING_TYPE_GFX,
9322 .align_mask = 0xff,
9323 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9324 .support_64bit_ptrs = true,
9325 .secure_submission_supported = true,
9326 .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9327 .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9328 .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9329 .emit_frame_size = /* totally 242 maximum if 16 IBs */
9330 5 + /* COND_EXEC */
9331 7 + /* PIPELINE_SYNC */
9332 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9333 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9334 4 + /* VM_FLUSH */
9335 8 + /* FENCE for VM_FLUSH */
9336 20 + /* GDS switch */
9337 4 + /* double SWITCH_BUFFER,
9338 * the first COND_EXEC jump to the place
9339 * just prior to this double SWITCH_BUFFER
9340 */
9341 5 + /* COND_EXEC */
9342 7 + /* HDP_flush */
9343 4 + /* VGT_flush */
9344 14 + /* CE_META */
9345 31 + /* DE_META */
9346 3 + /* CNTX_CTRL */
9347 5 + /* HDP_INVL */
9348 8 + 8 + /* FENCE x2 */
9349 2 + /* SWITCH_BUFFER */
9350 8, /* gfx_v10_0_emit_mem_sync */
9351 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9352 .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9353 .emit_fence = gfx_v10_0_ring_emit_fence,
9354 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9355 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9356 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9357 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9358 .test_ring = gfx_v10_0_ring_test_ring,
9359 .test_ib = gfx_v10_0_ring_test_ib,
9360 .insert_nop = amdgpu_ring_insert_nop,
9361 .pad_ib = amdgpu_ring_generic_pad_ib,
9362 .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9363 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9364 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9365 .preempt_ib = gfx_v10_0_ring_preempt_ib,
9366 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9367 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9368 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9369 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9370 .soft_recovery = gfx_v10_0_ring_soft_recovery,
9371 .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9372 };
9373
9374 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9375 .type = AMDGPU_RING_TYPE_COMPUTE,
9376 .align_mask = 0xff,
9377 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9378 .support_64bit_ptrs = true,
9379 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9380 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9381 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9382 .emit_frame_size =
9383 20 + /* gfx_v10_0_ring_emit_gds_switch */
9384 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9385 5 + /* hdp invalidate */
9386 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9387 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9388 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9389 2 + /* gfx_v10_0_ring_emit_vm_flush */
9390 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9391 8, /* gfx_v10_0_emit_mem_sync */
9392 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9393 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9394 .emit_fence = gfx_v10_0_ring_emit_fence,
9395 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9396 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9397 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9398 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9399 .test_ring = gfx_v10_0_ring_test_ring,
9400 .test_ib = gfx_v10_0_ring_test_ib,
9401 .insert_nop = amdgpu_ring_insert_nop,
9402 .pad_ib = amdgpu_ring_generic_pad_ib,
9403 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9404 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9405 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9406 .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9407 };
9408
9409 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9410 .type = AMDGPU_RING_TYPE_KIQ,
9411 .align_mask = 0xff,
9412 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9413 .support_64bit_ptrs = true,
9414 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9415 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9416 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9417 .emit_frame_size =
9418 20 + /* gfx_v10_0_ring_emit_gds_switch */
9419 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9420 5 + /*hdp invalidate */
9421 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9422 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9423 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9424 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9425 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9426 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9427 .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9428 .test_ring = gfx_v10_0_ring_test_ring,
9429 .test_ib = gfx_v10_0_ring_test_ib,
9430 .insert_nop = amdgpu_ring_insert_nop,
9431 .pad_ib = amdgpu_ring_generic_pad_ib,
9432 .emit_rreg = gfx_v10_0_ring_emit_rreg,
9433 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9434 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9435 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9436 };
9437
gfx_v10_0_set_ring_funcs(struct amdgpu_device * adev)9438 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9439 {
9440 int i;
9441
9442 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9443
9444 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9445 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9446
9447 for (i = 0; i < adev->gfx.num_compute_rings; i++)
9448 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9449 }
9450
9451 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9452 .set = gfx_v10_0_set_eop_interrupt_state,
9453 .process = gfx_v10_0_eop_irq,
9454 };
9455
9456 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9457 .set = gfx_v10_0_set_priv_reg_fault_state,
9458 .process = gfx_v10_0_priv_reg_irq,
9459 };
9460
9461 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9462 .set = gfx_v10_0_set_priv_inst_fault_state,
9463 .process = gfx_v10_0_priv_inst_irq,
9464 };
9465
9466 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9467 .set = gfx_v10_0_kiq_set_interrupt_state,
9468 .process = gfx_v10_0_kiq_irq,
9469 };
9470
gfx_v10_0_set_irq_funcs(struct amdgpu_device * adev)9471 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9472 {
9473 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9474 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9475
9476 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9477 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9478
9479 adev->gfx.priv_reg_irq.num_types = 1;
9480 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9481
9482 adev->gfx.priv_inst_irq.num_types = 1;
9483 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9484 }
9485
gfx_v10_0_set_rlc_funcs(struct amdgpu_device * adev)9486 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9487 {
9488 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
9489 case IP_VERSION(10, 1, 10):
9490 case IP_VERSION(10, 1, 1):
9491 case IP_VERSION(10, 1, 3):
9492 case IP_VERSION(10, 1, 4):
9493 case IP_VERSION(10, 3, 2):
9494 case IP_VERSION(10, 3, 1):
9495 case IP_VERSION(10, 3, 4):
9496 case IP_VERSION(10, 3, 5):
9497 case IP_VERSION(10, 3, 6):
9498 case IP_VERSION(10, 3, 3):
9499 case IP_VERSION(10, 3, 7):
9500 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9501 break;
9502 case IP_VERSION(10, 1, 2):
9503 case IP_VERSION(10, 3, 0):
9504 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9505 break;
9506 default:
9507 break;
9508 }
9509 }
9510
gfx_v10_0_set_gds_init(struct amdgpu_device * adev)9511 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9512 {
9513 unsigned int total_cu = adev->gfx.config.max_cu_per_sh *
9514 adev->gfx.config.max_sh_per_se *
9515 adev->gfx.config.max_shader_engines;
9516
9517 adev->gds.gds_size = 0x10000;
9518 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9519 adev->gds.gws_size = 64;
9520 adev->gds.oa_size = 16;
9521 }
9522
gfx_v10_0_set_mqd_funcs(struct amdgpu_device * adev)9523 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
9524 {
9525 /* set gfx eng mqd */
9526 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
9527 sizeof(struct v10_gfx_mqd);
9528 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
9529 gfx_v10_0_gfx_mqd_init;
9530 /* set compute eng mqd */
9531 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
9532 sizeof(struct v10_compute_mqd);
9533 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
9534 gfx_v10_0_compute_mqd_init;
9535 }
9536
gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device * adev,u32 bitmap)9537 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9538 u32 bitmap)
9539 {
9540 u32 data;
9541
9542 if (!bitmap)
9543 return;
9544
9545 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9546 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9547
9548 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9549 }
9550
gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device * adev)9551 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9552 {
9553 u32 disabled_mask =
9554 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9555 u32 efuse_setting = 0;
9556 u32 vbios_setting = 0;
9557
9558 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9559 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9560 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9561
9562 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9563 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9564 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9565
9566 disabled_mask |= efuse_setting | vbios_setting;
9567
9568 return (~disabled_mask);
9569 }
9570
gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device * adev)9571 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9572 {
9573 u32 wgp_idx, wgp_active_bitmap;
9574 u32 cu_bitmap_per_wgp, cu_active_bitmap;
9575
9576 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9577 cu_active_bitmap = 0;
9578
9579 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9580 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9581 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9582 if (wgp_active_bitmap & (1 << wgp_idx))
9583 cu_active_bitmap |= cu_bitmap_per_wgp;
9584 }
9585
9586 return cu_active_bitmap;
9587 }
9588
gfx_v10_0_get_cu_info(struct amdgpu_device * adev,struct amdgpu_cu_info * cu_info)9589 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9590 struct amdgpu_cu_info *cu_info)
9591 {
9592 int i, j, k, counter, active_cu_number = 0;
9593 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9594 unsigned int disable_masks[4 * 2];
9595
9596 if (!adev || !cu_info)
9597 return -EINVAL;
9598
9599 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9600
9601 mutex_lock(&adev->grbm_idx_mutex);
9602 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9603 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9604 bitmap = i * adev->gfx.config.max_sh_per_se + j;
9605 if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
9606 IP_VERSION(10, 3, 0)) ||
9607 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
9608 IP_VERSION(10, 3, 3)) ||
9609 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
9610 IP_VERSION(10, 3, 6)) ||
9611 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
9612 IP_VERSION(10, 3, 7))) &&
9613 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9614 continue;
9615 mask = 1;
9616 ao_bitmap = 0;
9617 counter = 0;
9618 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
9619 if (i < 4 && j < 2)
9620 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9621 adev, disable_masks[i * 2 + j]);
9622 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9623 cu_info->bitmap[0][i][j] = bitmap;
9624
9625 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9626 if (bitmap & mask) {
9627 if (counter < adev->gfx.config.max_cu_per_sh)
9628 ao_bitmap |= mask;
9629 counter++;
9630 }
9631 mask <<= 1;
9632 }
9633 active_cu_number += counter;
9634 if (i < 2 && j < 2)
9635 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9636 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9637 }
9638 }
9639 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
9640 mutex_unlock(&adev->grbm_idx_mutex);
9641
9642 cu_info->number = active_cu_number;
9643 cu_info->ao_cu_mask = ao_cu_mask;
9644 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9645
9646 return 0;
9647 }
9648
gfx_v10_3_get_disabled_sa(struct amdgpu_device * adev)9649 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9650 {
9651 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9652
9653 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9654 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9655 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9656
9657 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9658 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9659 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9660
9661 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9662 adev->gfx.config.max_shader_engines);
9663 disabled_sa = efuse_setting | vbios_setting;
9664 disabled_sa &= max_sa_mask;
9665
9666 return disabled_sa;
9667 }
9668
gfx_v10_3_program_pbb_mode(struct amdgpu_device * adev)9669 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9670 {
9671 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9672 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9673
9674 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9675
9676 max_sa_per_se = adev->gfx.config.max_sh_per_se;
9677 max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9678 max_shader_engines = adev->gfx.config.max_shader_engines;
9679
9680 for (se_index = 0; max_shader_engines > se_index; se_index++) {
9681 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9682 disabled_sa_per_se &= max_sa_per_se_mask;
9683 if (disabled_sa_per_se == max_sa_per_se_mask) {
9684 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9685 break;
9686 }
9687 }
9688 }
9689
gfx_v10_3_set_power_brake_sequence(struct amdgpu_device * adev)9690 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9691 {
9692 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9693 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9694 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9695 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9696
9697 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9698 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9699 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9700 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9701 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9702 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9703
9704 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9705 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9706 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9707 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9708
9709 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9710
9711 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9712 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9713 }
9714
9715 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = {
9716 .type = AMD_IP_BLOCK_TYPE_GFX,
9717 .major = 10,
9718 .minor = 0,
9719 .rev = 0,
9720 .funcs = &gfx_v10_0_ip_funcs,
9721 };
9722