Searched refs:mmSDMA0_GFX_MINOR_PTR_UPDATE (Results 1 – 9 of 9) sorted by relevance
| /linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_offset.h | 268 #define mmSDMA0_GFX_MINOR_PTR_UPDATE … macro
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| H A D | sdma0_4_0_offset.h | 272 #define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 macro
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| H A D | sdma0_4_2_2_offset.h | 272 #define mmSDMA0_GFX_MINOR_PTR_UPDATE … macro
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| H A D | sdma0_4_2_offset.h | 268 #define mmSDMA0_GFX_MINOR_PTR_UPDATE … macro
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v5_2.c | 536 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); in sdma_v5_2_gfx_resume()
565 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); in sdma_v5_2_gfx_resume()
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| H A D | sdma_v5_0.c | 731 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); in sdma_v5_0_gfx_resume()
762 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); in sdma_v5_0_gfx_resume()
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| H A D | sdma_v4_0.c | 1075 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); in sdma_v4_0_gfx_resume()
1091 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); in sdma_v4_0_gfx_resume()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 265 #define mmSDMA0_GFX_MINOR_PTR_UPDATE … macro
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| H A D | gc_10_3_0_offset.h | 254 #define mmSDMA0_GFX_MINOR_PTR_UPDATE … macro
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