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Searched refs:mmSDMA0_RLC0_DOORBELL (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_arcturus.c158 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_arcturus_hqd_sdma_load()
207 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) in kgd_arcturus_hqd_sdma_dump()
270 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0); in kgd_arcturus_hqd_sdma_destroy()
H A Damdgpu_amdkfd_gfx_v7.c267 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load()
308 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) in kgd_hqd_sdma_dump()
486 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0); in kgd_hqd_sdma_destroy()
H A Damdgpu_amdkfd_gfx_v8.c290 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load()
331 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) in kgd_hqd_sdma_dump()
521 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0); in kgd_hqd_sdma_destroy()
H A Damdgpu_amdkfd_gfx_v10_3.c393 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in hqd_sdma_load_v10_3()
442 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) in hqd_sdma_dump_v10_3()
577 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0); in hqd_sdma_destroy_v10_3()
H A Damdgpu_amdkfd_gfx_v10.c407 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load()
456 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) in kgd_hqd_sdma_dump()
653 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0); in kgd_hqd_sdma_destroy()
H A Damdgpu_amdkfd_gfx_v9.c418 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load()
467 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) in kgd_hqd_sdma_dump()
603 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0); in kgd_hqd_sdma_destroy()
/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h326 #define mmSDMA0_RLC0_DOORBELL … macro
H A Dsdma0_4_0_offset.h414 #define mmSDMA0_RLC0_DOORBELL 0x0152 macro
H A Dsdma0_4_2_2_offset.h414 #define mmSDMA0_RLC0_DOORBELL … macro
H A Dsdma0_4_2_offset.h410 #define mmSDMA0_RLC0_DOORBELL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h232 #define mmSDMA0_RLC0_DOORBELL 0x3512 macro
H A Doss_3_0_1_d.h271 #define mmSDMA0_RLC0_DOORBELL 0x3512 macro
H A Doss_2_0_d.h286 #define mmSDMA0_RLC0_DOORBELL 0x3512 macro
H A Doss_3_0_d.h393 #define mmSDMA0_RLC0_DOORBELL 0x3512 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h406 #define mmSDMA0_RLC0_DOORBELL … macro
H A Dgc_10_3_0_offset.h404 #define mmSDMA0_RLC0_DOORBELL … macro