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Searched refs:mmSDMA0_UTCL1_TIMEOUT (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h154 #define mmSDMA0_UTCL1_TIMEOUT … macro
H A Dsdma0_4_0_offset.h156 #define mmSDMA0_UTCL1_TIMEOUT 0x0047 macro
H A Dsdma0_4_2_2_offset.h156 #define mmSDMA0_UTCL1_TIMEOUT … macro
H A Dsdma0_4_2_offset.h156 #define mmSDMA0_UTCL1_TIMEOUT … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_0.c120 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
130 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
183 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
233 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
267 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
984 WREG32_SDMA(i, mmSDMA0_UTCL1_TIMEOUT, 0x00800080); in sdma_v4_0_ctx_switch_enable()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h131 #define mmSDMA0_UTCL1_TIMEOUT … macro
H A Dgc_10_3_0_offset.h130 #define mmSDMA0_UTCL1_TIMEOUT … macro