| /linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_0_d.h | 62 #define mmUVD_PGFSM_CONFIG 0x38F8 macro
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| H A D | uvd_4_2_d.h | 88 #define mmUVD_PGFSM_CONFIG 0x38f8 macro
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| H A D | uvd_3_1_d.h | 90 #define mmUVD_PGFSM_CONFIG 0x38f8 macro
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| H A D | uvd_5_0_d.h | 100 #define mmUVD_PGFSM_CONFIG 0x38c0 macro
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| H A D | uvd_6_0_d.h | 116 #define mmUVD_PGFSM_CONFIG 0x38c0 macro
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | jpeg_v3_0.c | 268 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); in jpeg_v3_0_disable_static_power_gating()
303 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); in jpeg_v3_0_enable_static_power_gating()
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| H A D | uvd_v4_2.c | 735 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | in uvd_v4_2_set_powergating_state()
746 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | in uvd_v4_2_set_powergating_state()
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| H A D | vcn_v1_0.c | 76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),
754 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_1_0_disable_static_power_gating()
768 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_1_0_disable_static_power_gating()
806 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_1_0_enable_static_power_gating()
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| H A D | vcn_v2_0.c | 84 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),
767 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_v2_0_disable_static_power_gating()
781 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_v2_0_disable_static_power_gating()
823 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_v2_0_enable_static_power_gating()
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| H A D | vcn_v3_0.c | 91 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),
659 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); in vcn_v3_0_disable_static_power_gating()
677 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); in vcn_v3_0_disable_static_power_gating()
715 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); in vcn_v3_0_enable_static_power_gating()
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| H A D | vcn_v2_5.c | 87 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 28 #define mmUVD_PGFSM_CONFIG … macro
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| H A D | vcn_2_5_offset.h | 395 #define mmUVD_PGFSM_CONFIG … macro
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| H A D | vcn_2_0_0_offset.h | 380 #define mmUVD_PGFSM_CONFIG … macro
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| H A D | vcn_3_0_0_offset.h | 663 #define mmUVD_PGFSM_CONFIG … macro
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