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Searched refs:mmUVD_POWER_STATUS (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v1_0.c49 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
774 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_1_0_disable_static_power_gating()
779 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_1_0_disable_static_power_gating()
788 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_1_0_enable_static_power_gating()
791 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_1_0_enable_static_power_gating()
1016 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); in vcn_v1_0_start_dpg_mode()
1019 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); in vcn_v1_0_start_dpg_mode()
1212 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_stop_dpg_mode()
1229 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_stop_dpg_mode()
1304 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_pause_dpg_mode()
[all …]
H A Dvcn_v2_0.c57 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
788 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_v2_0_disable_static_power_gating()
794 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_v2_0_disable_static_power_gating()
806 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_v2_0_enable_static_power_gating()
809 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_v2_0_enable_static_power_gating()
848 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); in vcn_v2_0_start_dpg_mode()
851 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); in vcn_v2_0_start_dpg_mode()
940 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), in vcn_v2_0_start_dpg_mode()
1154 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, in vcn_v2_0_stop_dpg_mode()
1167 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, in vcn_v2_0_stop_dpg_mode()
[all …]
H A Dvcn_v2_5.c59 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
60 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
877 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); in vcn_v2_5_start_dpg_mode()
880 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); in vcn_v2_5_start_dpg_mode()
976 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
1029 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, in vcn_v2_5_start()
1405 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1418 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1485 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), in vcn_v2_5_stop()
1556 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, in vcn_v2_5_pause_dpg_mode()
[all …]
H A Dvcn_v3_0.c64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
681 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); in vcn_v3_0_disable_static_power_gating()
687 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); in vcn_v3_0_disable_static_power_gating()
696 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); in vcn_v3_0_enable_static_power_gating()
699 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); in vcn_v3_0_enable_static_power_gating()
997 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); in vcn_v3_0_start_dpg_mode()
1000 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); in vcn_v3_0_start_dpg_mode()
1098 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v3_0_start_dpg_mode()
1545 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
1558 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
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H A Duvd_v5_0.c329 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); in uvd_v5_0_start()
H A Duvd_v6_0.c734 WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); in uvd_v6_0_start()
1488 WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); in uvd_v6_0_set_powergating_state()
H A Duvd_v7_0.c965 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0, in uvd_v7_0_start()
1767 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h65 #define mmUVD_POWER_STATUS 0x38FC macro
H A Duvd_4_2_d.h91 #define mmUVD_POWER_STATUS 0x38fc macro
H A Duvd_3_1_d.h93 #define mmUVD_POWER_STATUS 0x38fc macro
H A Duvd_5_0_d.h103 #define mmUVD_POWER_STATUS 0x38c4 macro
H A Duvd_6_0_d.h119 #define mmUVD_POWER_STATUS 0x38c4 macro
H A Duvd_7_0_offset.h28 #define mmUVD_POWER_STATUS … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h32 #define mmUVD_POWER_STATUS … macro
H A Dvcn_2_5_offset.h399 #define mmUVD_POWER_STATUS … macro
H A Dvcn_2_0_0_offset.h384 #define mmUVD_POWER_STATUS … macro
H A Dvcn_3_0_0_offset.h667 #define mmUVD_POWER_STATUS … macro