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Searched refs:mmVCE_RB_WPTR (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_1_0_d.h46 #define mmVCE_RB_WPTR 0x8064 macro
H A Dvce_2_0_d.h45 #define mmVCE_RB_WPTR 0x8064 macro
H A Dvce_3_0_d.h45 #define mmVCE_RB_WPTR 0x8064 macro
H A Dvce_4_0_offset.h88 #define mmVCE_RB_WPTR … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v2_0.c77 return RREG32(mmVCE_RB_WPTR); in vce_v2_0_ring_get_wptr()
94 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v2_0_ring_set_wptr()
245 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v2_0_start()
H A Dvce_v3_0.c122 v = RREG32(mmVCE_RB_WPTR); in vce_v3_0_ring_get_wptr()
153 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
282 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_start()
H A Dvce_v4_0.c89 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR)); in vce_v4_0_ring_get_wptr()
115 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), in vce_v4_0_ring_set_wptr()
344 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start()