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Searched refs:mmio_base (Results 1 – 25 of 162) sorted by relevance

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/linux/drivers/input/keyboard/
H A Dimx_keypad.c49 void __iomem *mmio_base; member
94 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
96 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
98 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
100 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
104 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
106 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
135 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
137 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
448 if (IS_ERR(keypad->mmio_base)) in imx_keypad_probe()
[all …]
/linux/drivers/pwm/
H A Dpwm-tiecap.c36 void __iomem *mmio_base; member
74 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_config()
79 writew(value, pc->mmio_base + ECCTL2); in ecap_pwm_config()
96 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_config()
99 writew(value, pc->mmio_base + ECCTL2); in ecap_pwm_config()
115 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_set_polarity()
124 writew(value, pc->mmio_base + ECCTL2); in ecap_pwm_set_polarity()
143 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_enable()
145 writew(value, pc->mmio_base + ECCTL2); in ecap_pwm_enable()
251 if (IS_ERR(pc->mmio_base)) in ecap_pwm_probe()
[all …]
H A Dpwm-tiehrpwm.c109 void __iomem *mmio_base; member
286 ehrpwm_write(pc->mmio_base, TBPRD, period_cycles); in ehrpwm_pwm_config()
299 ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles); in ehrpwm_pwm_config()
481 if (IS_ERR(pc->mmio_base)) in ehrpwm_pwm_probe()
482 return PTR_ERR(pc->mmio_base); in ehrpwm_pwm_probe()
530 pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL); in ehrpwm_pwm_save_context()
531 pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD); in ehrpwm_pwm_save_context()
532 pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA); in ehrpwm_pwm_save_context()
533 pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB); in ehrpwm_pwm_save_context()
547 ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa); in ehrpwm_pwm_restore_context()
[all …]
H A Dpwm-imx27.c85 void __iomem *mmio_base; member
135 val = readl(imx->mmio_base + MX3_PWMCR); in pwm_imx27_get_state()
155 val = readl(imx->mmio_base + MX3_PWMPR); in pwm_imx27_get_state()
167 val = readl(imx->mmio_base + MX3_PWMSAR); in pwm_imx27_get_state()
189 cr = readl(imx->mmio_base + MX3_PWMCR); in pwm_imx27_sw_reset()
206 sr = readl(imx->mmio_base + MX3_PWMSR); in pwm_imx27_wait_fifo_slot()
213 sr = readl(imx->mmio_base + MX3_PWMSR); in pwm_imx27_wait_fifo_slot()
287 writel(cr, imx->mmio_base + MX3_PWMCR); in pwm_imx27_apply()
331 if (IS_ERR(imx->mmio_base)) in pwm_imx27_probe()
332 return PTR_ERR(imx->mmio_base); in pwm_imx27_probe()
[all …]
H A Dpwm-imx1.c30 void __iomem *mmio_base; member
87 max = readl(imx->mmio_base + MX1_PWMP); in pwm_imx1_config()
90 writel(max - p, imx->mmio_base + MX1_PWMS); in pwm_imx1_config()
105 value = readl(imx->mmio_base + MX1_PWMC); in pwm_imx1_enable()
107 writel(value, imx->mmio_base + MX1_PWMC); in pwm_imx1_enable()
117 value = readl(imx->mmio_base + MX1_PWMC); in pwm_imx1_disable()
119 writel(value, imx->mmio_base + MX1_PWMC); in pwm_imx1_disable()
181 imx->mmio_base = devm_platform_ioremap_resource(pdev, 0); in pwm_imx1_probe()
182 if (IS_ERR(imx->mmio_base)) in pwm_imx1_probe()
183 return PTR_ERR(imx->mmio_base); in pwm_imx1_probe()
H A Dpwm-pxa.c55 void __iomem *mmio_base; member
95 writel(prescale | PWMCR_SD, pc->mmio_base + offset + PWMCR); in pxa_pwm_config()
96 writel(dc, pc->mmio_base + offset + PWMDCR); in pxa_pwm_config()
97 writel(pv, pc->mmio_base + offset + PWMPCR); in pxa_pwm_config()
187 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); in pwm_probe()
188 if (IS_ERR(pc->mmio_base)) in pwm_probe()
189 return PTR_ERR(pc->mmio_base); in pwm_probe()
H A Dpwm-spear.c53 void __iomem *mmio_base; member
65 return readl_relaxed(chip->mmio_base + (num << 4) + offset); in spear_pwm_readl()
72 writel_relaxed(val, chip->mmio_base + (num << 4) + offset); in spear_pwm_writel()
205 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); in spear_pwm_probe()
206 if (IS_ERR(pc->mmio_base)) in spear_pwm_probe()
207 return PTR_ERR(pc->mmio_base); in spear_pwm_probe()
226 val = readl_relaxed(pc->mmio_base + PWMMCR); in spear_pwm_probe()
228 writel_relaxed(val, pc->mmio_base + PWMMCR); in spear_pwm_probe()
/linux/drivers/edac/
H A Dal_mc_edac.c57 void __iomem *mmio_base; member
95 al_mc->mmio_base + AL_MC_ECC_CLEAR); in handle_ce()
140 al_mc->mmio_base + AL_MC_ECC_CLEAR); in handle_ue()
199 ecccfg0 = readl(mmio_base + AL_MC_ECC_CFG); in get_scrub_mode()
222 void __iomem *mmio_base; in al_mc_edac_probe() local
226 mmio_base = devm_platform_ioremap_resource(pdev, 0); in al_mc_edac_probe()
227 if (IS_ERR(mmio_base)) { in al_mc_edac_probe()
229 PTR_ERR(mmio_base)); in al_mc_edac_probe()
230 return PTR_ERR(mmio_base); in al_mc_edac_probe()
248 al_mc->mmio_base = mmio_base; in al_mc_edac_probe()
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dpio.h72 u16 mmio_base; member
101 u16 mmio_base; member
111 return b43_read16(q->dev, q->mmio_base + offset); in b43_piotx_read16()
116 return b43_read32(q->dev, q->mmio_base + offset); in b43_piotx_read32()
122 b43_write16(q->dev, q->mmio_base + offset, value); in b43_piotx_write16()
128 b43_write32(q->dev, q->mmio_base + offset, value); in b43_piotx_write32()
134 return b43_read16(q->dev, q->mmio_base + offset); in b43_piorx_read16()
139 return b43_read32(q->dev, q->mmio_base + offset); in b43_piorx_read32()
145 b43_write16(q->dev, q->mmio_base + offset, value); in b43_piorx_write16()
151 b43_write32(q->dev, q->mmio_base + offset, value); in b43_piorx_write32()
/linux/drivers/ata/
H A Dsata_sil.c545 tmp = readl(mmio_base + SIL_SYSCFG); in sil_freeze()
547 writel(tmp, mmio_base + SIL_SYSCFG); in sil_freeze()
548 readl(mmio_base + SIL_SYSCFG); /* flush */ in sil_freeze()
578 tmp = readl(mmio_base + SIL_SYSCFG); in sil_thaw()
580 writel(tmp, mmio_base + SIL_SYSCFG); in sil_thaw()
665 mmio_base + sil_port[i].fifo_cfg); in sil_init_controller()
688 tmp = readl(mmio_base + sil_port[2].bmdma); in sil_init_controller()
691 mmio_base + sil_port[2].bmdma); in sil_init_controller()
727 void __iomem *mmio_base; in sil_init_one() local
765 mmio_base = host->iomap[SIL_MMIO_BAR]; in sil_init_one()
[all …]
H A Dpata_pdc2027x.c461 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; in pdc_read_counter() local
521 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); in pdc_adjust_pll()
560 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL); in pdc_adjust_pll()
561 ioread16(mmio_base + PDC_PLL_CTL); /* flush */ in pdc_adjust_pll()
570 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); in pdc_adjust_pll()
592 scr = ioread32(mmio_base + PDC_SYS_CTL); in pdc_detect_pll_input_clock()
595 ioread32(mmio_base + PDC_SYS_CTL); /* flush */ in pdc_detect_pll_input_clock()
609 scr = ioread32(mmio_base + PDC_SYS_CTL); in pdc_detect_pll_input_clock()
612 ioread32(mmio_base + PDC_SYS_CTL); /* flush */ in pdc_detect_pll_input_clock()
690 void __iomem *mmio_base; in pdc2027x_init_one() local
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H A Dsata_qstor.c192 u8 __iomem *mmio_base = qs_mmio_base(ap->host); in qs_freeze() local
200 u8 __iomem *mmio_base = qs_mmio_base(ap->host); in qs_thaw() local
354 u8 __iomem *mmio_base = qs_mmio_base(host); in qs_intr_pkt() local
357 u32 sff0 = readl(mmio_base + QS_HST_SFF); in qs_intr_pkt()
358 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4); in qs_intr_pkt()
460 void __iomem *mmio_base = qs_mmio_base(ap->host); in qs_port_start() local
482 void __iomem *mmio_base = qs_mmio_base(host); in qs_host_stop() local
490 void __iomem *mmio_base = host->iomap[QS_MMIO_BAR]; in qs_host_init() local
498 u8 __iomem *chan = mmio_base + (port_no * 0x4000); in qs_host_init()
506 u8 __iomem *chan = mmio_base + (port_no * 0x4000); in qs_host_init()
[all …]
H A Dpata_sil680.c340 void __iomem *mmio_base; in sil680_init_one() local
380 mmio_base = host->iomap[SIL680_MMIO_BAR]; in sil680_init_one()
381 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00; in sil680_init_one()
382 host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80; in sil680_init_one()
383 host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a; in sil680_init_one()
384 host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a; in sil680_init_one()
386 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08; in sil680_init_one()
387 host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0; in sil680_init_one()
388 host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca; in sil680_init_one()
389 host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca; in sil680_init_one()
H A Dsata_inic162x.c234 void __iomem *mmio_base; member
268 return hpriv->mmio_base + ap->port_no * PORT_SIZE; in inic_port_base()
426 host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT); in inic_interrupt()
762 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL); in init_controller()
763 readw(mmio_base + HOST_CTL); /* flush */ in init_controller()
767 val = readw(mmio_base + HOST_CTL); in init_controller()
777 void __iomem *port_base = mmio_base + i * PORT_SIZE; in init_controller()
784 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL); in init_controller()
785 val = readw(mmio_base + HOST_IRQ_MASK); in init_controller()
787 writew(val, mmio_base + HOST_IRQ_MASK); in init_controller()
[all …]
/linux/drivers/usb/host/
H A Dohci-pxa27x.c120 void __iomem *mmio_base; member
164 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA); in pxa27x_ohci_select_pmm()
165 __raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB); in pxa27x_ohci_select_pmm()
220 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); in pxa27x_setup_hc()
253 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); in pxa27x_setup_hc()
254 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA); in pxa27x_setup_hc()
259 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); in pxa27x_reset_hc()
281 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); in pxa27x_start_hc()
297 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); in pxa27x_start_hc()
319 __raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS); in pxa27x_stop_hc()
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/linux/drivers/thermal/
H A Dthermal_mmio.c12 void __iomem *mmio_base; member
13 u32 (*read_mmio)(void __iomem *mmio_base);
18 static u32 thermal_mmio_readb(void __iomem *mmio_base) in thermal_mmio_readb() argument
20 return readb(mmio_base); in thermal_mmio_readb()
28 t = sensor->read_mmio(sensor->mmio_base) & sensor->mask; in thermal_mmio_get_temperature()
53 sensor->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); in thermal_mmio_probe()
54 if (IS_ERR(sensor->mmio_base)) in thermal_mmio_probe()
55 return PTR_ERR(sensor->mmio_base); in thermal_mmio_probe()
/linux/drivers/clk/mmp/
H A Dclk-audio.c61 void __iomem *mmio_base; member
216 writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL0); in audio_pll_set_rate()
220 writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL1); in audio_pll_set_rate()
257 priv->sspa_mux.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
267 priv->sysclk_div.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
288 priv->sspa0_div.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
301 priv->sspa0_gate.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
310 priv->sspa1_mux.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
319 priv->sspa1_div.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
363 if (IS_ERR(priv->mmio_base)) in mmp2_audio_clk_probe()
[all …]
/linux/drivers/gpu/drm/xe/
H A Dxe_hw_engine.c42 u32 mmio_base; member
52 .mmio_base = RENDER_RING_BASE,
60 .mmio_base = BLT_RING_BASE,
133 .mmio_base = BSD_RING_BASE,
141 .mmio_base = BSD2_RING_BASE,
149 .mmio_base = BSD3_RING_BASE,
157 .mmio_base = BSD4_RING_BASE,
281 reg.addr += hwe->mmio_base; in hw_engine_mmio_write32()
291 reg.addr += hwe->mmio_base; in hw_engine_mmio_read32()
450 hwe->mmio_base = info->mmio_base; in hw_engine_init_early()
[all …]
/linux/drivers/misc/vmw_vmci/
H A Dvmci_guest.c55 void __iomem *mmio_base; member
104 if (dev->mmio_base != NULL) in vmci_read_reg()
111 if (dev->mmio_base != NULL) in vmci_write_reg()
120 if (vmci_dev->mmio_base == NULL) in vmci_read_data()
152 if (dev->mmio_base != NULL) { in vmci_write_data()
607 if (!mmio_base) in vmci_guest_probe_device()
611 if (!mmio_base) { in vmci_guest_probe_device()
635 vmci_dev->mmio_base = mmio_base; in vmci_guest_probe_device()
639 if (mmio_base != NULL) { in vmci_guest_probe_device()
713 if (mmio_base != NULL) { in vmci_guest_probe_device()
[all …]
/linux/drivers/rtc/
H A Drtc-ep93xx.c30 void __iomem *mmio_base; member
40 comp = readl(ep93xx_rtc->mmio_base + EP93XX_RTC_SWCOMP); in ep93xx_rtc_get_swcomp()
58 time = readl(ep93xx_rtc->mmio_base + EP93XX_RTC_DATA); in ep93xx_rtc_read_time()
69 writel(secs + 1, ep93xx_rtc->mmio_base + EP93XX_RTC_LOAD); in ep93xx_rtc_set_time()
132 ep93xx_rtc->mmio_base = devm_platform_ioremap_resource(pdev, 0); in ep93xx_rtc_probe()
133 if (IS_ERR(ep93xx_rtc->mmio_base)) in ep93xx_rtc_probe()
134 return PTR_ERR(ep93xx_rtc->mmio_base); in ep93xx_rtc_probe()
/linux/drivers/thermal/intel/int340x_thermal/
H A Dprocessor_thermal_mbox.c29 data = readl(proc_priv->mmio_base + MBOX_OFFSET_INTERFACE); in wait_for_mbox_ready()
52 writel(data, (proc_priv->mmio_base + MBOX_OFFSET_DATA)); in send_mbox_write_cmd()
55 writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE)); in send_mbox_write_cmd()
73 writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE)); in send_mbox_read_cmd()
80 *resp = readl(proc_priv->mmio_base + MBOX_OFFSET_DATA); in send_mbox_read_cmd()
82 *resp = readq(proc_priv->mmio_base + MBOX_OFFSET_DATA); in send_mbox_read_cmd()
/linux/drivers/video/fbdev/mb862xx/
H A Dmb862xxfbdrv.c624 par->host = par->mmio_base; in mb862xx_gdc_init()
625 par->i2c = par->mmio_base + MB862XX_I2C_BASE; in mb862xx_gdc_init()
627 par->cap = par->mmio_base + MB862XX_CAP_BASE; in mb862xx_gdc_init()
629 par->geo = par->mmio_base + MB862XX_GEO_BASE; in mb862xx_gdc_init()
726 if (par->mmio_base == NULL) { in of_platform_mb862xx_probe()
772 iounmap(par->mmio_base); in of_platform_mb862xx_probe()
809 iounmap(par->mmio_base); in of_platform_mb862xx_remove()
846 par->host = par->mmio_base; in coralp_init()
1063 if (par->mmio_base == NULL) { in mb862xx_pci_probe()
1119 iounmap(par->mmio_base); in mb862xx_pci_probe()
[all …]
/linux/drivers/soundwire/
H A Dintel_init.c66 link->mmio_base = res->mmio_base; in intel_link_dev_register()
68 link->registers = res->mmio_base + SDW_LINK_BASE in intel_link_dev_register()
71 link->shim = res->mmio_base + res->shim_base; in intel_link_dev_register()
72 link->alh = res->mmio_base + res->alh_base; in intel_link_dev_register()
75 link->registers = res->mmio_base + SDW_IP_BASE(link_id); in intel_link_dev_register()
77 link->shim = res->mmio_base + SDW_SHIM2_GENERIC_BASE(link_id); in intel_link_dev_register()
78 link->shim_vs = res->mmio_base + SDW_SHIM2_VS_BASE(link_id); in intel_link_dev_register()
206 ctx->mmio_base = res->mmio_base; in sdw_intel_probe_controller()
/linux/drivers/net/ethernet/broadcom/
H A Dbgmac.c46 if (!ring->mmio_base) in bgmac_dma_tx_reset()
68 ring->mmio_base, val); in bgmac_dma_tx_reset()
77 ring->mmio_base); in bgmac_dma_tx_reset()
82 ring->mmio_base); in bgmac_dma_tx_reset()
225 ring->mmio_base); in bgmac_dma_tx_add()
294 if (!ring->mmio_base) in bgmac_dma_rx_reset()
303 ring->mmio_base); in bgmac_dma_rx_reset()
633 ring->mmio_base = ring_base[i]; in bgmac_dma_alloc()
642 ring->mmio_base); in bgmac_dma_alloc()
658 ring->mmio_base = ring_base[i]; in bgmac_dma_alloc()
[all …]
/linux/drivers/platform/mellanox/
H A Dmlxbf-pmc.c121 void __iomem *mmio_base; member
1118 pmcaddr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_l3_counter()
1123 pmcaddr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_l3_counter()
1175 addr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_crspace_counter()
1197 addr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_clear_crspace_counter()
1362 pmcaddr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_read_l3_event()
1367 pmcaddr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_read_l3_event()
1411 addr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_read_crspace_event()
1745 mlxbf_pmc_write(pmc->block[blk_num].mmio_base + in mlxbf_pmc_enable_store()
1986 pmc->block[i].mmio_base = in mlxbf_pmc_map_counters()
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